regdx_fis_pend_r;// waiting to send first DWORD of the H2D data transfer
regdx_fis_pend_r;// waiting to send first DWORD of the H2D data transfer
wiredx_dma_last_w;// sending last adat word
wiredx_dma_last_w;// sending last data word
regdx_busy_r;
regdx_busy_r;
reg[2:0]dx_err_r;
reg[2:0]dx_err_r;
regxmit_ok_r;
regxmit_ok_r;
...
@@ -168,16 +169,19 @@ module ahci_fis_transmit #(
...
@@ -168,16 +169,19 @@ module ahci_fis_transmit #(
wiredone_w=xmit_ok_r||((|dx_err_r)&&dx_busy_r)||dma_start;// done on last transmit or error
wiredone_w=xmit_ok_r||((|dx_err_r)&&dx_busy_r)||dma_start;// done on last transmit or error
regfetch_cmd_busy_r;
regfetch_cmd_busy_r;
regxfer_cntr_not_set;
regwatch_prd_end;
// now ahci_dma watches for the last data DWORD and generates last_h2d_data, so transmission will end if either of xfer counter or DMA data (defined by total prd size)
wiremasked_last_h2d_data=xfer_cntr_not_set&&last_h2d_data;// otherwise use xfer counter to find FIS end
// if xfer_cntr wazs 0, it will never be decremented and never equal to 1, will not generate last)
wirewatch_prd_end_w=masked_last_h2d_data||watch_prd_end;// Maybe not needed - just use watch_prd_end
// reg xfer_cntr_is_set;
// reg watch_prd_end;
// wire masked_last_h2d_data = xfer_cntr_not_set && last_h2d_data; // otherwise use xfer counter to find FIS end
// wire watch_prd_end_w = masked_last_h2d_data || watch_prd_end; // Maybe not needed - just use watch_prd_end
// reg [1:0] was_dma_re; // previous values of dma_re
// reg [1:0] was_dma_re; // previous values of dma_re
reg[2:0]was_dma_ndav;// inverted/masked previous values of dma_dav
// reg [2:0] was_dma_ndav; // inverted/masked previous values of dma_dav
assignfis_data_valid=ct_stb;// no wait write to output register 'todev_data', ct_re_r[0] is throttled according to FIFO room availability
/// assign fis_data_valid = ct_stb; // no wait write to output register 'todev_data', ct_re_r[0] is throttled according to FIFO room availability
// What else to wait for when
assignfis_data_valid=ct_stb||(!dma_ct_busy&&dx_fis_pend_r);// no wait write to output register 'todev_data', ct_re_r[0] is throttled according to FIFO room availability
assignct_re_w=todev_ready&&((cfis_acmd_left_r[4:1]!=0)||(cfis_acmd_left_r[0]&&!ct_re_r[0]));// Later add more sources
assignct_re_w=todev_ready&&((cfis_acmd_left_r[4:1]!=0)||(cfis_acmd_left_r[0]&&!ct_re_r[0]));// Later add more sources
/// assign write_or_w = (dma_en_r?(dma_dav && todev_ready && ()):fis_data_valid); // do not fill the buffer if FIFO is not ready for DMA,
/// assign write_or_w = (dma_en_r?(dma_dav && todev_ready ):fis_data_valid); // do not fill the buffer if FIFO is not ready for DMA,
assignwrite_or_w=(dma_en_r?(dma_dav&&todev_ready&&(!todev_full_r||watch_prd_end_w)):fis_data_valid);// do not fill the buffer if FIFO is not ready for DMA,
/// assign write_or_w = (dma_en_r?(dma_dav && todev_ready && (!todev_full_r || !watch_prd_end_w)):fis_data_valid); // do not fill the buffer if FIFO is not ready for DMA,
assignwrite_or_w=dma_re_w||fis_data_valid;
// When watching for FIS end, do not fill/use output register in the same cycle
// When watching for FIS end, do not fill/use output register in the same cycle
