eliminating use of PLL with GTX (cb2fc48f) · Commits · Elphel / x393_sata

.project

+17 −17

Original line number	Original line	Diff line number	Diff line
	@@ -52,87 +52,87 @@
	<link>		<link>
	<name>vivado_logs/VivadoBitstream.log</name>		<name>vivado_logs/VivadoBitstream.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160312151407716.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160312231527798.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOpt.log</name>		<name>vivado_logs/VivadoOpt.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160312151407716.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160312231527798.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPhys.log</name>		<name>vivado_logs/VivadoOptPhys.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160312151407716.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160312231527798.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPower.log</name>		<name>vivado_logs/VivadoOptPower.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160312151407716.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160312231527798.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoPlace.log</name>		<name>vivado_logs/VivadoPlace.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160312151407716.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160312231527798.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoRoute.log</name>		<name>vivado_logs/VivadoRoute.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160312151407716.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160312231527798.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoSynthesis.log</name>		<name>vivado_logs/VivadoSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160312151407716.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160312231356578.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160312151407716.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160312231527798.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160312151407716.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160312231356578.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportImplemented.log</name>		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160312151407716.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160312231527798.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportSynthesis.log</name>		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160312151407716.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160312231356578.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-opt-phys.dcp</name>		<name>vivado_state/x393_sata-opt-phys.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160312151407716.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160312231527798.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-opt-power.dcp</name>		<name>vivado_state/x393_sata-opt-power.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160312151407716.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160312231527798.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-opt.dcp</name>		<name>vivado_state/x393_sata-opt.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160312151407716.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160312231527798.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-place.dcp</name>		<name>vivado_state/x393_sata-place.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160312151407716.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160312231527798.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-route.dcp</name>		<name>vivado_state/x393_sata-route.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160312151407716.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160312231527798.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-synth.dcp</name>		<name>vivado_state/x393_sata-synth.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160312151407716.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160312231356578.dcp</location>
	</link>		</link>
	</linkedResources>		</linkedResources>
	</projectDescription>		</projectDescription>

host/gtx_wrap.v

+114 −312

Original line number	Original line	Diff line number	Diff line
	@@ -84,7 +84,7 @@ module gtx_wrap #(
	input wire txelecidle,		input wire txelecidle,
	output wire txp,		output wire txp,
	output wire txn,		output wire txn,
	output wire txoutclk,		output wire txoutclk, // global clock
	input wire txpcsreset,		input wire txpcsreset,
	output wire txresetdone,		output wire txresetdone,
	input wire txcominit,		input wire txcominit,
	@@ -108,7 +108,7 @@ module gtx_wrap #(

	output wire [1:0] txbufstatus,		output wire [1:0] txbufstatus,

	output xclk // just to measure frequency to set the local clock		output xclk // just to measure frequency to set the local clock (global clock)

	`ifdef USE_DATASCOPE		`ifdef USE_DATASCOPE
	// Datascope interface (write to memory that can be software-read)		// Datascope interface (write to memory that can be software-read)
	@@ -144,17 +144,9 @@ wire rxresetdone_gtx;
	wire txresetdone_gtx;		wire txresetdone_gtx;
	reg wrap_rxreset_;		reg wrap_rxreset_;
	reg wrap_txreset_;		reg wrap_txreset_;
	`ifdef OLD_ELASTIC
	reg rxresetdone_gtx_r;
	reg txresetdone_gtx_r;
	// resets while PCS resets, active low
	always @ (posedge rxusrclk2) wrap_rxreset_ <= rxuserrdy & rxresetdone_gtx_r;
	always @ (posedge txusrclk2) wrap_txreset_ <= txuserrdy & txresetdone_gtx_r;
	`else // OLD_ELASTIC
	// resets while PCS resets, active low		// resets while PCS resets, active low
	always @ (posedge rxusrclk2) wrap_rxreset_ <= rxuserrdy & rxresetdone_gtx;		always @ (posedge rxusrclk2) wrap_rxreset_ <= rxuserrdy & rxresetdone_gtx;
	always @ (posedge txusrclk2) wrap_txreset_ <= txuserrdy & txresetdone_gtx;		always @ (posedge txusrclk2) wrap_txreset_ <= txuserrdy & txresetdone_gtx;
	`endif // OLD_ELASTIC
	wire [63:0] rxdata_gtx;		wire [63:0] rxdata_gtx;
	wire [7:0] rxcharisk_gtx;		wire [7:0] rxcharisk_gtx;
	wire [7:0] rxdisperr_gtx;		wire [7:0] rxdisperr_gtx;
	@@ -561,158 +553,7 @@ gtx_10x8dec gtx_10x8dec(
	wire rxcomwakedet_gtx;		wire rxcomwakedet_gtx;
	wire rxcominitdet_gtx;		wire rxcominitdet_gtx;

	`ifdef OLD_ELASTIC

	// elastic buffer: transition from xclk to rxusrclk
	wire [15:0] rxdata_els_out;
	wire [1:0] rxcharisk_els_out;
	wire [1:0] rxnotintable_els_out;
	wire [1:0] rxdisperr_els_out;
	wire lword_strobe;
	wire isaligned;
	wire elastic_full;
	wire elastic_empty;

	gtx_elastic #(
	.DEPTH_LOG2 (3),
	.OFFSET (4)
	)
	gtx_elastic(
	// .rst (~rx_clocks_aligned), // ~wrap_rxreset_),
	.rst (~wrap_rxreset_),
	.wclk (xclk),
	.rclk (rxusrclk),

	/// .isaligned_in (state_aligned),
	// .isaligned_in (state_aligned && rxdlysresetdone_r), // input
	.isaligned_in (state_aligned), // input Moved clock phase reset/align to OOB module to handle
	.charisk_in (rxcharisk_dec_out),
	.notintable_in (rxnotintable_dec_out),
	.disperror_in (rxdisperr_dec_out),
	.data_in (rxdata_dec_out),

	.isaligned_out (isaligned),
	.charisk_out (rxcharisk_els_out),
	.notintable_out (rxnotintable_els_out),
	.disperror_out (rxdisperr_els_out),
	.data_out (rxdata_els_out),

	.lword_strobe (lword_strobe),

	.full (elastic_full),
	.empty (elastic_empty)
	);

	// iface resync
	reg rxcomwakedet_gtx_r;
	reg rxcominitdet_gtx_r;


	// insert resync if it's necessary
	generate
	if (DATA_BYTE_WIDTH == 4) begin
	// resync to rxusrclk
	// Fin = 2Fout => 2WIDTHin = WIDTHout
	// first data word arrived = last word of a primitive, second arrived - first one
	// lword_strobe indicates that second data word is arrived
	wire rxdata_resync_nempty;
	reg rxdata_resync_nempty_r;
	wire rxdata_resync_strobe;
	wire [50:0] rxdata_resync_in;
	wire [50:0] rxdata_resync_out;
	reg [25:0] rxdata_resync_buf;

	assign rxdata_resync_strobe = lword_strobe;
	assign rxdata_resync_in = {
	isaligned, // 1
	rxcomwakedet_gtx_r \| rxdata_resync_buf[25], // 1
	rxcominitdet_gtx_r \| rxdata_resync_buf[24], // 1
	rxresetdone_gtx_r, // 1
	txresetdone_gtx_r, // 1
	elastic_full \| rxdata_resync_buf[23], // 1
	elastic_empty \| rxdata_resync_buf[22], // 1
	rxdisperr_els_out, // 2
	rxnotintable_els_out, // 2
	rxcharisk_els_out, // 2
	rxdata_els_out, // 16
	rxdata_resync_buf[21:0]}; // 22 / 51 total
	always @ (posedge rxusrclk) begin
	/// rxdata_resync_buf <= ~wrap_rxreset_ ? 26'h0 : ~rxdata_resync_strobe ? {rxcomwakedet_gtx_r, rxcominitdet_gtx_r, elastic_full, elastic_empty, rxdisperr_els_out, rxnotintable_els_out, rxcharisk_els_out, rxdata_els_out} : rxdata_resync_buf;
	if (!wrap_rxreset_) rxdata_resync_buf <= 26'b0;
	else if (!rxdata_resync_strobe) rxdata_resync_buf <= {rxcomwakedet_gtx_r,
	rxcominitdet_gtx_r,
	elastic_full,
	elastic_empty,
	rxdisperr_els_out,
	rxnotintable_els_out,
	rxcharisk_els_out,
	rxdata_els_out};
	end
	always @ (posedge rxusrclk2)
	rxdata_resync_nempty_r <= rxdata_resync_nempty;

	fifo_cross_clocks #(
	.DATA_WIDTH (51),
	.DATA_DEPTH (4)
	)
	rxdata_resynchro(
	// .rst (~wrap_rxreset_),
	.rst (1'b0),
	.rrst (~wrap_rxreset_),
	.wrst (~wrap_rxreset_),
	.rclk (rxusrclk2),
	.wclk (rxusrclk),
	.we (rxdata_resync_strobe),
	.re (rxdata_resync_nempty & rxdata_resync_nempty_r),
	.data_in (rxdata_resync_in),
	.data_out (rxdata_resync_out),
	.nempty (rxdata_resync_nempty),
	.half_empty ()
	);
	assign rxbyteisaligned = rxdata_resync_out[50];
	assign rxcomwakedet = rxdata_resync_out[49];
	assign rxcominitdet = rxdata_resync_out[48];
	assign rxresetdone = rxdata_resync_out[47];
	assign txresetdone = rxdata_resync_out[46];
	assign rxelsfull = rxdata_resync_out[45];
	assign rxelsempty = rxdata_resync_out[44];
	assign rxdisperr[3:0] = {rxdata_resync_out[43:42], rxdata_resync_out[21:20]};
	assign rxnotintable[3:0] = {rxdata_resync_out[41:40], rxdata_resync_out[19:18]};
	assign rxcharisk[3:0] = {rxdata_resync_out[39:38], rxdata_resync_out[17:16]};
	assign rxdata[31:0] = {rxdata_resync_out[37:22], rxdata_resync_out[15:0] };
	end else if (DATA_BYTE_WIDTH == 2) begin
	// no resync is needed => straightforward assignments
	assign rxbyteisaligned = isaligned;
	assign rxcomwakedet = rxcomwakedet_gtx_r;
	assign rxcominitdet = rxcominitdet_gtx_r;
	assign rxresetdone = rxresetdone_gtx_r;
	assign txresetdone = txresetdone_gtx_r;
	assign rxelsfull = elastic_full;
	assign rxelsempty = elastic_empty;
	assign rxdisperr[1:0] = rxdisperr_els_out;
	assign rxnotintable[1:0] = rxnotintable_els_out;
	assign rxcharisk[1:0] = rxcharisk_els_out;
	assign rxdata[15:0] = rxdata_els_out;
	end
	else begin
	// unconsidered case
	always @ (posedge txusrclk)
	begin
	$display("Wrong width set in %m, value is %d", DATA_BYTE_WIDTH);
	end
	end
	endgenerate

	// latching gtx outputs, synchronous to RXUSRCLK2 = rxusrclk
	always @ (posedge rxusrclk)
	begin
	rxcomwakedet_gtx_r <= rxcomwakedet_gtx;
	rxcominitdet_gtx_r <= rxcominitdet_gtx;
	rxresetdone_gtx_r <= rxresetdone_gtx;
	txresetdone_gtx_r <= txresetdone_gtx;
	end

	`else // OLD_ELASTIC
	elastic1632 #(		elastic1632 #(
	.DEPTH_LOG2 (ELASTIC_DEPTH), // 16 //4),		.DEPTH_LOG2 (ELASTIC_DEPTH), // 16 //4),
	.OFFSET (ELASTIC_OFFSET) // 10 //5)		.OFFSET (ELASTIC_OFFSET) // 10 //5)
	@@ -843,63 +684,24 @@ wire rxcominitdet_gtx;
	.out_pulse (rxcomwakedet), // output		.out_pulse (rxcomwakedet), // output
	.busy () // output		.busy () // output
	);		);


	//rxusrclk2

	`endif //OLD_ELASTIC
	wire txoutclk_gtx;		wire txoutclk_gtx;
	wire xclk_gtx;		wire xclk_gtx;
	//wire xclk_mr;
	BUFG bufg_txoutclk (.O(txoutclk),.I(txoutclk_gtx));
	//BUFR bufr_xclk (.O(xclk),.I(xclk_mr),.CE(1'b1),.CLR(1'b0));
	//BUFMR bufmr_xclk (.O(xclk_mr),.I(xclk_gtx));
	`ifdef USE_DRP
	wire xclk_gtx_g;

	`ifdef STRAIGHT_XCLK
	BUFH BUFH_i (
	.O(), // output
	.I() // input
	);
	/* Instance template for module clock_inverter */
	clock_inverter clock_inverter_i (
	.rst (),
	.clk_in (), // input
	.invert (), // input
	.clk_out() // output
	);

	BUFG bug_xclk (.O(xclk),.I(xclk_gtx));
	`else
	BUFH bufr_xclk (.O (xclk_gtx_g),
	.I (xclk_gtx));

	clock_inverter bug_xclk (
	.rst (rxreset),
	.clk_in (xclk_gtx_g), // input
	.invert (other_control[15]), // input other_control[15] inverts xclk phase
	.clk_out (xclk)); // output
	`endif


	`else		select_clk_buf #(
	// VDT bug - incorrectly processes defines when calculating closure		.BUFFER_TYPE("BUFG")
	BUFH BUFH_i (		) bufg_txoutclk (
	.O(), // output		.o (txoutclk), // output
	.I() // input		.i (txoutclk_gtx), // input
			.clr (1'b0) // input
	);		);
	/* Instance template for module clock_inverter */		select_clk_buf #(
	clock_inverter clock_inverter_i (		.BUFFER_TYPE("BUFG")
	.rst (),		) bug_xclk (
	.clk_in (), // input		.o (xclk), // output
	.invert (), // input		.i (xclk_gtx), // input
	.clk_out() // output		.clr (1'b0) // input
	);		);

	BUFG bug_xclk (.O(xclk),.I(xclk_gtx));
	`endif

	gtxe2_channel_wrapper #(		gtxe2_channel_wrapper #(
	.SIM_RECEIVER_DETECT_PASS ("TRUE"),		.SIM_RECEIVER_DETECT_PASS ("TRUE"),
	.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),		.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),

host/sata_phy.v

+83 −69

Original line number	Original line	Diff line number	Diff line
	@@ -227,7 +227,7 @@ wire txp;
	wire txn;		wire txn;
	wire rxp;		wire rxp;
	wire rxn;		wire rxn;
	wire txoutclk;		wire txoutclk; // comes out global from gtx_wrap
	wire txpmareset_done;		wire txpmareset_done;
	wire rxeyereset_done;		wire rxeyereset_done;

	@@ -377,7 +377,7 @@ always @ (posedge clk or posedge extrst)
	`endif // OLD_TXPCSRESET		`endif // OLD_TXPCSRESET


	// issue rx reset to restore functionality after oob sequence. Let it lasts 8 clock lycles		// issue rx reset to restore functionality after oob sequence. Let it last 8 clock cycles
	reg [3:0] rxreset_oob_cnt;		reg [3:0] rxreset_oob_cnt;
	wire rxreset_oob_stop;		wire rxreset_oob_stop;

	@@ -395,17 +395,20 @@ always @ (posedge clk or posedge extrst)
	* USRCLKs generation. USRCLK @ 150MHz, same as TXOUTCLK; USRCLK2 @ 75Mhz -> sata_clk === sclk		* USRCLKs generation. USRCLK @ 150MHz, same as TXOUTCLK; USRCLK2 @ 75Mhz -> sata_clk === sclk
	* It's recommended to use MMCM instead of PLL, whatever		* It's recommended to use MMCM instead of PLL, whatever
	*/		*/
	wire usrpll_fb_clk;
	wire usrclk;
	wire usrclk2;

	wire usrclk_global;		wire usrclk_global;
	BUFG bufg_usrclk (.O(usrclk_global),.I(usrclk));		wire usrclk2;
	assign txusrclk = usrclk_global; // 150MHz		//`define GTX_USE_PLL
	assign txusrclk2 = clk; // usrclk2; // should not use non-buffered clock!		`ifdef GTX_USE_PLL
	assign rxusrclk = usrclk_global; // 150MHz		wire usrpll_fb_clk;
	assign rxusrclk2 = clk; // usrclk2; // should not use non-buffered clock!		wire usrclk;
			select_clk_buf #(
			.BUFFER_TYPE("BUFG")
			) bufg_usrclk (
			.o (usrclk_global), // output
			.i (usrclk), // input
			.clr (1'b0) // input
			);
	PLLE2_ADV #(		PLLE2_ADV #(
	.BANDWIDTH ("OPTIMIZED"),		.BANDWIDTH ("OPTIMIZED"),
	.CLKFBOUT_MULT (8),		.CLKFBOUT_MULT (8),
	@@ -418,18 +421,6 @@ PLLE2_ADV #(
	.CLKOUT1_DIVIDE (16),		.CLKOUT1_DIVIDE (16),
	.CLKOUT1_DUTY_CYCLE (0.500),		.CLKOUT1_DUTY_CYCLE (0.500),
	.CLKOUT1_PHASE (0.000),		.CLKOUT1_PHASE (0.000),
	/* .CLKOUT2_DIVIDE = 1,
	.CLKOUT2_DUTY_CYCLE = 0.500,
	.CLKOUT2_PHASE = 0.000,
	.CLKOUT3_DIVIDE = 1,
	.CLKOUT3_DUTY_CYCLE = 0.500,
	.CLKOUT3_PHASE = 0.000,
	.CLKOUT4_DIVIDE = 1,
	.CLKOUT4_DUTY_CYCLE = 0.500,
	.CLKOUT4_PHASE = 0.000,
	.CLKOUT5_DIVIDE = 1,
	.CLKOUT5_DUTY_CYCLE = 0.500,
	.CLKOUT5_PHASE = 0.000,*/
	.COMPENSATION ("ZHOLD"),		.COMPENSATION ("ZHOLD"),
	.DIVCLK_DIVIDE (1),		.DIVCLK_DIVIDE (1),
	.IS_CLKINSEL_INVERTED (1'b0),		.IS_CLKINSEL_INVERTED (1'b0),
	@@ -463,6 +454,31 @@ usrclk_pll(
	.PWRDWN (1'b0),		.PWRDWN (1'b0),
	.RST (~cplllock)		.RST (~cplllock)
	);		);
			`else // GTX_USE_PLL
			// divide txoutclk (global) by 2, then make global. Does not need to be phase-aligned - will use FIFO
			reg usrclk2_r;
			always @ (posedge txoutclk) begin
			if (~cplllock) usrclk2_r <= 0;
			else usrclk2_r <= ~usrclk2;
			end
			assign txusrclk = txoutclk; // 150MHz, was already global
			assign usrclk_global = txoutclk; // 150MHz, was already global
			assign usrclk2 = usrclk2_r;
			assign usrpll_locked = cplllock;
			`endif // else // GTX_USE_PLL

			assign txusrclk = usrclk_global; // 150MHz
			assign txusrclk2 = clk; // usrclk2;
			assign rxusrclk = usrclk_global; // 150MHz
			assign rxusrclk2 = clk; // usrclk2;

			select_clk_buf #(
			.BUFFER_TYPE("BUFG")
			) bufg_sclk (
			.o (clk), // output
			.i (usrclk2), // input
			.clr (1'b0) // input
			);

	/*		/*
	* Padding for an external input clock @ 150 MHz		* Padding for an external input clock @ 150 MHz
	@@ -528,7 +544,7 @@ gtx_wrap
	.txelecidle (txelecidle), // input wire		.txelecidle (txelecidle), // input wire
	.txp (txp), // output wire		.txp (txp), // output wire
	.txn (txn), // output wire		.txn (txn), // output wire
	.txoutclk (txoutclk), // output wire		.txoutclk (txoutclk), // output wire // made global inside
	.txpcsreset (txpcsreset), // input wire		.txpcsreset (txpcsreset), // input wire
	.txresetdone (txresetdone), // output wire		.txresetdone (txresetdone), // output wire
	.txcominit (txcominit), // input wire		.txcominit (txcominit), // input wire
	@@ -547,7 +563,7 @@ gtx_wrap
	.dbg_rxcdrlock (dbg_rxcdrlock) ,		.dbg_rxcdrlock (dbg_rxcdrlock) ,
	.dbg_rxdlysresetdone(dbg_rxdlysresetdone),		.dbg_rxdlysresetdone(dbg_rxdlysresetdone),
	.txbufstatus (txbufstatus[1:0]),		.txbufstatus (txbufstatus[1:0]),
	.xclk (xclk) // output receive clock, just to measure frequency		.xclk (xclk) // output receive clock, just to measure frequency // global
	`ifdef USE_DATASCOPE		`ifdef USE_DATASCOPE
	,.datascope_clk (datascope_clk), // output		,.datascope_clk (datascope_clk), // output
	.datascope_waddr (datascope_waddr), // output[9:0]		.datascope_waddr (datascope_waddr), // output[9:0]
	@@ -580,8 +596,6 @@ gtx_wrap
	assign cplllockdetclk = reliable_clk; //gtrefclk;		assign cplllockdetclk = reliable_clk; //gtrefclk;
	assign drpclk = reliable_clk; //gtrefclk;		assign drpclk = reliable_clk; //gtrefclk;

	//assign clk = usrclk2;
	BUFG bufg_sclk (.O(clk),.I(usrclk2));
	assign rxn = rxn_in;		assign rxn = rxn_in;
	assign rxp = rxp_in;		assign rxp = rxp_in;
	assign txn_out = txn;		assign txn_out = txn;

system_defines.vh

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -3,7 +3,7 @@
	`define SYSTEM_DEFINES		`define SYSTEM_DEFINES
	`define USE_DRP		`define USE_DRP
	`define ALIGN_CLOCKS		`define ALIGN_CLOCKS
	`define STRAIGHT_XCLK		// `define STRAIGHT_XCLK
	`define USE_DATASCOPE		`define USE_DATASCOPE
	// `define DATASCOPE_INCOMING_RAW		// `define DATASCOPE_INCOMING_RAW
	`define PRELOAD_BRAMS		`define PRELOAD_BRAMS

top.v

+27 −6

Original line number	Original line	Diff line number	Diff line
	@@ -40,7 +40,7 @@
	`include "system_defines.vh"		`include "system_defines.vh"

	module top #(		module top #(
	//`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - partially used		`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - partially used
	)		)
	(		(
	// sata serial data iface		// sata serial data iface
	@@ -149,11 +149,31 @@ always @(posedge comb_rst or posedge axi_aclk0) begin
	else axi_rst_pre <= 1'b0;		else axi_rst_pre <= 1'b0;
	end		end

	//BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(/fclk[0]/ sclk));		select_clk_buf #(
	//assign axi_aclk = sclk;		.BUFFER_TYPE("BUFG")
	BUFG bufg_axi_aclk0_i (.O(axi_aclk0),.I(fclk[0]));		) bufg_axi_aclk0_i (
	BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));		.o (axi_aclk0), // output
	BUFG bufg_extrst_i (.O(extrst),.I(axi_rst_pre));		.i (fclk[0]), // input
			.clr (1'b0) // input
			);

			select_clk_buf #(
			.BUFFER_TYPE("BUFG")
			) bufg_axi_rst_i (
			.o (axi_rst), // output
			.i (axi_rst_pre), // input
			.clr (1'b0) // input
			);

			select_clk_buf #(
			.BUFFER_TYPE("BUFG")
			) bufg_extrst_i (
			.o (extrst), // output
			.i (axi_rst_pre), // input
			.clr (1'b0) // input
			);


	axi_hp_clk #(		axi_hp_clk #(
	.CLKIN_PERIOD(20.000),		.CLKIN_PERIOD(20.000),
	.CLKFBOUT_MULT_AXIHP(18),		.CLKFBOUT_MULT_AXIHP(18),
	@@ -164,6 +184,7 @@ axi_hp_clk #(
	.clk_axihp (hclk), // output		.clk_axihp (hclk), // output
	.locked_axihp () // output // not controlled?		.locked_axihp () // output // not controlled?
	);		);

	sata_ahci_top sata_top(		sata_ahci_top sata_top(
	.sata_clk (sclk),		.sata_clk (sclk),
	// reliable clock to source drp and cpll lock det circuits		// reliable clock to source drp and cpll lock det circuits

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