From ca5c6e3221f5f5c6ae1f2aa8e5b3d87fd6f5a10f Mon Sep 17 00:00:00 2001 From: Andrey Filippov Date: Sat, 23 Jan 2016 17:43:14 -0700 Subject: [PATCH] simulating/debugging --- ahci/ahci_fis_receive.v | 2 +- ahci/ahci_fsm.v | 11 ++- device/sata_device.v | 53 +++++++++++-- device/sata_phy_dev.v | 16 ++-- tb/tb_ahci.tf | 21 ++++- tb_ahci_01.sav | 165 ++++++++++++++++++++++++++++++++++++---- x393 | 2 +- 7 files changed, 235 insertions(+), 35 deletions(-) diff --git a/ahci/ahci_fis_receive.v b/ahci/ahci_fis_receive.v index 1bfc424..1a1bfbe 100644 --- a/ahci/ahci_fis_receive.v +++ b/ahci/ahci_fis_receive.v @@ -325,7 +325,7 @@ localparam DATA_TYPE_ERR = 3; if (store_sig[1]) sig_r[31:8] <= hba_data_in[23:0]; if (store_sig[3]) sig_r[ 7:0] <= hba_data_in[ 7:0]; - if (reg_d2h) tf_err_sts <= hba_data_in[15:0]; + if (reg_d2h) tf_err_sts <= hba_data_in[31:16]; // 15:0]; // Sets pPioErr[pPmpCur] to Error field of the FIS // Updates PxTFD.STS.ERR with pPioErr[pPmpCur] ?? else if (reg_ps[0]) tf_err_sts <= {hba_data_in[31:24],hba_data_in[23:16]}; diff --git a/ahci/ahci_fsm.v b/ahci/ahci_fsm.v index 54b4d65..1318ca5 100644 --- a/ahci/ahci_fsm.v +++ b/ahci/ahci_fsm.v @@ -255,6 +255,7 @@ module ahci_fsm // reg jump_r; reg [2:0] fsm_jump; wire fsm_next; + reg fsm_next_r; reg fsm_actions; // processing actions reg fsm_act_busy; reg [1:0] fsm_transitions; // processing transitions @@ -277,6 +278,7 @@ module ahci_fsm reg [1:0] phy_ready_prev; // previous state of phy_ready / speed reg phy_ready_chng_r; // pulse when phy_ready changes wire phy_ready_chng_w = !hba_rst && !was_rst && (phy_ready != phy_ready_prev); + reg was_last_action_r; // delay last action if it was fsm_wait_act; assign fsm_next = (fsm_preload || (fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]) && !async_pend_r[0]; // quiet if received cominit is pending assign update_all = fsm_jump[0]; @@ -334,11 +336,12 @@ module ahci_fsm else if (fsm_jump[2]) fsm_actions <= 1; else if (fsm_last_act_w && fsm_next) fsm_actions <= 0; + if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w; - - if (hba_rst || pre_jump_w) fsm_transitions <= 0; - else if (fsm_last_act_w && fsm_actions && fsm_next) fsm_transitions <= 1; - else fsm_transitions <= {fsm_transitions[0],fsm_transitions[0]}; + if (hba_rst || pre_jump_w) fsm_transitions <= 0; + else if ((fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) || + (fsm_act_busy && fsm_act_done && was_last_action_r) ) fsm_transitions <= 1; + else fsm_transitions <= {fsm_transitions[0],fsm_transitions[0]}; if (hba_rst) fsm_preload <= 0; else fsm_preload <= |fsm_jump[1:0]; diff --git a/device/sata_device.v b/device/sata_device.v index 8aaf1e6..7458f97 100644 --- a/device/sata_device.v +++ b/device/sata_device.v @@ -41,6 +41,7 @@ module sata_device( input wire EXTCLK_P, input wire EXTCLK_N ); +`include "includes/fis_types.vh" //`ifdef SIMULATION reg [639:0] DEV_TITLE; // to show human-readable state in the GTKWave // reg [31:0] DEV_DATA; @@ -58,6 +59,8 @@ wire dev_rst; reg [31:0] dev2phy_data = 32'hB5B5957C; // SYNCP reg [3:0] dev2phy_isk = 4'h1; +reg [2:0] phy_ready_syncp_r; // allow device to send 3 SYNCp before getting ready + sata_phy_dev phy( // pll reset .extrst (rst), @@ -128,6 +131,8 @@ reg [31:0] receive_crc; integer receive_id = 0; integer receive_status = 0; + + /* * Monitor incoming primitives every clock cycle * if there is a data transfer request, start a receive sequence @@ -288,7 +293,7 @@ function tranCheckFIS; //SuppressThisWarning VEditor: VDT bug - the function is begin // $display("[Device] TRANSPORT: Says the FIS is valid"); DEV_TITLE = "Says the FIS is valid"; - $display("[Device] TRANSPORT: %s @%t", DEV_TITLE, $time); + $display("[Device] TRANSPORT: %s @%t", DEV_TITLE, $time); tranCheckFIS = 0; // always tell LL the FIS os OK end @@ -634,9 +639,43 @@ endtask -reg [31:0] transmit_data [2047:0]; +reg [31:0] transmit_data [2047:0]; // @SuppressThisWarning VEditor - Assigned in testbench reg [31:0] transmit_data_pause [2047:0]; -reg [31:0] transmit_crc; // never assigned +reg [31:0] transmit_crc; // never assigned // @SuppressThisWarning VEditor - Assigned in testbench +task clear_transmit_pause; // @SuppressThisWarning VEditor - Used in testbench + input [31:0] pause_val; + integer i; + begin + for (i = 0; i < 2048; i = i + 1) begin + transmit_data_pause[i] = pause_val; + end + end +endtask + +// Wait for device phy ready (full COMRESET/COMINIT sequence) and wait to send several SYNCp primitives so host knows it is done +task wait_ready; // @SuppressThisWarning VEditor - Used in testbench + input integer num_syncp; + begin + wait (phy_ready); + repeat(num_syncp + 1) @(posedge clk); + end +endtask + +task send_good_status; // @SuppressThisWarning VEditor - Used in testbench + input integer id; + input [2:0] dev_specific_status_bits; + input irq; + output integer status; + begin + transmit_data[0] = FIS_D2HR | (irq? 'h4000:0) | (dev_specific_status_bits << 20) | 'h1000000; + transmit_data[1] = 1; + transmit_data[2] = 0; + transmit_data[3] = 1; + transmit_data[4] = 0; + linkTransmitFIS(id, 5, 0, status); +// linkTransmitFIS ( + end +endtask /* * Transmits data to a host. ~Link Transmit FSM * Correct execution, as it shall be w/o errors from a device side. (except timeouts and data consistency, see below) @@ -661,7 +700,7 @@ reg [31:0] transmit_crc; // never assigned * b) Scrambler messed up * c) There is an error in the host */ -task linkTransmitFIS; +task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench input integer id; input integer size; // dwords count input integer transmit_custom_crc; @@ -900,7 +939,7 @@ endtask // checks, if it is data coming from the host function [0:0] linkIsData; - input dummy; + input dummy; // @SuppressThisWarning VEditor - unused (is it for some simulator?) begin if (|phy2dev_charisk) linkIsData = 1; @@ -912,7 +951,7 @@ endfunction // obvious function [31:0] linkGetData; // TODO non-even word count - input dummy; + input dummy; // @SuppressThisWarning VEditor - unused (is it for some simulator?) begin linkGetData = phy2dev_data; end @@ -922,7 +961,7 @@ endfunction * Return value is a string containing its name! */ function [112:0] linkGetPrim; - input integer dummy; + input integer dummy; // @SuppressThisWarning VEditor - unused (is it for some simulator?) reg [112:0] type; begin if (~|phy2dev_charisk) begin diff --git a/device/sata_phy_dev.v b/device/sata_phy_dev.v index ff115e8..bf519ea 100644 --- a/device/sata_phy_dev.v +++ b/device/sata_phy_dev.v @@ -79,10 +79,10 @@ wire [7:0] rxdisperr; wire [7:0] rxdisperr_gtx; wire [7:0] rxnotintable; wire [7:0] rxnotintable_gtx; -wire [31:0] rxdata_out; -wire [31:0] txdata_in; -wire [3:0] txcharisk_in; -wire [3:0] rxcharisk_out; +//wire [31:0] rxdata_out; +//wire [31:0] txdata_in; +//wire [3:0] txcharisk_in; +//wire [3:0] rxcharisk_out; wire rxcomwakedet; wire rxcominitdet; @@ -763,9 +763,9 @@ assign rxn = rxn_in; assign rxp = rxp_in; assign txn_out = txn; assign txp_out = txp; -assign ll_data_out = rxdata_out; -assign ll_charisk_out = rxcharisk_out; -assign txdata_in = ll_data_in; -assign txcharisk_in = ll_charisk_in; +//assign ll_data_out = rxdata_out; +//assign ll_charisk_out = rxcharisk_out; +//assign txdata_in = ll_data_in; +//assign txcharisk_in = ll_charisk_in; endmodule diff --git a/tb/tb_ahci.tf b/tb/tb_ahci.tf index e068dbc..2184c14 100644 --- a/tb/tb_ahci.tf +++ b/tb/tb_ahci.tf @@ -67,6 +67,9 @@ reg [639:0] TESTBENCH_TITLE = "RESET"; // to show human-readable state in the GT reg [31:0] TESTBENCH_DATA; reg [11:0] TESTBENCH_ID; +reg [639:0] DEVICE_TITLE = "RESET"; // to show human-readable state in the GTKWave +reg [31:0] DEVICE_DATA; +reg [11:0] Device_ID; initial #1 $display("HI THERE"); initial @@ -639,7 +642,7 @@ localparam MAXIGP1 = 32'h80000000; // Start of the MAXIGP1 address range (use ah endtask -initial begin +initial begin //Host wait (!RST); //reg [639:0] TESTBENCH_TITLE = "RESET"; // to show human-readable state in the GTKWave TESTBENCH_TITLE = "NO_RESET"; @@ -658,6 +661,22 @@ initial begin end +integer status; +initial begin //Device + dev.clear_transmit_pause(0); +// dev.linkTransmitFIS(66, 5, 0, status); +// wait (dev.phy_ready); + dev.wait_ready(3); + DEVICE_TITLE = "NO_RESET"; + $display("[Dev-TB]: %s @%t", DEVICE_TITLE, $time); + dev.send_good_status (66, // input integer id; + 5, // input [2:0] dev_specific_status_bits; + 1, // input irq; + status); // output integer status; + DEVICE_TITLE = "Device sent D2H RS"; + $display("[Dev-TB]: %s, status = 0x%x @%t", DEVICE_TITLE, status, $time); + +end initial begin // #30000; #50000; diff --git a/tb_ahci_01.sav b/tb_ahci_01.sav index 29a7cc9..397abd6 100644 --- a/tb_ahci_01.sav +++ b/tb_ahci_01.sav @@ -1,34 +1,39 @@ [*] [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI -[*] Sat Jan 23 07:05:52 2016 +[*] Sat Jan 23 23:40:23 2016 [*] -[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160122235411900.fst" -[dumpfile_mtime] "Sat Jan 23 06:55:08 2016" -[dumpfile_size] 6269364 +[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160123162627844.fst" +[dumpfile_mtime] "Sat Jan 23 23:27:24 2016" +[dumpfile_size] 6302723 [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav" -[timestart] 0 -[size] 1823 1173 -[pos] 1942 0 -*-21.079729 6065536 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[timestart] 15250600 +[size] 1823 1180 +[pos] 1951 0 +*-16.074623 15525400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] tb_ahci. +[treeopen] tb_ahci.dev. +[treeopen] tb_ahci.dev.phy. [treeopen] tb_ahci.dut. [treeopen] tb_ahci.dut.axi_hp_clk_i. [treeopen] tb_ahci.dut.sata_top. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy. +[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl. [treeopen] tb_ahci.dut.sata_top.ahci_top_i. [treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i. [treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i. [treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i. -[sst_width] 402 -[signals_width] 245 +[sst_width] 275 +[signals_width] 249 [sst_expanded] 1 -[sst_vpaned_height] 621 +[sst_vpaned_height] 625 @820 tb_ahci.TESTBENCH_TITLE[639:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0] +tb_ahci.DEVICE_TITLE[639:0] +tb_ahci.dev.DEV_TITLE[639:0] @28 tb_ahci.CLK tb_ahci.RST @@ -81,9 +86,30 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.reliable_clk tb_ahci.dut.sata_top.ahci_sata_layers_i.extclk_n tb_ahci.dut.sata_top.ahci_sata_layers_i.rst tb_ahci.dut.sata_top.ahci_sata_layers_i.clk +tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_d2h_valid +tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_d2h_almost_full +@22 +tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_fill[9:0] +@c00028 +tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_fifo_re_regen[1:0] +@28 +(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_fifo_re_regen[1:0] +(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_fifo_re_regen[1:0] +@1401200 +-group_end +@800200 +-fifo_d2h_control +@28 +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.rst +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.rd +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.wr +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.ramo_full +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.mem_re +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.mem_regen @200 - @1000200 +-fifo_d2h_control -ahci_sata_layers @800200 -ahci_top @@ -91,6 +117,22 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.clk tb_ahci.dut.sata_top.ahci_top_i.port_arst tb_ahci.dut.sata_top.ahci_top_i.hba_arst tb_ahci.dut.sata_top.ahci_top_i.phy_ready[1:0] +tb_ahci.dut.sata_top.ahci_top_i.irq +@800022 +tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0] +@28 +(0)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0] +(1)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0] +(2)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0] +(3)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0] +(4)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0] +(5)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0] +(6)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0] +(7)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0] +@23 +tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0] +@1001200 +-group_end @1000200 -ahci_top @800200 @@ -128,9 +170,19 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0] @28 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_preload tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_actions +@800028 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_transitions[1:0] +@28 +(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_transitions[1:0] +(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_transitions[1:0] +@1001200 +-group_end +@28 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_next tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_wait_act_w +tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.update_busy +tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_act_busy +tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_act_done tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_last_act_w tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.cond_met_w tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pre_jump_w @@ -142,10 +194,13 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0] (0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0] (1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0] (2)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0] +tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_pre_act_w @1001200 -group_end @200 - +@800200 +-actions @28 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pfsm_started tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pxci0_clear @@ -156,6 +211,12 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.comreset_send tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.set_sts_80 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.ssts_det_dnp tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.sirq_PC +tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.get_rfis +tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.update_sig +tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.update_err_sts +@1000200 +-actions +@28 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.serr_diag_X @200 - @@ -180,9 +241,45 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st -ahci_fsm @800200 -link -@200 -- +@28 +tb_ahci.dut.sata_top.ahci_sata_layers_i.phy_speed[1:0] +tb_ahci.dut.sata_top.ahci_sata_layers_i.phy_ready +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_ready +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.link_reset +@22 +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_data_in[31:0] +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_isk_in[3:0] +@28 +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.dword_val +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_busy_in +@800200 +-states +@28 +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_align +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_idle +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_nocomm +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_nocommerr +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_badend +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_data +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_eof +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_goodcrc +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_goodend +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_rdy +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_rhold +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_shold +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_wait +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_reset +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_crc +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_data +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_eof +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_rdy +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_rhold +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_shold +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_sof +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_sync_esc +tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_wait @1000200 +-states -link @800200 -phy @@ -223,6 +320,16 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxresetdone tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txresetdone tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_ready tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txreset +@200 +- +@22 +tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxdata[31:0] +tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.ll_data_out[31:0] +tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.ll_charisk_out[3:0] +@200 +- +@22 +tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txdata[31:0] @1000200 -phy @800200 @@ -246,9 +353,41 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cplllock tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cplllockdetclk tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txelecidle tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txelecidle_gtx +@800200 +-gtx8x10enc +@28 +tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.wrap_txreset_ +tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_8x10enc.rst +@22 +tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_in[15:0] +@28 +tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txcharisk_enc_in[1:0] +@22 +tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0] @200 - @1000200 +-gtx8x10enc -gtx +@800200 +-device +@28 +tb_ahci.dev.phy_ready +@22 +tb_ahci.dev.phy2dev_err[3:0] +@800200 +-dev_phy +@28 +tb_ahci.dev.phy.rst_r +@22 +tb_ahci.dev.phy.txdata[31:0] +tb_ahci.dev.phy.ll_data_out[31:0] +tb_ahci.dev.phy.ll_data_in[31:0] +tb_ahci.dev.phy.ll_charisk_in[3:0] +@200 +- +@1000200 +-dev_phy +-device [pattern_trace] 1 [pattern_trace] 0 diff --git a/x393 b/x393 index ae1f1eb..7e2f1a0 160000 --- a/x393 +++ b/x393 @@ -1 +1 @@ -Subproject commit ae1f1eb4725bc03ac56bd4e06b058b59d716e677 +Subproject commit 7e2f1a070b2f984169270fc4564145f6ed7a8e42 -- 2.18.1