Started FIS -> AXI FIFO module

c11c0ad4 · Andrey Filippov · e2fb6292 · c11c0ad4 · c11c0ad4
Commit c11c0ad4 authored Jan 03, 2016 by Andrey Filippov
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ahci_dma_rd_fifo.v utils/ahci_dma_rd_fifo.v +2 -2

ahci_dma_wr_fifo.v utils/ahci_dma_wr_fifo.v +277 -0

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--- a/utils/ahci_dma_rd_fifo.v
+++ b/utils/ahci_dma_rd_fifo.v
 /*******************************************************************************
 * Module: ahci_dma_rd_fifo
 * Date:2016-01-01  
- * Author: andrey     
+ * Author: Andrey Filippov
 * Description: cross clocks,  word-realign, 64->32
 * Convertion from x64 QWORD-aligned AXI data @hclk to
 * 32-bit word-aligned data at mclk
@@ -135,7 +135,7 @@ module  ahci_dma_rd_fifo#(
    end
-    always @ (posedge hclk) begin
+    always @ (posedge mclk) begin
        hrst_mclk <= hrst;
        if    (hrst_mclk)             raddr <= 0;

--- a/utils/ahci_dma_wr_fifo.v
+++ b/utils/ahci_dma_wr_fifo.v