GTX parallel logic is implemented externally (bcfe20f6) · Commits · Elphel / x393_sata

device/sata_phy_dev.v

+4 −1

Original line number	Original line	Diff line number	Diff line
	@@ -19,7 +19,10 @@
	* along with this program. If not, see <http://www.gnu.org/licenses/> .		* along with this program. If not, see <http://www.gnu.org/licenses/> .
	*******************************************************************************/		*******************************************************************************/
	`include "oob_dev.v"		`include "oob_dev.v"
	module sata_phy_dev(		module sata_phy_dev #(
			parameter DATA_BYTE_WIDTH = 4
			)
			(
	// initial reset, resets PLL. After pll is locked, an internal sata reset is generated.		// initial reset, resets PLL. After pll is locked, an internal sata reset is generated.
	input wire extrst,		input wire extrst,
	// sata clk, generated in pll as usrclk2		// sata clk, generated in pll as usrclk2

dma/axi_regs.v

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -88,7 +88,7 @@ axibram_write #(
	)		)
	axibram_write(		axibram_write(
	.aclk (ACLK),		.aclk (ACLK),
	.rst (ARESETN),		.arst (ARESETN),
	.awaddr (AWADDR),		.awaddr (AWADDR),
	.awvalid (AWVALID),		.awvalid (AWVALID),
	.awready (AWREADY),		.awready (AWREADY),
	@@ -120,7 +120,7 @@ axibram_read #(
	)		)
	axibram_read(		axibram_read(
	.aclk (ACLK),		.aclk (ACLK),
	.rst (ARESETN),		.arst (ARESETN),
	.araddr (ARADDR),		.araddr (ARADDR),
	.arvalid (ARVALID),		.arvalid (ARVALID),
	.arready (ARREADY),		.arready (ARREADY),

dma/sata_top.v

+5 −3

Original line number	Original line	Diff line number	Diff line
	@@ -537,7 +537,8 @@ V .MEMBRIDGE_ADDR (),
	.FRAME_HEIGHT_BITS (),		.FRAME_HEIGHT_BITS (),
	.FRAME_WIDTH_BITS ()		.FRAME_WIDTH_BITS ()
	)*/ membridge(		)*/ membridge(
	.rst (rst), // input		.mrst (rst), // input
			.hrst (rst), // input
	.mclk (hclk), // input		.mclk (hclk), // input
	.hclk (hclk), // input		.hclk (hclk), // input
	.cmd_ad (cmd_ad),		.cmd_ad (cmd_ad),
	@@ -604,9 +605,10 @@ V .MEMBRIDGE_ADDR (),
	.afi_rresp (afi_rresp), // input[2:0]		.afi_rresp (afi_rresp), // input[2:0]
	.afi_rcount (afi_rcount), // input[7:0]		.afi_rcount (afi_rcount), // input[7:0]
	.afi_racount (afi_racount), // input[2:0]		.afi_racount (afi_racount), // input[2:0]
	.afi_rdissuecap1en (afi_rdissuecap1en), // output		.afi_rdissuecap1en (afi_rdissuecap1en)/*, // output
	.rdata_done (rdata_done)		.rdata_done (rdata_done)*/
	);		);
			assign rdata_done = 1'b0;

	sata_host sata_host(		sata_host sata_host(
	.extrst (rst),		.extrst (rst),

host/gtx_10x8dec.v

0 → 100644

+137 −0

Original line number	Original line	Diff line number	Diff line
			/*******************************************************************************
			* Module: gtx_10x8dec
			* Date: 2015-07-11
			* Author: Alexey
			* Description: 8x10 encoder implementation
			*
			* Copyright (c) 2015 Elphel, Inc.
			* gtx_10x8dec.v is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* gtx_10x8dec.v file is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/
			module gtx_10x8dec(
			input wire rst,
			input wire clk,
			input wire [19:0] indata,
			output wire [15:0] outdata,
			output wire [1:0] outisk,
			output wire [1:0] notintable,
			output wire [1:0] disperror
			/* uncomment if necessary
			input wire [0:0] inaux,
			output wire [0:0] outaux, */
			);
			/*
			uncomment if necessary
			// bypass auxilary informational signals
			reg [0:0] aux_r;
			reg [0:0] aux_rr;
			always @ (posedge clk)
			begin
			aux_r <= inaux;
			aux_rr <= aux_r;
			end
			assign outaux = aux_rr;
			*/
			// split incoming data in 2 bytes
			wire [9:0] addr0;
			wire [9:0] addr1;

			assign addr0 = indata[9:0];
			assign addr1 = indata[19:10];

			// get decoded values after 2 clock cycles, all '1's = cannot be decoded
			wire [15:0] table0_out;
			wire [15:0] table1_out;
			wire [9:0] table0;
			wire [9:0] table1;
			assign table0 = table0_out[9:0];
			assign table1 = table1_out[9:0];

			assign outdata = {table1[7:0], table0[7:0]};
			assign outisk = {table1[8], table0[8]};
			assign notintable = {\|table1, \|table0};

			// disparity control
			// last clock disparity
			reg disparity;
			// disparity after 1st byte
			wire disparity_interm;
			// delayed ones
			reg disp0_r;
			reg disp1_r;
			reg disp1_rr;
			always @ (posedge clk)
			begin
			disp0_r <= disparity;
			disp1_r <= disparity_interm;
			disp1_rr <= disp1_r;
			end
			// overall expected disparity when the table values would apper - disp0_r.
			// disp1_rr shows expected after 0st byte would be considered
			wire expected_disparity;
			wire expected_disparity_interm;

			assign expected_disparity = disp0_r;
			assign expected_disparity_interm = disp1_rr;

			// invert disparity after a byte
			// if current encoded word containg an equal amount of 1s and 0s (i.e. 5 x '1'), disp shall stay the same
			// if amounts are unequal, there are either 4 or 6 '1's. in either case disp shall be inverted
			wire inv_disp0;
			wire inv_disp1;
			assign inv_disp0 = ~^(indata[9:0]);
			assign inv_disp1 = ~^(indata[19:10]);

			assign disparity_interm = inv_disp0 ? ~disparity : disparity;
			always @ (posedge clk)
			disparity <= rst ? 1'b0 : inv_disp1 ^ inv_disp0 ? ~disparity : disparity;

			// to correct disparity if once an error occured
			reg correct_table_disp;
			always @ (posedge clk)
			correct_table_disp <= rst ? 1'b0 : disperror ? ~correct_table_disp : correct_table_disp;

			// calculate disparity on table values
			wire table_disp0;
			wire table_disp1;
			assign table_disp0 = table0[9] ^ correct_table_disp;
			assign table_disp1 = table1[9] ^ correct_table_disp;

			assign disperror = {table_disp0 == expected_disparity, table_disp1 == expected_disparity_interm};

			// TODO change mem to 18 instead of 36, so the highest address bit could be dropped
			ramt_var_w_var_r #(
			.REGISTERS_A (1),
			.REGISTERS_B (1),
			.LOG2WIDTH_A (4),
			.LOG2WIDTH_B (4)
			`include "gtx_10x8dec_init.v"
			)
			decoding_table(
			.clk_a (clk),
			.addr_a ({1'b0, addr0}),
			.en_a (1'b1),
			.regen_a (1'b1),
			.we_a (1'b0),
			.data_out_a (table0_out),
			.data_in_a (16'h0),
			.clk_b (clk),
			.addr_b ({1'b0, addr1}),
			.en_b (1'b1),
			.regen_b (1'b1),
			.we_b (1'b0),
			.data_out_b (table1_out),
			.data_in_b (16'h0)
			);

			endmodule

host/gtx_10x8dec_geninit.py

0 → 100644

+13 −0

Original line number	Original line	Diff line number	Diff line
			mem7f = []
			for i in range(0x80):
			mem7f.append(0);

			i = 0
			for line in open('gtx_10x8dec_init_stub.v').readlines():
			addr = int('0b' + line.split()[1], 2)
			a = int('0b' + line.split()[0], 2)
			mem7f[addr >> 4] = (mem7f[addr >> 4] << 16) + a
			i += 1

			for i in range(0x80):
			print ', .INIT_%02X\t(256\'h%064X)' % (i, mem7f[i])

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