Finished initial code, starting verification (ba05fb7c) · Commits · Elphel / x393_sata

ahci/ahci_sata_layers.v

+2 −2

Original line number	Diff line number	Diff line
		@@ -52,7 +52,7 @@ module ahci_sata_layers #(
		output x_rdy_collision, // X_RDY/X_RDY collision on interface
		output syncesc_recv, // Where to get it?

		input pcmd_cleared, // PxCMD.ST 1->0 transition by software
		input pcmd_st_cleared, // PxCMD.ST 1->0 transition by software
		input syncesc_send, // Send sync escape
		output syncesc_send_done, // "SYNC escape until the interface is quiescent..."
		input comreset_send, // Not possible yet?
		@@ -231,7 +231,7 @@ module ahci_sata_layers #(
		.link_reset (ll_link_reset), // input wire // oob sequence is reinitiated and link now is not established or rxelecidle
		.sync_escape_req (syncesc_send), // input wire // TL demands to brutally cancel current transaction
		.sync_escape_ack (syncesc_send_done), // output wire // acknowlegement of a successful reception?
		.incom_stop_req (pcmd_cleared), // input wire // TL demands to stop current recieving session
		.incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current recieving session
		// inputs from phy
		.phy_ready (phy_ready), // input wire // phy is ready - link is established
		// data-primitives stream from phy

ahci/sata_ahci_top.v

+169 −171

Original line number	Diff line number	Diff line
		@@ -49,7 +49,7 @@
		* Commands interface
		*/
		input wire ACLK, // AXI PS Master GP1 Clock , input
		input wire ARESETN, // AXI PS Master GP1 Reset, output
		input wire ARESETN, // AXI PS Master GP1 Reset, output // @SuppressThisWarning VEditor unused (arst instead)
		// AXI PS Master GP1: Read Address
		input wire [31:0] ARADDR, // AXI PS Master GP1 ARADDR[31:0], output
		input wire ARVALID, // AXI PS Master GP1 ARVALID, output
		@@ -141,6 +141,7 @@
		input wire [2:0] afi_racount,
		output wire afi_rdissuecap1en,

		output wire irq,
		/*
		* PHY
		*/
		@@ -153,8 +154,8 @@
		input wire EXTCLK_N
		);

		wire sata_clk;
		wire sata_rst;
		// wire sata_clk;
		// wire sata_rst;
		wire exrst;

		// Data/type FIFO, host -> device
		@@ -173,7 +174,7 @@

		// communication with transport/link/phys layers
		// wire phy_rst; // frome phy, as a response to hba_arst \|\| port_arst. It is deasserted when clock is stable
		wire [ 1:0] phy_ready; // 0 - not ready, 1..3 - negotiated speed
		wire [ 1:0] phy_speed; // 0 - not ready, 1..3 - negotiated speed
		wire xmit_ok; // FIS transmission acknowledged OK
		wire xmit_err; // Error during sending of a FIS
		wire syncesc_recv; // These two inputs interrupt transmit
		@@ -207,9 +208,6 @@
		wire [3:0] sctl_ipm; // Interface power management transitions allowed
		wire [3:0] sctl_spd; // Interface maximal speed

		wire irq; // CPU interrupt request



		ahci_top #(
		.PREFETCH_ALWAYS(0),
		@@ -307,36 +305,36 @@
		.d2h_data (d2h_data), // input[31:0]
		.d2h_type (d2h_type), // input[1:0]
		.d2h_valid (d2h_valid), // input
		.d2h_many(), // input
		.d2h_ready(), // output
		.phy_ready(), // input[1:0]
		.xmit_ok(), // input
		.xmit_err(), // input
		.syncesc_recv(), // input
		.pcmd_st_cleared(), // output
		.syncesc_send(), // output
		.syncesc_send_done(), // input
		.comreset_send(), // output
		.cominit_got(), // input
		.set_offline(), // output
		.x_rdy_collision(), // input
		.send_R_OK(), // output
		.send_R_ERR(), // output
		.serr_DT(), // input
		.serr_DS(), // input
		.serr_DH(), // input
		.serr_DC(), // input
		.serr_DB(), // input
		.serr_DW(), // input
		.serr_DI(), // input
		.serr_EP(), // input
		.serr_EC(), // input
		.serr_ET(), // input
		.serr_EM(), // input
		.serr_EI(), // input
		.sctl_ipm(), // output[3:0]
		.sctl_spd(), // output[3:0]
		.irq() // output
		.d2h_many (d2h_many), // input
		.d2h_ready (d2h_ready), // output
		.phy_ready (phy_speed), // input[1:0]
		.xmit_ok (xmit_ok), // input
		.xmit_err (xmit_err), // input
		.syncesc_recv (syncesc_recv), // input
		.pcmd_st_cleared (pcmd_st_cleared), // output
		.syncesc_send (syncesc_send), // output
		.syncesc_send_done (syncesc_send_done), // input
		.comreset_send (comreset_send), // output
		.cominit_got (cominit_got), // input
		.set_offline (set_offline), // output
		.x_rdy_collision (x_rdy_collision), // input
		.send_R_OK (send_R_OK), // output
		.send_R_ERR (send_R_ERR), // output
		.serr_DT (serr_DT), // input
		.serr_DS (serr_DS), // input
		.serr_DH (serr_DH), // input
		.serr_DC (serr_DC), // input
		.serr_DB (serr_DB), // input
		.serr_DW (serr_DW), // input
		.serr_DI (serr_DI), // input
		.serr_EP (serr_EP), // input
		.serr_EC (serr_EC), // input
		.serr_ET (serr_ET), // input
		.serr_EM (serr_EM), // input
		.serr_EI (serr_EI), // input
		.sctl_ipm (sctl_ipm), // output[3:0]
		.sctl_spd (sctl_spd), // output[3:0]
		.irq (irq) // output
		);

		ahci_sata_layers #(
		@@ -344,54 +342,54 @@
		.DATA_BYTE_WIDTH(4)
		) ahci_sata_layers_i (
		.exrst (exrst), // input
		.reliable_clk (ACLK), // input
		.reliable_clk (reliable_clk), // input
		.rst (sata_rst), // output
		.clk (sata_clk), // output
		.h2d_data(), // input[31:0]
		.h2d_mask(), // input[1:0]
		.h2d_type(), // input[1:0]
		.h2d_valid(), // input
		.h2d_ready(), // output
		.d2h_data(), // output[31:0]
		.d2h_mask(), // output[1:0]
		.d2h_type(), // output[1:0]
		.d2h_valid(), // output
		.d2h_many(), // output
		.d2h_ready(), // input
		.phy_speed(), // output[1:0]
		.h2d_data (h2d_data), // input[31:0]
		.h2d_mask (2'h3), //h2d_mask), // input[1:0]
		.h2d_type (h2d_type), // input[1:0]
		.h2d_valid (h2d_valid), // input
		.h2d_ready (h2d_ready), // output
		.d2h_data (d2h_data), // output[31:0]
		.d2h_mask (), // 2h_mask), // output[1:0]
		.d2h_type (d2h_type), // output[1:0]
		.d2h_valid (d2h_valid), // output
		.d2h_many (d2h_many), // output
		.d2h_ready (d2h_ready), // input
		.phy_speed (phy_speed), // output[1:0]
		.gtx_ready(), // output
		.xmit_ok(), // output
		.xmit_err(), // output
		.x_rdy_collision(), // output
		.syncesc_recv(), // output
		.pcmd_cleared(), // input
		.syncesc_send(), // input
		.syncesc_send_done(), // output
		.comreset_send(), // input
		.cominit_got(), // output
		.set_offline(), // input
		.send_R_OK(), // input
		.send_R_ERR(), // input
		.serr_DT(), // output
		.serr_DS(), // output
		.serr_DH(), // output
		.serr_DC(), // output
		.serr_DB(), // output
		.serr_DW(), // output
		.serr_DI(), // output
		.serr_EP(), // output
		.serr_EC(), // output
		.serr_ET(), // output
		.serr_EM(), // output
		.serr_EI(), // output
		.sctl_ipm(), // input[3:0]
		.sctl_spd(), // input[3:0]
		.extclk_p(), // input wire
		.extclk_n(), // input wire
		.txp_out(), // output wire
		.txn_out(), // output wire
		.rxp_in(), // input wire
		.rxn_in() // input wire
		.xmit_ok (xmit_ok), // output
		.xmit_err (xmit_err), // output
		.x_rdy_collision (x_rdy_collision), // output
		.syncesc_recv (syncesc_recv), // output
		.pcmd_st_cleared (pcmd_st_cleared), // input
		.syncesc_send (syncesc_send), // input
		.syncesc_send_done (syncesc_send_done), // output
		.comreset_send (comreset_send), // input
		.cominit_got (cominit_got), // output
		.set_offline (set_offline), // input
		.send_R_OK (send_R_OK), // input
		.send_R_ERR (send_R_ERR), // input
		.serr_DT (serr_DT), // output
		.serr_DS (serr_DS), // output
		.serr_DH (serr_DH), // output
		.serr_DC (serr_DC), // output
		.serr_DB (serr_DB), // output
		.serr_DW (serr_DW), // output
		.serr_DI (serr_DI), // output
		.serr_EP (serr_EP), // output
		.serr_EC (serr_EC), // output
		.serr_ET (serr_ET), // output
		.serr_EM (serr_EM), // output
		.serr_EI (serr_EI), // output
		.sctl_ipm (sctl_ipm), // input[3:0]
		.sctl_spd (sctl_spd), // input[3:0]
		.extclk_p (EXTCLK_P), // input wire
		.extclk_n (EXTCLK_N), // input wire
		.txp_out (TXP), // output wire
		.txn_out (TXN), // output wire
		.rxp_in (RXP), // input wire
		.rxn_in (RXN) // input wire
		);

dma/sata_top.v

+13 −10

Original line number	Diff line number	Diff line
		@@ -42,9 +42,10 @@
		* Takes commands from axi iface as a slave, transfers data with another axi iface as a master
		*/
		module sata_top(
		output wire sclk,
		output wire sata_clk,
		output wire sata_rst,
		input wire extrst,
		// input wire extrst,
		input wire arst,

		// reliable clock to source drp and cpll lock det circuits
		input wire reliable_clk,
		@@ -147,6 +148,8 @@
		input wire [2:0] afi_racount,
		output wire afi_rdissuecap1en,

		output wire irq, // not used here, for compatibility with AHCI branch

		/*
		* PHY
		*/
		@@ -158,7 +161,7 @@
		input wire EXTCLK_P,
		input wire EXTCLK_N
		);

		assign irq = 0;
		//wire sata_rst;
		// dma_regs <-> sata host
		// tmp to cmd control
		@@ -238,7 +241,7 @@ wire bram_regen;
		// sata logic reset
		//wire rst;
		// sata clk
		//wire sclk;
		//wire sata_clk;
		// dma_regs <-> dma_control
		wire [31:7] mem_address;
		wire [31:0] lba;
		@@ -354,7 +357,7 @@ axi_regs axi_regs(
		dma_regs dma_regs(
		.rst (ARESETN), // input wire
		.ACLK (ACLK), // input wire
		.sclk (sclk), // input wire
		.sclk (sata_clk), // input wire
		// control iface
		.mem_address (mem_address[31:7]), // output[31:7] wire
		.lba (lba), // output[31:0] wire
		@@ -442,7 +445,7 @@ dma_regs dma_regs(


		dma_control dma_control(
		.sclk (sclk), // input wire
		.sclk (sata_clk), // input wire
		.hclk (hclk), // input wire
		.rst (sata_rst), // input wire

		@@ -545,9 +548,9 @@ V .MEMBRIDGE_ADDR (),
		.FRAME_HEIGHT_BITS (),
		.FRAME_WIDTH_BITS ()
		)*/ membridge(
		.mrst (sata_rst), // hrst), // input Andrey: Wrong, should be @sclk
		.mrst (sata_rst), // hrst), // input Andrey: Wrong, should be @sata_clk
		.hrst (hrst), // input
		.mclk (sclk), // input
		.mclk (sata_clk), // input
		.hclk (hclk), // input
		.cmd_ad (cmd_ad), // input[7:0]
		.cmd_stb (cmd_stb), // input // Nothing here
		@@ -619,11 +622,11 @@ V .MEMBRIDGE_ADDR (),
		assign rdata_done = 1'b0;

		sata_host sata_host(
		.extrst (extrst),
		.extrst (arst),
		// sata rst
		.rst (sata_rst),
		// sata clk
		.clk (sclk),
		.clk (sata_clk),
		// reliable clock to source drp and cpll lock det circuits
		.reliable_clk (reliable_clk),
		// temporary

dma/top.v

+18 −11

Original line number	Diff line number	Diff line
		@@ -54,12 +54,12 @@ module top #(
		);

		wire axi_aclk0;
		wire sclk;
		wire sata_rst;
		wire sclk ; // Just output from SATA subsystem SuppressThisWarning VEditor Not used
		wire sata_rst; // Just output from SATA subsystem SuppressThisWarning VEditor Not used
		wire extrst;
		wire [3:0] fclk;
		wire [3:0] frst;
		wire axi_aclk;
		//wire axi_aclk;
		wire axi_rst;
		wire hclk;
		wire comb_rst;
		@@ -141,6 +141,8 @@ wire [ 7:0] afi3_rcount; // input[7:0]
		wire [ 2:0] afi3_racount; // input[2:0]
		wire afi3_rdissuecap1en; // output

		wire irq; // ps7 IRQ

		assign comb_rst=~frst[0] \| frst[1];
		always @(posedge comb_rst or posedge axi_aclk0) begin
		if (comb_rst) axi_rst_pre <= 1'b1;
		@@ -148,7 +150,7 @@ always @(posedge comb_rst or posedge axi_aclk0) begin
		end

		//BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(/fclk[0]/ sclk));
		assign axi_aclk = sclk;
		//assign axi_aclk = sclk;
		BUFG bufg_axi_aclk0_i (.O(axi_aclk0),.I(fclk[0]));
		BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
		BUFG bufg_extrst_i (.O(extrst),.I(axi_rst_pre));
		@@ -162,14 +164,17 @@ axi_hp_clk #(
		.clk_axihp (hclk), // output
		.locked_axihp () // output // not controlled?
		);

		`ifdef AHCI_SATA
		sata_ahci_top sata_top(
		`else
		sata_top sata_top(
		.sclk (sclk),
		`endif
		.sata_clk (sclk),
		// reliable clock to source drp and cpll lock det circuits
		.reliable_clk (axi_aclk0),
		.hclk (hclk),
		.sata_rst (sata_rst),
		.extrst (extrst),
		.arst (extrst),
		.ACLK (axi_aclk0),
		.ARESETN (axi_rst/* \| sata_rst*/),
		// AXI PS Master GP1: Read Address
		@@ -263,6 +268,8 @@ sata_top sata_top(
		.afi_racount (afi3_racount),
		.afi_rdissuecap1en (afi3_rdissuecap1en),

		.irq (irq), // output wire

		/*
		* PHY
		*/
		@@ -502,8 +509,8 @@ PS7 ps7_i (
		.DMA3DATYPE(), // DMAC 3 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
		.DMA3RSTN(), // DMAC 3 RESET output (reserved, do not use), output
		// Interrupt signals
		.IRQF2P(), // Interrupts, OL to PS [19:0], input
		.IRQP2F(), // Interrupts, OL to PS [28:0], output
		.IRQF2P({19'b0,irq}), // Interrupts, PL to PS [19:0], input
		.IRQP2F(), // Interrupts, PS to PL [28:0], output
		// Event Signals
		.EVENTEVENTI(), // EVENT Wake up one or both CPU from WFE state, input
		.EVENTEVENTO(), // EVENT Asserted when one of the COUs executed SEV instruction, output

system_defines.vh

+1 −0

Original line number	Diff line number	Diff line
		@@ -2,6 +2,7 @@
		`ifndef SYSTEM_DEFINES
		`define SYSTEM_DEFINES
		`define PRELOAD_BRAMS
		`define AHCI_SATA 1
		// Enviroment-dependent options
		`ifdef IVERILOG
		`define SIMULATION

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