Loading ahci/ahci_dma.v +1 −1 Original line number Diff line number Diff line Loading @@ -447,7 +447,7 @@ module ahci_dma ( if (prd_wr) qw_datawr_last <= qwcount[21:3] == 0; /// else if (afi_wvalid) qw_datawr_last <= qw_datawr_burst == 1; else if (afi_wvalid) qw_datawr_last <= (qw_datawr_burst == 1) || (qw_datawr_last && !(|qw_datawr_left[21:3])); // last case - n*16 + 1 (last burst single) else if (afi_wvalid) qw_datawr_last <= (qw_datawr_burst == 1) || (qw_datawr_last && (qw_datawr_left[21:3] == 16)); // last case - n*16 + 1 (last burst single) if (prd_wr) qw_datawr_burst <= (|qwcount[21:7])? 4'hf: qwcount[6:3]; /// else if (afi_wvalid && qw_datawr_last && (qw_datawr_left[21:7] == 0)) qw_datawr_burst <= qw_datawr_left[6:3]; // if not last roll over to 'hf Loading tb/tb_ahci.tf +5 −3 Original line number Diff line number Diff line Loading @@ -895,9 +895,11 @@ initial begin //Host maxigp1_print (HBA_PORT__PxSSTS__DET__ADDR << 2,"HBA_PORT__PxSSTS__DET__ADDR"); setup_pio_read_identify_command_simple(1); // prdt interrupt for entry 0 // setup_pio_read_identify_command_simple(1); // prdt interrupt for entry 0 // setup_pio_read_identify_command_shifted(1); // prdt interrupt for entry 0 // setup_pio_read_identify_command_multi4(1,27,71,83); // prdt interrupt for entry 0 /// setup_pio_read_identify_command_multi4(1,27,71,83); // prdt interrupt for entry 0 /// setup_pio_read_identify_command_multi4(1,27,64,83); // prdt interrupt for entry 0 setup_pio_read_identify_command_multi4(1,64,63,64); // prdt interrupt for entry 0 maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR"); maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__PSE__MASK); // allow PS only interrupts (PIO setup) Loading tb_ahci_01.sav +7 −7 Original line number Diff line number Diff line [*] [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] Wed Jan 27 20:13:54 2016 [*] Wed Jan 27 20:37:20 2016 [*] [dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160127131132886.fst" [dumpfile_mtime] "Wed Jan 27 20:12:01 2016" [dumpfile_size] 3824547 [dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160127133150634.fst" [dumpfile_mtime] "Wed Jan 27 20:32:21 2016" [dumpfile_size] 3824683 [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav" [timestart] 24704000 [size] 1823 1180 [timestart] 22094000 [size] 1823 1173 [pos] 1994 0 *-16.995279 25103334 23903334 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-19.117058 23716667 23903334 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] tb_ahci. [treeopen] tb_ahci.dev.phy. [treeopen] tb_ahci.dut. Loading Loading
ahci/ahci_dma.v +1 −1 Original line number Diff line number Diff line Loading @@ -447,7 +447,7 @@ module ahci_dma ( if (prd_wr) qw_datawr_last <= qwcount[21:3] == 0; /// else if (afi_wvalid) qw_datawr_last <= qw_datawr_burst == 1; else if (afi_wvalid) qw_datawr_last <= (qw_datawr_burst == 1) || (qw_datawr_last && !(|qw_datawr_left[21:3])); // last case - n*16 + 1 (last burst single) else if (afi_wvalid) qw_datawr_last <= (qw_datawr_burst == 1) || (qw_datawr_last && (qw_datawr_left[21:3] == 16)); // last case - n*16 + 1 (last burst single) if (prd_wr) qw_datawr_burst <= (|qwcount[21:7])? 4'hf: qwcount[6:3]; /// else if (afi_wvalid && qw_datawr_last && (qw_datawr_left[21:7] == 0)) qw_datawr_burst <= qw_datawr_left[6:3]; // if not last roll over to 'hf Loading
tb/tb_ahci.tf +5 −3 Original line number Diff line number Diff line Loading @@ -895,9 +895,11 @@ initial begin //Host maxigp1_print (HBA_PORT__PxSSTS__DET__ADDR << 2,"HBA_PORT__PxSSTS__DET__ADDR"); setup_pio_read_identify_command_simple(1); // prdt interrupt for entry 0 // setup_pio_read_identify_command_simple(1); // prdt interrupt for entry 0 // setup_pio_read_identify_command_shifted(1); // prdt interrupt for entry 0 // setup_pio_read_identify_command_multi4(1,27,71,83); // prdt interrupt for entry 0 /// setup_pio_read_identify_command_multi4(1,27,71,83); // prdt interrupt for entry 0 /// setup_pio_read_identify_command_multi4(1,27,64,83); // prdt interrupt for entry 0 setup_pio_read_identify_command_multi4(1,64,63,64); // prdt interrupt for entry 0 maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR"); maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__PSE__MASK); // allow PS only interrupts (PIO setup) Loading
tb_ahci_01.sav +7 −7 Original line number Diff line number Diff line [*] [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] Wed Jan 27 20:13:54 2016 [*] Wed Jan 27 20:37:20 2016 [*] [dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160127131132886.fst" [dumpfile_mtime] "Wed Jan 27 20:12:01 2016" [dumpfile_size] 3824547 [dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160127133150634.fst" [dumpfile_mtime] "Wed Jan 27 20:32:21 2016" [dumpfile_size] 3824683 [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav" [timestart] 24704000 [size] 1823 1180 [timestart] 22094000 [size] 1823 1173 [pos] 1994 0 *-16.995279 25103334 23903334 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-19.117058 23716667 23903334 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] tb_ahci. [treeopen] tb_ahci.dev.phy. [treeopen] tb_ahci.dut. Loading