Added gtx wrapper to implement PCS features beyond gtx inself (9f7bbe7d) · Commits · Elphel / x393_sata

device/sata_phy_dev.v

+24 −6

Original line number	Diff line number	Diff line
		@@ -60,7 +60,15 @@ wire [31:0] txdata_oob;
		wire [3:0] txcharisk;
		wire [3:0] txcharisk_oob;
		wire [63:0] rxdata;
		wire [3:0] rxcharisk;
		wire [63:0] rxdata_gtx;
		wire [7:0] rxcharisk;
		wire [7:0] rxcharisk_gtx;
		wire [7:0] rxchariscomma;
		wire [7:0] rxchariscomma_gtx;
		wire [7:0] rxdisperr;
		wire [7:0] rxdisperr_gtx;
		wire [7:0] rxnotintable;
		wire [7:0] rxnotintable_gtx;
		wire [31:0] rxdata_out;
		wire [31:0] txdata_in;
		wire [3:0] txcharisk_in;
		@@ -546,15 +554,15 @@ gtx(
		.RX8B10BEN (1'b1),
		.RXUSRCLK (rxusrclk),
		.RXUSRCLK2 (rxusrclk2),
		.RXDATA (rxdata),
		.RXDATA (rxdata_gtx),
		.RXPRBSERR (),
		.RXPRBSSEL (3'd0),
		.RXPRBSCNTRESET (1'b0),
		.RXDFEXYDEN (1'b1),
		.RXDFEXYDHOLD (1'b0),
		.RXDFEXYDOVRDEN (1'b0),
		.RXDISPERR (),
		.RXNOTINTABLE (),
		.RXDISPERR (rxdisperr_gtx),
		.RXNOTINTABLE (rxnotintable_gtx),
		.GTXRXP (rxp),
		.GTXRXN (rxn),
		.RXBUFRESET (1'b0),
		@@ -637,8 +645,8 @@ gtx(
		.RXELECIDLEMODE (2'b00),
		.RXPOLARITY (1'b0),
		.RXSLIDE (1'b0),
		.RXCHARISCOMMA (),
		.RXCHARISK (rxcharisk),
		.RXCHARISCOMMA (rxchariscomma_gtx),
		.RXCHARISK (rxcharisk_gtx),
		.RXCHBONDI (5'b00000),
		.RXRESETDONE (rxresetdone),
		.RXQPIEN (1'b0),
		@@ -722,6 +730,16 @@ gtx(
		.TXSYNCIN (1'b0)*/
		);

		// align to 4-byte boundary
		reg twobytes_shift;
		always @ (posedge clk)
		twobytes_shift <= rst ? 1'b0 : rxchariscomma_gtx[0] === 1'bx ? 1'b0 : rxchariscomma_gtx[2] === 1'bx ? 1'b0 : rxchariscomma_gtx[2] ? 1'b1 : rxchariscomma_gtx[0] ? 1'b0 : twobytes_shift;
		assign rxdata = twobytes_shift ? {rxdata_gtx[63:32] , rxdata_gtx[15:0] , rxdata_gtx[31:16] } : rxdata_gtx;
		assign rxcharisk = twobytes_shift ? {rxcharisk_gtx[7:4] , rxcharisk_gtx[1:0] , rxcharisk_gtx[3:2] } : rxcharisk_gtx;
		assign rxchariscomma = twobytes_shift ? {rxchariscomma_gtx[7:4], rxchariscomma_gtx[1:0], rxchariscomma_gtx[3:2]} : rxchariscomma_gtx;
		assign rxdisperr = twobytes_shift ? {rxdisperr_gtx[7:4] , rxdisperr_gtx[1:0] , rxdisperr_gtx[3:2] } : rxdisperr_gtx;
		assign rxnotintable = twobytes_shift ? {rxnotintable_gtx[7:4] , rxnotintable_gtx[1:0] , rxnotintable_gtx[3:2] } : rxnotintable_gtx;

		/*
		* Interfaces
		*/

dma/sata_top.v

+11 −9

Original line number	Diff line number	Diff line
		@@ -30,6 +30,8 @@
		*/
		module sata_top(
		output wire sclk,
		output wire sata_rst,
		input wire extrst,
		/*
		* Commands interface
		*/
		@@ -146,7 +148,7 @@
		input wire EXTCLK_N
		);

		wire sata_rst;
		//wire sata_rst;
		// dma_regs <-> sata host
		// tmp to cmd control
		wire cmd_val_out;
		@@ -223,7 +225,7 @@ wire bram_wen;
		wire bram_ren;
		wire bram_regen;
		// sata logic reset
		wire rst;
		//wire rst;
		// sata clk
		//wire sclk;
		// dma_regs <-> dma_control
		@@ -284,7 +286,7 @@ wire [63:0] buf_rdata;
		// additional adapter <-> membridge wire
		wire rdata_done; // = membridge.is_last_in_page & membridge.afi_rready;

		assign rst = ARESETN;
		//assign rst = ARESETN;


		axi_regs axi_regs(
		@@ -344,7 +346,7 @@ axi_regs axi_regs(
		* Programmable sata controller registers
		*/
		dma_regs dma_regs(
		.rst (rst),
		.rst (sata_rst),
		.ACLK (ACLK),
		.sclk (sclk),
		// control iface
		@@ -436,7 +438,7 @@ dma_regs dma_regs(
		dma_control dma_control(
		.sclk (sclk),
		.hclk (hclk),
		.rst (rst),
		.rst (sata_rst),

		// registers iface
		.mem_address (mem_address),
		@@ -484,7 +486,7 @@ dma_control dma_control(

		dma_adapter dma_adapter(
		.clk (hclk),
		.rst (rst),
		.rst (sata_rst),
		// command iface
		.cmd_type (adp_type),
		.cmd_val (adp_val),
		@@ -537,8 +539,8 @@ V .MEMBRIDGE_ADDR (),
		.FRAME_HEIGHT_BITS (),
		.FRAME_WIDTH_BITS ()
		)*/ membridge(
		.mrst (rst), // input
		.hrst (rst), // input
		.mrst (sata_rst), // input
		.hrst (ARESETN), // input
		.mclk (hclk), // input
		.hclk (hclk), // input
		.cmd_ad (cmd_ad),
		@@ -611,7 +613,7 @@ V .MEMBRIDGE_ADDR (),
		assign rdata_done = 1'b0;

		sata_host sata_host(
		.extrst (rst),
		.extrst (extrst),
		// sata rst
		.rst (sata_rst),
		// sata clk

dma/top.v

+6 −1

Original line number	Diff line number	Diff line
		@@ -43,6 +43,8 @@ wire [32*REGISTERS_CNT - 1:0] outmem;
		wire clrstart;

		wire sclk;
		wire sata_rst;
		wire extrst;
		wire [3:0] fclk;
		wire [3:0] frst;
		wire axi_aclk;
		@@ -166,6 +168,7 @@ end
		BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(/fclk[0]/ sclk));
		BUFG bufg_axi_aclk0_i (.O(axi_aclk0),.I(fclk[0]));
		BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
		BUFG bufg_extrst_i (.O(extrst),.I(axi_rst_pre));
		axi_hp_clk #(
		.CLKIN_PERIOD(6.666),
		.CLKFBOUT_MULT_AXIHP(6),
		@@ -179,8 +182,10 @@ axi_hp_clk #(

		sata_top sata_top(
		.sclk (sclk),
		.sata_rst (sata_rst),
		.extrst (extrst),
		.ACLK (axi_aclk),
		.ARESETN (axi_rst),
		.ARESETN (axi_rst \| sata_rst),
		// AXI PS Master GP1: Read Address
		.ARADDR (ARADDR),
		.ARVALID (ARVALID),

host/gtx_10x8dec.v

+22 −13

Original line number	Diff line number	Diff line
		@@ -52,14 +52,14 @@ assign addr1 = indata[19:10];
		// get decoded values after 2 clock cycles, all '1's = cannot be decoded
		wire [15:0] table0_out;
		wire [15:0] table1_out;
		wire [9:0] table0;
		wire [9:0] table1;
		assign table0 = table0_out[9:0];
		assign table1 = table1_out[9:0];
		wire [10:0] table0;
		wire [10:0] table1;
		assign table0 = table0_out[10:0];
		assign table1 = table1_out[10:0];

		assign outdata = {table1[7:0], table0[7:0]};
		assign outisk = {table1[8], table0[8]};
		assign notintable = {\|table1, \|table0};
		assign notintable = {&table1, &table0};

		// disparity control
		// last clock disparity
		@@ -68,11 +68,13 @@ reg disparity;
		wire disparity_interm;
		// delayed ones
		reg disp0_r;
		reg disp0_rr;
		reg disp1_r;
		reg disp1_rr;
		always @ (posedge clk)
		begin
		disp0_r <= disparity;
		disp0_rr <= disp0_r;
		disp1_r <= disparity_interm;
		disp1_rr <= disp1_r;
		end
		@@ -81,8 +83,8 @@ end
		wire expected_disparity;
		wire expected_disparity_interm;

		assign expected_disparity = disp0_r;
		assign expected_disparity_interm = disp1_rr;
		assign expected_disparity = disp0_rr ^ correct_table_disp;
		assign expected_disparity_interm = disp1_rr ^ correct_table_disp;

		// invert disparity after a byte
		// if current encoded word containg an equal amount of 1s and 0s (i.e. 5 x '1'), disp shall stay the same
		@@ -99,15 +101,22 @@ always @ (posedge clk)
		// to correct disparity if once an error occured
		reg correct_table_disp;
		always @ (posedge clk)
		correct_table_disp <= rst ? 1'b0 : disperror ? ~correct_table_disp : correct_table_disp;
		correct_table_disp <= rst ? 1'b0 : disperror[1] ? ~correct_table_disp : correct_table_disp;

		// calculate disparity on table values
		wire table_disp0;
		wire table_disp1;
		assign table_disp0 = table0[9] ^ correct_table_disp;
		assign table_disp1 = table1[9] ^ correct_table_disp;
		wire table_pos_disp0;
		wire table_neg_disp0;
		wire table_pos_disp1;
		wire table_neg_disp1;
		// table_pos_disp - for current 10-bit word disparity can be positive
		// _neg_ - can be negative
		// neg & pos - can be either of them
		assign table_pos_disp0 = table0[10];
		assign table_neg_disp0 = table0[9];
		assign table_pos_disp1 = table1[10];
		assign table_neg_disp1 = table1[9];

		assign disperror = {table_disp0 == expected_disparity, table_disp1 == expected_disparity_interm};
		assign disperror = ~{table_pos_disp0 & expected_disparity \| table_neg_disp0 & ~expected_disparity, table_pos_disp1 & expected_disparity_interm \| table_neg_disp1 & ~expected_disparity_interm};

		// TODO change mem to 18 instead of 36, so the highest address bit could be dropped
		ramt_var_w_var_r #(

host/gtx_10x8dec_geninit.py

+36 −5

Original line number	Diff line number	Diff line
		# left_column[9] = disparity
		# left_column[8] = conrtol
		# left_column[7:0] = decoded 8
		# right column[9:0] = encoded 10 in correct order : abcdefgh. Need to flip it, because gtx spits out flipped data with flipped bit order
		#

		mem7f = []
		for i in range(0x80):
		mem7f.append(0);

		i = 0
		filecontent = {}
		for line in open('gtx_10x8dec_init_stub.v').readlines():
		addr = int('0b' + line.split()[1], 2)
		a = int('0b' + line.split()[0], 2)
		mem7f[addr >> 4] = (mem7f[addr >> 4] << 16) + a
		i += 1
		address_flipped_str = line.split()[1];
		address_str = address_flipped_str[::-1]
		address = int('0b' + address_str, 2)
		# retrieve everything but disparity - highest bit
		value = int('0b' + line.split()[0][1:], 2)
		# retrieve disparity
		disparity = int('0b' + line.split()[0][0], 2)
		# if disparity = 1 -> flag positive disparity, 0 -> flag negative one
		disp_pos = 1 if disparity == 1 else 0
		disp_neg = 1 if disparity == 0 else 0

		if address_str in filecontent:
		disp_pos = 1 if filecontent[address_str][1] == 1 or disp_pos else 0
		disp_neg = 1 if filecontent[address_str][2] == 1 or disp_neg else 0

		filecontent[address_str] = [address, disp_pos, disp_neg, value];


		for key in filecontent:
		(address, disp_pos, disp_neg, value) = filecontent[key]
		# if address == 0x2aa:
		# print '2AA: ADDR>>4 = %X' % (address >> 4),' ADDR = ', bin(address), ' POS DISP = ', bin(disp_pos), ' NEG DISP = ', bin(disp_neg), ' VALUE = ', bin(value)
		# print 'ADDR = ', bin(address), ' POS DISP = ', bin(disp_pos), ' NEG DISP = ', bin(disp_neg), ' VALUE = ', bin(value)
		to_mem = (disp_pos << 10) + (disp_neg << 9) + value
		mem7f[address >> 4] = mem7f[address >> 4] + (to_mem << ((address % 16) * 16))
		# if (address >> 4) == 0x2a:
		# print '2AA: ADDR = %X, to mem = %X, total = %X ' % ((address ),to_mem, mem7f[address >> 4])#, ' ADDR = ', bin(address), ' POS DISP = ', bin(disp_pos), ' NEG DISP = ', bin(disp_neg), ' VALUE = ', bin(value)
		# if addr == 0x2aa:
		# print "FLIPPED ADDR %s " % address_flipped_str, "ADDR %x " % addr, "ADDR7f %x " % (addr >> 4), "VALUE %x " % a

		for i in range(0x80):
		print ', .INIT_%02X\t(256\'h%064X)' % (i, mem7f[i])

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