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Elphel
x393_sata
Commits
9f7bbe7d
Commit
9f7bbe7d
authored
Sep 04, 2015
by
Alexey Grebenkin
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Added gtx wrapper to implement PCS features beyond gtx inself
parent
bcfe20f6
Changes
15
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Showing
15 changed files
with
551 additions
and
443 deletions
+551
-443
sata_phy_dev.v
device/sata_phy_dev.v
+24
-6
sata_top.v
dma/sata_top.v
+11
-9
top.v
dma/top.v
+6
-1
gtx_10x8dec.v
host/gtx_10x8dec.v
+22
-13
gtx_10x8dec_geninit.py
host/gtx_10x8dec_geninit.py
+36
-5
gtx_10x8dec_init.v
host/gtx_10x8dec_init.v
+54
-54
gtx_8x10enc.v
host/gtx_8x10enc.v
+2
-2
gtx_8x10enc_geninit.py
host/gtx_8x10enc_geninit.py
+5
-3
gtx_8x10enc_init.v
host/gtx_8x10enc_init.v
+41
-41
gtx_8x10enc_init_stub.v
host/gtx_8x10enc_init_stub.v
+268
-268
gtx_comma_align.v
host/gtx_comma_align.v
+9
-3
gtx_elastic.v
host/gtx_elastic.v
+21
-11
gtx_wrap.v
host/gtx_wrap.v
+31
-25
oob.v
host/oob.v
+19
-1
build
simul/build
+2
-1
No files found.
device/sata_phy_dev.v
View file @
9f7bbe7d
...
...
@@ -60,7 +60,15 @@ wire [31:0] txdata_oob;
wire
[
3
:
0
]
txcharisk
;
wire
[
3
:
0
]
txcharisk_oob
;
wire
[
63
:
0
]
rxdata
;
wire
[
3
:
0
]
rxcharisk
;
wire
[
63
:
0
]
rxdata_gtx
;
wire
[
7
:
0
]
rxcharisk
;
wire
[
7
:
0
]
rxcharisk_gtx
;
wire
[
7
:
0
]
rxchariscomma
;
wire
[
7
:
0
]
rxchariscomma_gtx
;
wire
[
7
:
0
]
rxdisperr
;
wire
[
7
:
0
]
rxdisperr_gtx
;
wire
[
7
:
0
]
rxnotintable
;
wire
[
7
:
0
]
rxnotintable_gtx
;
wire
[
31
:
0
]
rxdata_out
;
wire
[
31
:
0
]
txdata_in
;
wire
[
3
:
0
]
txcharisk_in
;
...
...
@@ -546,15 +554,15 @@ gtx(
.
RX8B10BEN
(
1'b1
)
,
.
RXUSRCLK
(
rxusrclk
)
,
.
RXUSRCLK2
(
rxusrclk2
)
,
.
RXDATA
(
rxdata
)
,
.
RXDATA
(
rxdata
_gtx
)
,
.
RXPRBSERR
()
,
.
RXPRBSSEL
(
3'd0
)
,
.
RXPRBSCNTRESET
(
1'b0
)
,
.
RXDFEXYDEN
(
1'b1
)
,
.
RXDFEXYDHOLD
(
1'b0
)
,
.
RXDFEXYDOVRDEN
(
1'b0
)
,
.
RXDISPERR
()
,
.
RXNOTINTABLE
()
,
.
RXDISPERR
(
rxdisperr_gtx
)
,
.
RXNOTINTABLE
(
rxnotintable_gtx
)
,
.
GTXRXP
(
rxp
)
,
.
GTXRXN
(
rxn
)
,
.
RXBUFRESET
(
1'b0
)
,
...
...
@@ -637,8 +645,8 @@ gtx(
.
RXELECIDLEMODE
(
2'b00
)
,
.
RXPOLARITY
(
1'b0
)
,
.
RXSLIDE
(
1'b0
)
,
.
RXCHARISCOMMA
()
,
.
RXCHARISK
(
rxcharisk
)
,
.
RXCHARISCOMMA
(
rxchariscomma_gtx
)
,
.
RXCHARISK
(
rxcharisk
_gtx
)
,
.
RXCHBONDI
(
5'b00000
)
,
.
RXRESETDONE
(
rxresetdone
)
,
.
RXQPIEN
(
1'b0
)
,
...
...
@@ -722,6 +730,16 @@ gtx(
.TXSYNCIN (1'b0)*/
)
;
// align to 4-byte boundary
reg
twobytes_shift
;
always
@
(
posedge
clk
)
twobytes_shift
<=
rst
?
1'b0
:
rxchariscomma_gtx
[
0
]
===
1'bx
?
1'b0
:
rxchariscomma_gtx
[
2
]
===
1'bx
?
1'b0
:
rxchariscomma_gtx
[
2
]
?
1'b1
:
rxchariscomma_gtx
[
0
]
?
1'b0
:
twobytes_shift
;
assign
rxdata
=
twobytes_shift
?
{
rxdata_gtx
[
63
:
32
]
,
rxdata_gtx
[
15
:
0
]
,
rxdata_gtx
[
31
:
16
]
}
:
rxdata_gtx
;
assign
rxcharisk
=
twobytes_shift
?
{
rxcharisk_gtx
[
7
:
4
]
,
rxcharisk_gtx
[
1
:
0
]
,
rxcharisk_gtx
[
3
:
2
]
}
:
rxcharisk_gtx
;
assign
rxchariscomma
=
twobytes_shift
?
{
rxchariscomma_gtx
[
7
:
4
]
,
rxchariscomma_gtx
[
1
:
0
]
,
rxchariscomma_gtx
[
3
:
2
]
}
:
rxchariscomma_gtx
;
assign
rxdisperr
=
twobytes_shift
?
{
rxdisperr_gtx
[
7
:
4
]
,
rxdisperr_gtx
[
1
:
0
]
,
rxdisperr_gtx
[
3
:
2
]
}
:
rxdisperr_gtx
;
assign
rxnotintable
=
twobytes_shift
?
{
rxnotintable_gtx
[
7
:
4
]
,
rxnotintable_gtx
[
1
:
0
]
,
rxnotintable_gtx
[
3
:
2
]
}
:
rxnotintable_gtx
;
/*
* Interfaces
*/
...
...
dma/sata_top.v
View file @
9f7bbe7d
...
...
@@ -30,6 +30,8 @@
*/
module
sata_top
(
output
wire
sclk
,
output
wire
sata_rst
,
input
wire
extrst
,
/*
* Commands interface
*/
...
...
@@ -146,7 +148,7 @@
input
wire
EXTCLK_N
)
;
wire
sata_rst
;
//
wire sata_rst;
// dma_regs <-> sata host
// tmp to cmd control
wire
cmd_val_out
;
...
...
@@ -223,7 +225,7 @@ wire bram_wen;
wire
bram_ren
;
wire
bram_regen
;
// sata logic reset
wire
rst
;
//
wire rst;
// sata clk
//wire sclk;
// dma_regs <-> dma_control
...
...
@@ -284,7 +286,7 @@ wire [63:0] buf_rdata;
// additional adapter <-> membridge wire
wire
rdata_done
;
// = membridge.is_last_in_page & membridge.afi_rready;
assign
rst
=
ARESETN
;
//
assign rst = ARESETN;
axi_regs
axi_regs
(
...
...
@@ -344,7 +346,7 @@ axi_regs axi_regs(
* Programmable sata controller registers
*/
dma_regs
dma_regs
(
.
rst
(
rst
)
,
.
rst
(
sata_
rst
)
,
.
ACLK
(
ACLK
)
,
.
sclk
(
sclk
)
,
// control iface
...
...
@@ -436,7 +438,7 @@ dma_regs dma_regs(
dma_control
dma_control
(
.
sclk
(
sclk
)
,
.
hclk
(
hclk
)
,
.
rst
(
rst
)
,
.
rst
(
sata_
rst
)
,
// registers iface
.
mem_address
(
mem_address
)
,
...
...
@@ -484,7 +486,7 @@ dma_control dma_control(
dma_adapter
dma_adapter
(
.
clk
(
hclk
)
,
.
rst
(
rst
)
,
.
rst
(
sata_
rst
)
,
// command iface
.
cmd_type
(
adp_type
)
,
.
cmd_val
(
adp_val
)
,
...
...
@@ -537,8 +539,8 @@ V .MEMBRIDGE_ADDR (),
.FRAME_HEIGHT_BITS (),
.FRAME_WIDTH_BITS ()
)*/
membridge
(
.
mrst
(
rst
)
,
// input
.
hrst
(
rst
)
,
// input
.
mrst
(
sata_
rst
)
,
// input
.
hrst
(
ARESETN
)
,
// input
.
mclk
(
hclk
)
,
// input
.
hclk
(
hclk
)
,
// input
.
cmd_ad
(
cmd_ad
)
,
...
...
@@ -611,7 +613,7 @@ V .MEMBRIDGE_ADDR (),
assign
rdata_done
=
1'b0
;
sata_host
sata_host
(
.
extrst
(
rst
)
,
.
extrst
(
ext
rst
)
,
// sata rst
.
rst
(
sata_rst
)
,
// sata clk
...
...
dma/top.v
View file @
9f7bbe7d
...
...
@@ -43,6 +43,8 @@ wire [32*REGISTERS_CNT - 1:0] outmem;
wire
clrstart
;
wire
sclk
;
wire
sata_rst
;
wire
extrst
;
wire
[
3
:
0
]
fclk
;
wire
[
3
:
0
]
frst
;
wire
axi_aclk
;
...
...
@@ -166,6 +168,7 @@ end
BUFG
bufg_axi_aclk_i
(
.
O
(
axi_aclk
)
,.
I
(
/*fclk[0]*/
sclk
))
;
BUFG
bufg_axi_aclk0_i
(
.
O
(
axi_aclk0
)
,.
I
(
fclk
[
0
]))
;
BUFG
bufg_axi_rst_i
(
.
O
(
axi_rst
)
,.
I
(
axi_rst_pre
))
;
BUFG
bufg_extrst_i
(
.
O
(
extrst
)
,.
I
(
axi_rst_pre
))
;
axi_hp_clk
#(
.
CLKIN_PERIOD
(
6.666
)
,
.
CLKFBOUT_MULT_AXIHP
(
6
)
,
...
...
@@ -179,8 +182,10 @@ axi_hp_clk #(
sata_top
sata_top
(
.
sclk
(
sclk
)
,
.
sata_rst
(
sata_rst
)
,
.
extrst
(
extrst
)
,
.
ACLK
(
axi_aclk
)
,
.
ARESETN
(
axi_rst
)
,
.
ARESETN
(
axi_rst
|
sata_rst
)
,
// AXI PS Master GP1: Read Address
.
ARADDR
(
ARADDR
)
,
.
ARVALID
(
ARVALID
)
,
...
...
host/gtx_10x8dec.v
View file @
9f7bbe7d
...
...
@@ -52,14 +52,14 @@ assign addr1 = indata[19:10];
// get decoded values after 2 clock cycles, all '1's = cannot be decoded
wire
[
15
:
0
]
table0_out
;
wire
[
15
:
0
]
table1_out
;
wire
[
9
:
0
]
table0
;
wire
[
9
:
0
]
table1
;
assign
table0
=
table0_out
[
9
:
0
]
;
assign
table1
=
table1_out
[
9
:
0
]
;
wire
[
10
:
0
]
table0
;
wire
[
10
:
0
]
table1
;
assign
table0
=
table0_out
[
10
:
0
]
;
assign
table1
=
table1_out
[
10
:
0
]
;
assign
outdata
=
{
table1
[
7
:
0
]
,
table0
[
7
:
0
]
};
assign
outisk
=
{
table1
[
8
]
,
table0
[
8
]
};
assign
notintable
=
{
|
table1
,
|
table0
};
assign
notintable
=
{
&
table1
,
&
table0
};
// disparity control
// last clock disparity
...
...
@@ -68,11 +68,13 @@ reg disparity;
wire
disparity_interm
;
// delayed ones
reg
disp0_r
;
reg
disp0_rr
;
reg
disp1_r
;
reg
disp1_rr
;
always
@
(
posedge
clk
)
begin
disp0_r
<=
disparity
;
disp0_rr
<=
disp0_r
;
disp1_r
<=
disparity_interm
;
disp1_rr
<=
disp1_r
;
end
...
...
@@ -81,8 +83,8 @@ end
wire
expected_disparity
;
wire
expected_disparity_interm
;
assign
expected_disparity
=
disp0_r
;
assign
expected_disparity_interm
=
disp1_rr
;
assign
expected_disparity
=
disp0_r
r
^
correct_table_disp
;
assign
expected_disparity_interm
=
disp1_rr
^
correct_table_disp
;
// invert disparity after a byte
// if current encoded word containg an equal amount of 1s and 0s (i.e. 5 x '1'), disp shall stay the same
...
...
@@ -99,15 +101,22 @@ always @ (posedge clk)
// to correct disparity if once an error occured
reg
correct_table_disp
;
always
@
(
posedge
clk
)
correct_table_disp
<=
rst
?
1'b0
:
disperror
?
~
correct_table_disp
:
correct_table_disp
;
correct_table_disp
<=
rst
?
1'b0
:
disperror
[
1
]
?
~
correct_table_disp
:
correct_table_disp
;
// calculate disparity on table values
wire
table_disp0
;
wire
table_disp1
;
assign
table_disp0
=
table0
[
9
]
^
correct_table_disp
;
assign
table_disp1
=
table1
[
9
]
^
correct_table_disp
;
wire
table_pos_disp0
;
wire
table_neg_disp0
;
wire
table_pos_disp1
;
wire
table_neg_disp1
;
// table_pos_disp - for current 10-bit word disparity can be positive
// _neg_ - can be negative
// neg & pos - can be either of them
assign
table_pos_disp0
=
table0
[
10
]
;
assign
table_neg_disp0
=
table0
[
9
]
;
assign
table_pos_disp1
=
table1
[
10
]
;
assign
table_neg_disp1
=
table1
[
9
]
;
assign
disperror
=
{
table_disp0
==
expected_disparity
,
table_disp1
==
expected_disparity_interm
};
assign
disperror
=
~{
table_pos_disp0
&
expected_disparity
|
table_neg_disp0
&
~
expected_disparity
,
table_pos_disp1
&
expected_disparity_interm
|
table_neg_disp1
&
~
expected_disparity_interm
};
// TODO change mem to 18 instead of 36, so the highest address bit could be dropped
ramt_var_w_var_r
#(
...
...
host/gtx_10x8dec_geninit.py
View file @
9f7bbe7d
# left_column[9] = disparity
# left_column[8] = conrtol
# left_column[7:0] = decoded 8
# right column[9:0] = encoded 10 in correct order : abcdefgh. Need to flip it, because gtx spits out flipped data with flipped bit order
#
mem7f
=
[]
for
i
in
range
(
0x80
):
mem7f
.
append
(
0
);
i
=
0
filecontent
=
{}
for
line
in
open
(
'gtx_10x8dec_init_stub.v'
)
.
readlines
():
addr
=
int
(
'0b'
+
line
.
split
()[
1
],
2
)
a
=
int
(
'0b'
+
line
.
split
()[
0
],
2
)
mem7f
[
addr
>>
4
]
=
(
mem7f
[
addr
>>
4
]
<<
16
)
+
a
i
+=
1
address_flipped_str
=
line
.
split
()[
1
];
address_str
=
address_flipped_str
[::
-
1
]
address
=
int
(
'0b'
+
address_str
,
2
)
# retrieve everything but disparity - highest bit
value
=
int
(
'0b'
+
line
.
split
()[
0
][
1
:],
2
)
# retrieve disparity
disparity
=
int
(
'0b'
+
line
.
split
()[
0
][
0
],
2
)
# if disparity = 1 -> flag positive disparity, 0 -> flag negative one
disp_pos
=
1
if
disparity
==
1
else
0
disp_neg
=
1
if
disparity
==
0
else
0
if
address_str
in
filecontent
:
disp_pos
=
1
if
filecontent
[
address_str
][
1
]
==
1
or
disp_pos
else
0
disp_neg
=
1
if
filecontent
[
address_str
][
2
]
==
1
or
disp_neg
else
0
filecontent
[
address_str
]
=
[
address
,
disp_pos
,
disp_neg
,
value
];
for
key
in
filecontent
:
(
address
,
disp_pos
,
disp_neg
,
value
)
=
filecontent
[
key
]
# if address == 0x2aa:
# print '2AA: ADDR>>4 = %X' % (address >> 4),' ADDR = ', bin(address), ' POS DISP = ', bin(disp_pos), ' NEG DISP = ', bin(disp_neg), ' VALUE = ', bin(value)
# print 'ADDR = ', bin(address), ' POS DISP = ', bin(disp_pos), ' NEG DISP = ', bin(disp_neg), ' VALUE = ', bin(value)
to_mem
=
(
disp_pos
<<
10
)
+
(
disp_neg
<<
9
)
+
value
mem7f
[
address
>>
4
]
=
mem7f
[
address
>>
4
]
+
(
to_mem
<<
((
address
%
16
)
*
16
))
# if (address >> 4) == 0x2a:
# print '2AA: ADDR = %X, to mem = %X, total = %X ' % ((address ),to_mem, mem7f[address >> 4])#, ' ADDR = ', bin(address), ' POS DISP = ', bin(disp_pos), ' NEG DISP = ', bin(disp_neg), ' VALUE = ', bin(value)
# if addr == 0x2aa:
# print "FLIPPED ADDR %s " % address_flipped_str, "ADDR %x " % addr, "ADDR7f %x " % (addr >> 4), "VALUE %x " % a
for
i
in
range
(
0x80
):
print
', .INIT_
%02
X
\t
(256
\'
h
%064
X)'
%
(
i
,
mem7f
[
i
])
host/gtx_10x8dec_init.v
View file @
9f7bbe7d
...
...
@@ -2,62 +2,62 @@
,
.
INIT_01
(
256'h0000000000000000000000000000000000000000000000000000000000000000
)
,
.
INIT_02
(
256'h0000000000000000000000000000000000000000000000000000000000000000
)
,
.
INIT_03
(
256'h0000000000000000000000000000000000000000000000000000000000000000
)
,
.
INIT_04
(
256'h00000
000000000000000
00000000000000000000000000000000000000000000
)
,
.
INIT_05
(
256'h00000
000000000000000000000000217023702570277029702B702D702F703F7
)
,
.
INIT_06
(
256'h000000000000000000000000000000000
208022802480268028802A802C802E8
)
,
.
INIT_07
(
256'h0000000000000
00000000000000000000207022702470267028702A702C702E7
)
,
.
INIT_08
(
256'h00000
000000000000000
00000000000000000000000000000000000000000000
)
,
.
INIT_09
(
256'h00000
00000000000000000000000021B023B025B027B029B02BB02DB02FB03FB
)
,
.
INIT_0A
(
256'h00000
0000000000000000000000000000204022402440264028402A402C402E4
)
,
.
INIT_0B
(
256'h00
1402140034023400540254007402740094029400B402B400D402D400F402F4
)
,
.
INIT_0C
(
256'h00000
0000000000000000000000000000218023802580278029802B802D802F8
)
,
.
INIT_0D
(
256'h000
C020C002C022C004C024C006C026C008C028C00AC02AC00CC02CC00EC02EC
)
,
.
INIT_0E
(
256'h00
1C021C003C023C005C025C007C027C009C029C00BC02BC00DC02DC00FC02FC
)
,
.
INIT_0F
(
256'h000000000000000000000000000000000
11C013C015C017C019C01BC01DC01FC
)
,
.
INIT_10
(
256'h00000
000000000000000
00000000000000000000000000000000000000000000
)
,
.
INIT_11
(
256'h00000
00000000000000000000000021D023D025D027D029D02BD02DD02FD03FD
)
,
.
INIT_12
(
256'h00000
0000000000000000000000000000202022202420262028202A202C202E2
)
,
.
INIT_13
(
256'h00
1202120032023200520252007202720092029200B202B200D202D200F202F2
)
,
.
INIT_14
(
256'h00000
000000000000000000000000000021F023F025F027F029F02BF02DF02FF
)
,
.
INIT_15
(
256'h000
A020A002A022A004A024A006A026A008A028A00AA02AA00CA02CA00EA02EA
)
,
.
INIT_16
(
256'h00
1A021A003A023A005A025A007A027A009A029A00BA02BA00DA02DA00FA02FA
)
,
.
INIT_17
(
256'h0000000000000
0000000000000000000000F002F004F006F008F00AF00CF00EF
)
,
.
INIT_18
(
256'h00000
0000000000000000000000000000200022002400260028002A002C002E
0
)
,
.
INIT_19
(
256'h000
602060026022600460246006602660086028600A602A600C602C600E602E6
)
,
.
INIT_1A
(
256'h00
1602160036023600560256007602760096029600B602B600D602D600F602F6
)
,
.
INIT_1B
(
256'h0000000000000
00000000000000000000010003000500070009000B000D000F
0
)
,
.
INIT_1C
(
256'h000
E020E002E022E004E024E006E026E008E028E00AE02AE00CE02CE00EE02EE
)
,
.
INIT_1D
(
256'h0000000000000
00000000000000000000001002100410061008100A100C100E1
)
,
.
INIT_1E
(
256'h0000000000000
000000000000000001E003E005E007E009E00BE00DE00FE01FE
)
,
.
INIT_04
(
256'h00000
4EE04ED000004EB
00000000000000000000000000000000000000000000
)
,
.
INIT_05
(
256'h00000
3FE03FD000003FB00000000000003F70000000000000000000000000000
)
,
.
INIT_06
(
256'h000000000000000000000000000000000
0000000000000000000000000000000
)
,
.
INIT_07
(
256'h0000000000000
3FC000000000000000000000000000000000000000000000000
)
,
.
INIT_08
(
256'h00000
40E040D0000040B
00000000000000000000000000000000000000000000
)
,
.
INIT_09
(
256'h00000
21E021D041C021B041A0419000002170416041500000413000000000000
)
,
.
INIT_0A
(
256'h00000
2010202040C0204040A0409000002080406040500000403000000000000
)
,
.
INIT_0B
(
256'h00
0000000000031C0000020F0200040700000210021F04140218041204110000
)
,
.
INIT_0C
(
256'h00000
26E026D0478026B047F0470000002670460046F0000057C000000000000
)
,
.
INIT_0D
(
256'h000
000000000027C0000027A0279046800000276027504640273046204610000
)
,
.
INIT_0E
(
256'h00
0000000000026C0000026A02690477000002660265047B0263047D047E0000
)
,
.
INIT_0F
(
256'h000000000000000000000000000000000
0000000000002740000027202710000
)
,
.
INIT_10
(
256'h00000
48E048D0000048B
00000000000000000000000000000000000000000000
)
,
.
INIT_11
(
256'h00000
29E029D049C029B049A0499000002970496049500000493000000000000
)
,
.
INIT_12
(
256'h00000
2810282048C0284048A0489000002880486048500000483000000000000
)
,
.
INIT_13
(
256'h00
0000000000039C0000028F0280048700000290029F04940298049204910000
)
,
.
INIT_14
(
256'h00000
6AE06AD04B806AB04BF04B0000002A704A004AF0000055C000000000000
)
,
.
INIT_15
(
256'h000
002BE02BD06BC02BB06BA06B904A802B706B606B504A406B304A204A10000
)
,
.
INIT_16
(
256'h00
0002A102A206AC02A406AA06A904B702A806A606A504BB06A304BD04BE0000
)
,
.
INIT_17
(
256'h0000000000000
3BC000002AF02A004A7000002B002BF06B402B806B206B10000
)
,
.
INIT_18
(
256'h00000
6CE06CD04D806CB04DF04D0000002C704C004CF0000053C00000000000
0
)
,
.
INIT_19
(
256'h000
002DE02DD06DC02DB06DA06D904C802D706D606D504C406D304C204C10000
)
,
.
INIT_1A
(
256'h00
0002C102C206CC02C406CA06C904D702C806C606C504DB06C304DD04DE0000
)
,
.
INIT_1B
(
256'h0000000000000
3DC000002CF02C004C7000002D002DF06D402D806D206D1000
0
)
,
.
INIT_1C
(
256'h000
002EE02ED04F802EB04FF04F0000002E704E004EF00000000000000000000
)
,
.
INIT_1D
(
256'h0000000000000
2FC000002FA02F904E8000002F602F504E402F304E204E10000
)
,
.
INIT_1E
(
256'h0000000000000
2EC000002EA02E904F7000002E602E504FB02E304FD04FE0000
)
,
.
INIT_1F
(
256'h0000000000000000000000000000000000000000000000000000000000000000
)
,
.
INIT_20
(
256'h0000000000000000000000000000000000000000000000000000000000000000
)
,
.
INIT_21
(
256'h00000
00000000000000000000000021E023E025E027E029E02BE02DE02FE03FE
)
,
.
INIT_22
(
256'h00000
0000000000000000000000000000201022102410261028102A102C102E1
)
,
.
INIT_23
(
256'h00
1102110031023100510251007102710091029100B102B100D102D100F102F1
)
,
.
INIT_24
(
256'h00000
0000000000000000000000000000210023002500270029002B002D002F
0
)
,
.
INIT_25
(
256'h000
902090029022900490249006902690089028900A902A900C902C900E902E9
)
,
.
INIT_26
(
256'h00
1902190039023900590259007902790099029900B902B900D902D900F902F9
)
,
.
INIT_27
(
256'h0000000000000
00000000000000000000000002000400060008000A000C000E
0
)
,
.
INIT_28
(
256'h00000
000000000000000000000000000020F022F024F026F028F02AF02CF02EF
)
,
.
INIT_29
(
256'h000
502050025022500450245006502650085028500A502A500C502C500E502E5
)
,
.
INIT_2A
(
256'h00
1502150035023500550255007502750095029500B502B500D502D500F502F5
)
,
.
INIT_2B
(
256'h0000000000000
0000000000000000000001F003F005F007F009F00BF00DF00FF
)
,
.
INIT_2C
(
256'h000
D020D002D022D004D024D006D026D008D028D00AD02AD00CD02CD00ED02ED
)
,
.
INIT_2D
(
256'h0000000000000
00000000000000000000002002200420062008200A200C200E2
)
,
.
INIT_2E
(
256'h0000000000000
000000000000000001D003D005D007D009D00BD00DD00FD01FD
)
,
.
INIT_2F
(
256'h000000000000000000000000000000000000000000000
000000000000000
0000
)
,
.
INIT_30
(
256'h00000
000000000000000000000000000031C033C035C037C039C03BC03DC03FC
)
,
.
INIT_31
(
256'h000
302030023022300430243006302630083028300A302A300C302C300E302E3
)
,
.
INIT_32
(
256'h00
1302130033023300530253007302730093029300B302B300D302D300F302F3
)
,
.
INIT_33
(
256'h0000000000000
00000000000000000000018003800580078009800B800D800F8
)
,
.
INIT_34
(
256'h000
B020B002B022B004B024B006B026B008B028B00AB02AB00CB02CB00EB02EB
)
,
.
INIT_35
(
256'h0000000000000
00000000000000000000004002400440064008400A400C400E4
)
,
.
INIT_36
(
256'h0000000000000
000000000000000001B003B005B007B009B00BB00DB00FB01FB
)
,
.
INIT_37
(
256'h000000000000000000000000000000000000000000000
000000000000000
0000
)
,
.
INIT_38
(
256'h00000000000000000000000000000000000
7002700470067008700A700C700E7
)
,
.
INIT_39
(
256'h00000000000000000000000000000000000
8002800480068008800A800C800E8
)
,
.
INIT_3A
(
256'h00000000000000000000000000000
017003700570077009700B700D700F701F7
)
,
.
INIT_3B
(
256'h000000000000000000000000000000000000000000000
000000000000000
0000
)
,
.
INIT_21
(
256'h00000
2FE02FD04FC02FB04FA04F9000002F704F604F5000004F3000000000000
)
,
.
INIT_22
(
256'h00000
2E102E204EC02E404EA04E9000002E804E604E5000004E3000000000000
)
,
.
INIT_23
(
256'h00
00000000000000000002EF02E004E7000002F002FF04F402F804F204F10000
)
,
.
INIT_24
(
256'h00000
62E062D0438062B043F0430000002270420042F000005DC00000000000
0
)
,
.
INIT_25
(
256'h000
0023E023D063C023B063A0639042802370636063504240633042204210000
)
,
.
INIT_26
(
256'h00
0002210222062C0224062A06290437022806260625043B0623043D043E0000
)
,
.
INIT_27
(
256'h0000000000000
33C0000022F0220042700000230023F0634023806320631000
0
)
,
.
INIT_28
(
256'h00000
64E064D0458064B045F0450000002470440044F000005BC000000000000
)
,
.
INIT_29
(
256'h000
0025E025D065C025B065A0659044802570656065504440653044204410000
)
,
.
INIT_2A
(
256'h00
0002410242064C0244064A06490457024806460645045B0643045D045E0000
)
,
.
INIT_2B
(
256'h0000000000000
35C0000024F0240044700000250025F06540258065206510000
)
,
.
INIT_2C
(
256'h000
0028E028D0498028B049F0490000002870480048F0000059C000000000000
)
,
.
INIT_2D
(
256'h0000000000000
29C0000029A0299048800000296029504840293048204810000
)
,
.
INIT_2E
(
256'h0000000000000
28C0000028A02890497000002860285049B0283049D049E0000
)
,
.
INIT_2F
(
256'h000000000000000000000000000000000000000000000
294000002920291
0000
)
,
.
INIT_30
(
256'h00000
46E046D0000046B00000000000000000000000000000000000000000000
)
,
.
INIT_31
(
256'h000
0027E027D047C027B047A0479000002770476047500000473000000000000
)
,
.
INIT_32
(
256'h00
0002610262046C0264046A0469000002680466046500000463000000000000
)
,
.
INIT_33
(
256'h0000000000000
37C0000026F0260046700000270027F04740278047204710000
)
,
.
INIT_34
(
256'h000
0020E020D0418020B041F0410000002070400040F0000051C000000000000
)
,
.
INIT_35
(
256'h0000000000000
21C0000021A0219040800000216021504040213040204010000
)
,
.
INIT_36
(
256'h0000000000000
20C0000020A02090417000002060205041B0203041D041E0000
)
,
.
INIT_37
(
256'h000000000000000000000000000000000000000000000
214000002120211
0000
)
,
.
INIT_38
(
256'h00000000000000000000000000000000000
000000000000005FC000000000000
)
,
.
INIT_39
(
256'h00000000000000000000000000000000000
00000000000000000000000000000
)
,
.
INIT_3A
(
256'h00000000000000000000000000000
5F700000000000005FB000005FD05FE0000
)
,
.
INIT_3B
(
256'h000000000000000000000000000000000000000000000
2F4000002F202F1
0000
)
,
.
INIT_3C
(
256'h0000000000000000000000000000000000000000000000000000000000000000
)
,
.
INIT_3D
(
256'h0000000000000000000000000000000000000000000000000000000000000000
)
,
.
INIT_3E
(
256'h0000000000000000000000000000000000000000000000000000000000000000
)
...
...
host/gtx_8x10enc.v
View file @
9f7bbe7d
...
...
@@ -65,8 +65,8 @@ always @ (posedge clk)
// select encoded bytes depending on a previous disparity
assign
enc0
=
~
disparity
&
table0
[
19
:
10
]
|
disparity
&
table0
[
9
:
0
]
;
assign
enc1
=
~
disparity_interm
&
table1
[
19
:
10
]
|
disparity_interm
&
table1
[
9
:
0
]
;
assign
enc0
=
{
10
{~
disparity
}}
&
table0
[
19
:
10
]
|
{
10
{
disparity
}}
&
table0
[
9
:
0
]
;
assign
enc1
=
{
10
{~
disparity_interm
}}
&
table1
[
19
:
10
]
|
{
10
{
disparity_interm
}}
&
table1
[
9
:
0
]
;
// latch output data
reg
[
19
:
0
]
outdata_l
;
...
...
host/gtx_8x10enc_geninit.py
View file @
9f7bbe7d
...
...
@@ -2,13 +2,15 @@ mem7f = []
for
i
in
range
(
0x80
):
mem7f
.
append
(
0
);
i
=
0
for
line
in
open
(
'gtx_8x10enc_init_stub.v'
)
.
readlines
():
addr
=
int
(
'0b'
+
line
.
split
()[
0
],
2
)
a
=
int
(
'0b'
+
line
.
split
()[
1
],
2
)
b
=
int
(
'0b'
+
line
.
split
()[
2
],
2
)
mem7f
[
addr
>>
3
]
=
(((
mem7f
[
addr
>>
3
]
<<
16
)
+
b
)
<<
16
)
+
a
i
+=
1
# mem7f[addr >> 3] = (((mem7f[addr >> 3] << 16) + b) << 16) + a
to_mem
=
(
b
<<
10
)
+
a
# if addr == 0x1bc or addr == 0x4a:
# print addr, ' = ', to_mem, ' : ', b, ' :', a
mem7f
[
addr
>>
3
]
=
mem7f
[
addr
>>
3
]
+
(
to_mem
<<
((
addr
%
8
)
*
32
))
for
i
in
range
(
0x80
):
print
', .INIT_
%02
X
\t
(256
\'
h
%064
X)'
%
(
i
,
mem7f
[
i
])
host/gtx_8x10enc_init.v
View file @
9f7bbe7d
,
.
INIT_00
(
256'h0
18B0274022B01D4012B02D40314031B00AB03540294029B0194019B0074038B
)
,
.
INIT_01
(
256'h00
6B03940254025B0154015B0344034B00D400DB02C402CB01C401CB028B0174
)
,
.
INIT_02
(
256'h0
24B01B40234023B0134013B0324032B00B400BB02A402AB01A401AB005B03A4
)
,
.
INIT_03
(
256'h00
CB03340264026B0164016B009B036400E400EB011B02E4021B01E4014B02B4
)
,
.
INIT_04
(
256'h0
1890279022901D9012902D90319031900A9035902990299019901990079038
9
)
,
.
INIT_05
(
256'h00
69039902590259015901590349034900D900D902C902C901C901C902890179
)
,
.
INIT_06
(
256'h0
24901B902390239013901390329032900B900B902A902A901A901A9005903A9
)
,
.
INIT_07
(
256'h00
C9033902690269016901690099036900E900E9011902E9021901E9014902B9
)
,
.
INIT_08
(
256'h0
1850275022501D5012502D50315031500A50355029502950195019500750385
)
,
.
INIT_09
(
256'h00
65039502550255015501550345034500D500D502C502C501C501C502850175
)
,
.
INIT_0A
(
256'h0
24501B502350235013501350325032500B500B502A502A501A501A5005503A5
)
,
.
INIT_0B
(
256'h00
C5033502650265016501650095036500E500E5011502E5021501E5014502B5
)
,
.
INIT_0C
(
256'h0
18C0273022C01D3012C02D30313031C00AC03530293029C0193019C0073038C
)
,
.
INIT_0D
(
256'h00
6C03930253025C0153015C0343034C00D300DC02C302CC01C301CC028C0173
)
,
.
INIT_0E
(
256'h0
24C01B30233023C0133013C0323032C00B300BC02A302AC01A301AC005C03A3
)
,
.
INIT_0F
(
256'h00
CC03330263026C0163016C009C036300E300EC011C02E3021C01E3014C02B
3
)
,
.
INIT_10
(
256'h0
18D0272022D01D2012D02D20312031D00AD03520292029D0192019D0072038D
)
,
.
INIT_11
(
256'h00
6D03920252025D0152015D0342034D00D200DD02C202CD01C201CD028D0172
)
,
.
INIT_12
(
256'h0
24D01B20232023D0132013D0322032D00B200BD02A202AD01A201AD005D03A2
)
,
.
INIT_13
(
256'h00
CD03320262026D0162016D009D036200E200ED011D02E2021D01E2014D02B2
)
,
.
INIT_14
(
256'h0
18A027A022A01DA012A02DA031A031A00AA035A029A029A019A019A007A038A
)
,
.
INIT_15
(
256'h00
6A039A025A025A015A015A034A034A00DA00DA02CA02CA01CA01CA028A017A
)
,
.
INIT_16
(
256'h0
24A01BA023A023A013A013A032A032A00BA00BA02AA02AA01AA01AA005A03AA
)
,
.
INIT_17
(
256'h00
CA033A026A026A016A016A009A036A00EA00EA011A02EA021A01EA014A02BA
)
,
.
INIT_18
(
256'h0
1860276022601D6012602D60316031600A60356029602960196019600760386
)
,
.
INIT_19
(
256'h00
66039602560256015601560346034600D600D602C602C601C601C602860176
)
,
.
INIT_1A
(
256'h0
24601B602360236013601360326032600B600B602A602A601A601A6005603A
6
)
,
.
INIT_1B
(
256'h00
C6033602660266016601660096036600E600E6011602E6021601E6014602B6
)
,
.
INIT_1C
(
256'h0
18E0271022E01D1012E02D10311031E00AE03510291029E0191019E0071038E
)
,
.
INIT_1D
(
256'h00
6E03910251025E0151015E0348034E00D100DE02C802CE01C801CE028E0171
)
,
.
INIT_1E
(
256'h0
24E01B102310237013101370321032E00B100B702A102AE01A101AE005E03A1
)
,
.
INIT_1F
(
256'h00
CE03310261026E0161016E009E036100E100EE011E02E1021E01E1014E02B1
)
,
.
INIT_00
(
256'h0
002E34700029B6600029765000D50AB00028F63000D48AD000D44AE000D18B9
)
,
.
INIT_01
(
256'h00
0D14BA00023B4E0002374D0002B36C00022F4B0002AB6A0002A769000D60A7
)
,
.
INIT_02
(
256'h0
00DA09700025B56000257550002D37400024F530002CB720002C771000D24B6
)
,
.
INIT_03
(
256'h00
0D28B5000D849E000D889D0002735C000D909B00026B5A00026759000D30B3
)
,
.
INIT_04
(
256'h0
009E24700099A66000996650009526B00098E6300094A6D0009466E00091A7
9
)
,
.
INIT_05
(
256'h00
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