Few more typos - now test is running ok on vdt

device/sata_phy_dev.v

@@ -293,7 +293,7 @@ ext_clock_buf(
     .ODIV2  ()
 );
 
-GTXE2_CHANNEL #(
+gtxe2_channel_wrapper #(
     .SIM_RECEIVER_DETECT_PASS               ("TRUE"),
     .SIM_TX_EIDLE_DRIVE_LEVEL               ("X"),
     .SIM_RESET_SPEEDUP                      ("FALSE"),
@@ -494,7 +494,7 @@ GTXE2_CHANNEL #(
     .RX_DFE_XYD_CFG                         (13'b0000000000000),
     .TX_PREDRIVER_MODE                      (1'b0)
 ) 
-gtx(
+gtx_wrapper(
     .CPLLFBCLKLOST                  (),
     .CPLLLOCK                       (cplllock),
     .CPLLLOCKDETCLK                 (cplllockdetclk),

wrapper/gtxe2_channel_wrapper.v

@@ -18,6 +18,7 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
  *******************************************************************************/
+`define OPEN_SOURCE_ONLY
 module gtxe2_channel_wrapper(
 // clocking ports, UG476 p.37
     input   [2:0]       CPLLREFCLKSEL,
@@ -553,7 +554,7 @@ parameter   RX_CLK25_DIV                 = 6;
 parameter   TX_CLK25_DIV                 = 6;
 
 `ifdef OPEN_SOURCE_ONLY
-GTXE2_CPL #(
+GTXE2_GPL #(
 `else // OPEN_SOURCE_ONLY
 GTXE2_CHANNEL #(
 `endif // OPEN_SOURCE_ONLY