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x393_sata
Commit 992333fa authored by Alexey Grebenkin's avatar Alexey Grebenkin
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Add top-level testbench

parent 5a15d6f2
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axi_regs.v
View file @ 992333fa
...@@ -95,7 +95,9 @@ module axi_regs( ...@@ -95,7 +95,9 @@ module axi_regs(
//reg [31:0] mem [3:0]; //reg [31:0] mem [3:0];
reg [32*16 - 1:0] mem; reg [32*16 - 1:0] mem;
`ifndef MAXI_NEW_IFACE `ifndef MAXI_NEW_IFACE
/*
* Converntional MAXI interface from x393 project, uses fifos, writes to/reads from memory
*/
wire [31:0] bram_waddr; wire [31:0] bram_waddr;
wire [31:0] bram_raddr; wire [31:0] bram_raddr;
wire [31:0] bram_wdata; wire [31:0] bram_wdata;
...@@ -103,7 +105,11 @@ wire [31:0] bram_rdata; ...@@ -103,7 +105,11 @@ wire [31:0] bram_rdata;
wire [3:0] bram_wstb; wire [3:0] bram_wstb;
wire bram_wen; wire bram_wen;
wire bram_ren; wire bram_ren;
wire bram_regen;
// 'write into memory'
// for testing purposes the 'memory' is a set of registers for now
// later on will try to use them as an application level registers
genvar ii; genvar ii;
generate generate
for (ii = 0; ii < 16; ii = ii + 1) for (ii = 0; ii < 16; ii = ii + 1)
...@@ -118,17 +124,19 @@ begin: write_to_mem ...@@ -118,17 +124,19 @@ begin: write_to_mem
end end
endgenerate endgenerate
// read from memory. Interface's protocol assumes returning data to delay
reg [3:0] bram_raddr_r; reg [3:0] bram_raddr_r;
always @ (posedge ACLK) always @ (posedge ACLK)
bram_raddr_r <= bram_ren ? bram_raddr[3:0] : bram_raddr_r; bram_raddr_r <= bram_regen ? bram_raddr[3:0] : bram_raddr_r;
assign bram_rdata = mem[32*bram_raddr_r + 31-:32]; assign bram_rdata = mem[32*bram_raddr_r + 31-:32];
// Interface's instantiation
axibram_write #( axibram_write #(
.ADDRESS_BITS(32) .ADDRESS_BITS(32)
) )
axibram_write( axibram_write(
.aclk (ACLK), .aclk (ACLK),
.rst (~ARESETN), .rst (ARESETN),
.awaddr (AWADDR), .awaddr (AWADDR),
.awvalid (AWVALID), .awvalid (AWVALID),
.awready (AWREADY), .awready (AWREADY),
...@@ -160,8 +168,8 @@ axibram_read #( ...@@ -160,8 +168,8 @@ axibram_read #(
) )
axibram_read( axibram_read(
.aclk (ACLK), .aclk (ACLK),
.rst (~ARESETN), .rst (ARESETN),
.araddr ({1'b0,ARADDR}), .araddr (ARADDR),
.arvalid (ARVALID), .arvalid (ARVALID),
.arready (ARREADY), .arready (ARREADY),
.arid (ARID), .arid (ARID),
...@@ -180,7 +188,7 @@ axibram_read( ...@@ -180,7 +188,7 @@ axibram_read(
.bram_rclk (), .bram_rclk (),
.bram_raddr (bram_raddr), .bram_raddr (bram_raddr),
.bram_ren (bram_ren), .bram_ren (bram_ren),
.bram_regen (), .bram_regen (bram_regen),
.bram_rdata (bram_rdata) .bram_rdata (bram_rdata)
); );
`else `else
......
simul/build
View file @ 992333fa
...@@ -3,9 +3,13 @@ LOGFILE_PATH="bld.log" ...@@ -3,9 +3,13 @@ LOGFILE_PATH="bld.log"
rm a.out rm a.out
if [ "$SATA_PATH" == '' ] if [ "$SATA_PATH" == '' ]
then then
SATA_PATH=".." export SATA_PATH=".."
fi fi
iverilog $SATA_PATH/tb/tb_axiregs.v -f opts -stb $1 2>&1| tee $LOGFILE_PATH if [ "$UNISIMS_PATH" == '' ]
then
export UNISIMS_PATH="../../../../eddr3-src/eddr3/unisims"
fi
iverilog $SATA_PATH/tb/tb_top.v -f opts -stb $1 2>&1| tee $LOGFILE_PATH
#-y$SATA_PATH/x393/util_modules -I$SATA_PATH/x393/ -I$SATA_PATH/x393/axi/ $SATA_PATH/tb/tb_axiregs.v -I$SATA_PATH/ -I$SATA_PATH/tb/ #-y$SATA_PATH/x393/util_modules -I$SATA_PATH/x393/ -I$SATA_PATH/x393/axi/ $SATA_PATH/tb/tb_axiregs.v -I$SATA_PATH/ -I$SATA_PATH/tb/
simul/opts
View file @ 992333fa
-v ${SATA_PATH}/x393/simulation_modules/simul_axi_fifo_out.v
-y ${SATA_PATH}/x393/simulation_modules
-y ${UNISIMS_PATH}/
-y ${SATA_PATH}/x393/util_modules -y ${SATA_PATH}/x393/util_modules
+incdir+${SATA_PATH}/tb/ +incdir+${SATA_PATH}/tb/
+incdir+${SATA_PATH}/x393/ +incdir+${SATA_PATH}/x393/
......
tb/tb_top.v 0 → 100644
View file @ 992333fa
/*******************************************************************************
* Module: tb
* Date: 2015-07-11
* Author: Alexey
* Description: testbench for top.v
*
* Copyright (c) 2015 Elphel, Inc.
* tb_top.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* tb_top.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
/*
* using x393_testbench01.tf style, contains a lot of copy-pasted code from there
*/
`timescale 1ns/1ps
`include "top.v"
module tb #(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
`include "includes/x393_simulation_parameters.vh"
)
(
);
initial #1 $display("HI THERE");
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,tb);
end
reg [11:0] ARID_IN_r;
reg [31:0] ARADDR_IN_r;
reg [3:0] ARLEN_IN_r;
reg [2:0] ARSIZE_IN_r;
reg [1:0] ARBURST_IN_r;
reg [11:0] AWID_IN_r;
reg [31:0] AWADDR_IN_r;
reg [3:0] AWLEN_IN_r;
reg [2:0] AWSIZE_IN_r;
reg [1:0] AWBURST_IN_r;
reg [11:0] WID_IN_r;
reg [31:0] WDATA_IN_r;
reg [3:0] WSTRB_IN_r;
reg WLAST_IN_r;
reg DEBUG1, DEBUG2, DEBUG3;
reg [11:0] GLOBAL_WRITE_ID=0;
reg [11:0] GLOBAL_READ_ID=0;
reg [11:0] LAST_ARID; // last issued ARID
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [SIMUL_AXI_READ_WIDTH-1:0] SIMUL_AXI_ADDR_W;
// SuppressWarnings VEditor
wire SIMUL_AXI_MISMATCH;
// SuppressWarnings VEditor
reg [31:0] SIMUL_AXI_READ;
// SuppressWarnings VEditor
reg [SIMUL_AXI_READ_WIDTH-1:0] SIMUL_AXI_ADDR;
// SuppressWarnings VEditor
reg SIMUL_AXI_FULL; // some data available
wire SIMUL_AXI_EMPTY= ~rvalid && rready && (rid==LAST_ARID); //SuppressThisWarning VEditor : may be unused, just for simulation // use it to wait for?
reg [31:0] registered_rdata; // here read data from task
reg CLK;
reg RST;
reg AR_SET_CMD_r;
wire AR_READY;
reg AW_SET_CMD_r;
wire AW_READY;
reg W_SET_CMD_r;
wire W_READY;
reg [3:0] RD_LAG; // ready signal lag in axi read channel (0 - RDY=1, 1..15 - RDY is asserted N cycles after valid)
reg [3:0] B_LAG; // ready signal lag in axi arete response channel (0 - RDY=1, 1..15 - RDY is asserted N cycles after valid)
// Simulation modules interconnection
wire [11:0] arid;
wire [31:0] araddr;
wire [3:0] arlen;
wire [2:0] arsize;
wire [1:0] arburst;
// SuppressWarnings VEditor : assigned in $readmem(14) system task
wire [3:0] arcache;
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [2:0] arprot;
wire arvalid;
wire arready;
wire [11:0] awid;
wire [31:0] awaddr;
wire [3:0] awlen;
wire [2:0] awsize;
wire [1:0] awburst;
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [3:0] awcache;
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [2:0] awprot;
wire awvalid;
wire awready;
wire [11:0] wid;
wire [31:0] wdata;
wire [3:0] wstrb;
wire wlast;
wire wvalid;
wire wready;
wire [31:0] rdata;
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [11:0] rid;
wire rlast;
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [1:0] rresp;
wire rvalid;
wire rready;
wire rstb=rvalid && rready;
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [1:0] bresp;
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [11:0] bid;
wire bvalid;
wire bready;
integer NUM_WORDS_READ;
integer NUM_WORDS_EXPECTED;
reg [15:0] ENABLED_CHANNELS = 0; // currently enabled memory channels
// integer SCANLINE_CUR_X;
// integer SCANLINE_CUR_Y;
wire AXI_RD_EMPTY=NUM_WORDS_READ==NUM_WORDS_EXPECTED; //SuppressThisWarning VEditor : may be unused, just for simulation
wire [11:0] #(AXI_TASK_HOLD) ARID_IN = ARID_IN_r;
wire [31:0] #(AXI_TASK_HOLD) ARADDR_IN = ARADDR_IN_r;
wire [3:0] #(AXI_TASK_HOLD) ARLEN_IN = ARLEN_IN_r;
wire [2:0] #(AXI_TASK_HOLD) ARSIZE_IN = ARSIZE_IN_r;
wire [1:0] #(AXI_TASK_HOLD) ARBURST_IN = ARBURST_IN_r;
wire [11:0] #(AXI_TASK_HOLD) AWID_IN = AWID_IN_r;
wire [31:0] #(AXI_TASK_HOLD) AWADDR_IN = AWADDR_IN_r;
wire [3:0] #(AXI_TASK_HOLD) AWLEN_IN = AWLEN_IN_r;
wire [2:0] #(AXI_TASK_HOLD) AWSIZE_IN = AWSIZE_IN_r;
wire [1:0] #(AXI_TASK_HOLD) AWBURST_IN = AWBURST_IN_r;
wire [11:0] #(AXI_TASK_HOLD) WID_IN = WID_IN_r;
wire [31:0] #(AXI_TASK_HOLD) WDATA_IN = WDATA_IN_r;
wire [ 3:0] #(AXI_TASK_HOLD) WSTRB_IN = WSTRB_IN_r;
wire #(AXI_TASK_HOLD) WLAST_IN = WLAST_IN_r;
wire #(AXI_TASK_HOLD) AR_SET_CMD = AR_SET_CMD_r;
wire #(AXI_TASK_HOLD) AW_SET_CMD = AW_SET_CMD_r;
wire #(AXI_TASK_HOLD) W_SET_CMD = W_SET_CMD_r;
always #(CLKIN_PERIOD/2) CLK = ~CLK;
/*
* connect axi ports to the dut
*/
assign dut.ps7_i.FCLKCLK= {4{CLK}};
assign dut.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST};
// Read address
assign dut.ps7_i.MAXIGP0ARADDR= araddr;
assign dut.ps7_i.MAXIGP0ARVALID= arvalid;
assign arready= dut.ps7_i.MAXIGP0ARREADY;
assign dut.ps7_i.MAXIGP0ARID= arid;
assign dut.ps7_i.MAXIGP0ARLEN= arlen;
assign dut.ps7_i.MAXIGP0ARSIZE= arsize[1:0]; // arsize[2] is not used
assign dut.ps7_i.MAXIGP0ARBURST= arburst;
// Read data
assign rdata= dut.ps7_i.MAXIGP0RDATA;
assign rvalid= dut.ps7_i.MAXIGP0RVALID;
assign dut.ps7_i.MAXIGP0RREADY= rready;
assign rid= dut.ps7_i.MAXIGP0RID;
assign rlast= dut.ps7_i.MAXIGP0RLAST;
assign rresp= dut.ps7_i.MAXIGP0RRESP;
// Write address
assign dut.ps7_i.MAXIGP0AWADDR= awaddr;
assign dut.ps7_i.MAXIGP0AWVALID= awvalid;
assign awready= dut.ps7_i.MAXIGP0AWREADY;
//assign awready= AWREADY_AAAA;
assign dut.ps7_i.MAXIGP0AWID=awid;
// SuppressWarnings VEditor all
// wire [ 1:0] AWLOCK;
// SuppressWarnings VEditor all
// wire [ 3:0] AWCACHE;
// SuppressWarnings VEditor all
// wire [ 2:0] AWPROT;
assign dut.ps7_i.MAXIGP0AWLEN= awlen;
assign dut.ps7_i.MAXIGP0AWSIZE= awsize[1:0]; // awsize[2] is not used
assign dut.ps7_i.MAXIGP0AWBURST= awburst;
// SuppressWarnings VEditor all
// wire [ 3:0] AWQOS;
// Write data
assign dut.ps7_i.MAXIGP0WDATA= wdata;
assign dut.ps7_i.MAXIGP0WVALID= wvalid;
assign wready= dut.ps7_i.MAXIGP0WREADY;
assign dut.ps7_i.MAXIGP0WID= wid;
assign dut.ps7_i.MAXIGP0WLAST= wlast;
assign dut.ps7_i.MAXIGP0WSTRB= wstrb;
// Write response
assign bvalid= dut.ps7_i.MAXIGP0BVALID;
assign dut.ps7_i.MAXIGP0BREADY= bready;
assign bid= dut.ps7_i.MAXIGP0BID;
assign bresp= dut.ps7_i.MAXIGP0BRESP;
// Simulation modules
simul_axi_master_rdaddr
#(
.ID_WIDTH(12),
.ADDRESS_WIDTH(32),
.LATENCY(AXI_RDADDR_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.5),
.VALID_DELAY(4.0)
) simul_axi_master_rdaddr_i (
.clk(CLK),
.reset(RST),
.arid_in(ARID_IN[11:0]),
.araddr_in(ARADDR_IN[31:0]),
.arlen_in(ARLEN_IN[3:0]),
.arsize_in(ARSIZE_IN[2:0]),
.arburst_in(ARBURST_IN[1:0]),
.arcache_in(4'b0),
.arprot_in(3'b0), // .arprot_in(2'b0),
.arid(arid[11:0]),
.araddr(araddr[31:0]),
.arlen(arlen[3:0]),
.arsize(arsize[2:0]),
.arburst(arburst[1:0]),
.arcache(arcache[3:0]),
.arprot(arprot[2:0]),
.arvalid(arvalid),
.arready(arready),
.set_cmd(AR_SET_CMD), // latch all other input data at posedge of clock
.ready(AR_READY) // command/data FIFO can accept command
);
simul_axi_master_wraddr
#(
.ID_WIDTH(12),
.ADDRESS_WIDTH(32),
.LATENCY(AXI_WRADDR_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.5),
.VALID_DELAY(4.0)
) simul_axi_master_wraddr_i (
.clk(CLK),
.reset(RST),
.awid_in(AWID_IN[11:0]),
.awaddr_in(AWADDR_IN[31:0]),
.awlen_in(AWLEN_IN[3:0]),
.awsize_in(AWSIZE_IN[2:0]),
.awburst_in(AWBURST_IN[1:0]),
.awcache_in(4'b0),
.awprot_in(3'b0), //.awprot_in(2'b0),
.awid(awid[11:0]),
.awaddr(awaddr[31:0]),
.awlen(awlen[3:0]),
.awsize(awsize[2:0]),
.awburst(awburst[1:0]),
.awcache(awcache[3:0]),
.awprot(awprot[2:0]),
.awvalid(awvalid),
.awready(awready),
.set_cmd(AW_SET_CMD), // latch all other input data at posedge of clock
.ready(AW_READY) // command/data FIFO can accept command
);
simul_axi_master_wdata
#(
.ID_WIDTH(12),
.DATA_WIDTH(32),
.WSTB_WIDTH(4),
.LATENCY(AXI_WRDATA_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.2),
.VALID_DELAY(3.6)
) simul_axi_master_wdata_i (
.clk(CLK),
.reset(RST),
.wid_in(WID_IN[11:0]),
.wdata_in(WDATA_IN[31:0]),
.wstrb_in(WSTRB_IN[3:0]),
.wlast_in(WLAST_IN),
.wid(wid[11:0]),
.wdata(wdata[31:0]),
.wstrb(wstrb[3:0]),
.wlast(wlast),
.wvalid(wvalid),
.wready(wready),
.set_cmd(W_SET_CMD), // latch all other input data at posedge of clock
.ready(W_READY) // command/data FIFO can accept command
);
simul_axi_slow_ready simul_axi_slow_ready_read_i(
.clk(CLK),
.reset(RST), //input reset,
.delay(RD_LAG), //input [3:0] delay,
.valid(rvalid), // input valid,
.ready(rready) //output ready
);
simul_axi_slow_ready simul_axi_slow_ready_write_resp_i(
.clk(CLK),
.reset(RST), //input reset,
.delay(B_LAG), //input [3:0] delay,
.valid(bvalid), // input ADDRESS_NUMBER+2:0 valid,
.ready(bready) //output ready
);
simul_axi_read #(
.ADDRESS_WIDTH(SIMUL_AXI_READ_WIDTH)
) simul_axi_read_i(
.clk(CLK),
.reset(RST),
.last(rlast),
.data_stb(rstb),
.raddr(ARADDR_IN[SIMUL_AXI_READ_WIDTH+1:2]),
.rlen(ARLEN_IN),
.rcmd(AR_SET_CMD),
.addr_out(SIMUL_AXI_ADDR_W[SIMUL_AXI_READ_WIDTH-1:0]),
.burst(), // burst in progress - just debug
.err_out()); // data last does not match predicted or FIFO over/under run - just debug
`include "includes/x393_tasks01.vh"
// device-under-test instance
top dut(
);
// testing itself
`include "test_top.v"
endmodule
tb/test_axi_regs.v
View file @ 992333fa
...@@ -115,7 +115,7 @@ begin ...@@ -115,7 +115,7 @@ begin
repeat (10) repeat (10)
@ (posedge ACLK); @ (posedge ACLK);
AWVALID <= 1'b1; AWVALID <= 1'b1;
AWADDR <= 32'h4; AWADDR <= 32'h5;
AWID <= 1'b0; AWID <= 1'b0;
AWLOCK <= 1'b0; AWLOCK <= 1'b0;
AWCACHE <= 1'b0; AWCACHE <= 1'b0;
...@@ -144,7 +144,7 @@ begin ...@@ -144,7 +144,7 @@ begin
#170; #170;
repeat (10) repeat (10)
@ (posedge ACLK); @ (posedge ACLK);
ARADDR <= 32'h4; ARADDR <= 32'h5;
ARVALID <= 1'b1; ARVALID <= 1'b1;
ARID <= 1'b0; ARID <= 1'b0;
ARLOCK <= 1'b0; ARLOCK <= 1'b0;
...@@ -166,6 +166,125 @@ begin ...@@ -166,6 +166,125 @@ begin
end end
*/
// Simulation modules
simul_axi_master_rdaddr
#(
.ID_WIDTH(12),
.ADDRESS_WIDTH(32),
.LATENCY(AXI_RDADDR_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.5),
.VALID_DELAY(4.0)
) simul_axi_master_rdaddr_i (
.clk(CLK),
.reset(RST),
.arid_in(ARID_IN[11:0]),
.araddr_in(ARADDR_IN[31:0]),
.arlen_in(ARLEN_IN[3:0]),
.arsize_in(ARSIZE_IN[2:0]),
.arburst_in(ARBURST_IN[1:0]),
.arcache_in(4'b0),
.arprot_in(3'b0), // .arprot_in(2'b0),
.arid(arid[11:0]),
.araddr(araddr[31:0]),
.arlen(arlen[3:0]),
.arsize(arsize[2:0]),
.arburst(arburst[1:0]),
.arcache(arcache[3:0]),
.arprot(arprot[2:0]),
.arvalid(arvalid),
.arready(arready),
.set_cmd(AR_SET_CMD), // latch all other input data at posedge of clock
.ready(AR_READY) // command/data FIFO can accept command
);
simul_axi_master_wraddr
#(
.ID_WIDTH(12),
.ADDRESS_WIDTH(32),
.LATENCY(AXI_WRADDR_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.5),
.VALID_DELAY(4.0)
) simul_axi_master_wraddr_i (
.clk(CLK),
.reset(RST),
.awid_in(AWID_IN[11:0]),
.awaddr_in(AWADDR_IN[31:0]),
.awlen_in(AWLEN_IN[3:0]),
.awsize_in(AWSIZE_IN[2:0]),
.awburst_in(AWBURST_IN[1:0]),
.awcache_in(4'b0),
.awprot_in(3'b0), //.awprot_in(2'b0),
.awid(awid[11:0]),
.awaddr(awaddr[31:0]),
.awlen(awlen[3:0]),
.awsize(awsize[2:0]),
.awburst(awburst[1:0]),
.awcache(awcache[3:0]),
.awprot(awprot[2:0]),
.awvalid(awvalid),
.awready(awready),
.set_cmd(AW_SET_CMD), // latch all other input data at posedge of clock
.ready(AW_READY) // command/data FIFO can accept command
);
simul_axi_master_wdata
#(
.ID_WIDTH(12),
.DATA_WIDTH(32),
.WSTB_WIDTH(4),
.LATENCY(AXI_WRDATA_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.2),
.VALID_DELAY(3.6)
) simul_axi_master_wdata_i (
.clk(CLK),
.reset(RST),
.wid_in(WID_IN[11:0]),
.wdata_in(WDATA_IN[31:0]),
.wstrb_in(WSTRB_IN[3:0]),
.wlast_in(WLAST_IN),
.wid(wid[11:0]),
.wdata(wdata[31:0]),
.wstrb(wstrb[3:0]),
.wlast(wlast),
.wvalid(wvalid),
.wready(wready),
.set_cmd(W_SET_CMD), // latch all other input data at posedge of clock
.ready(W_READY) // command/data FIFO can accept command
);
simul_axi_slow_ready simul_axi_slow_ready_read_i(
.clk(CLK),
.reset(RST), //input reset,
.delay(RD_LAG), //input [3:0] delay,
.valid(rvalid), // input valid,
.ready(rready) //output ready
);
simul_axi_slow_ready simul_axi_slow_ready_write_resp_i(
.clk(CLK),
.reset(RST), //input reset,
.delay(B_LAG), //input [3:0] delay,
.valid(bvalid), // input ADDRESS_NUMBER+2:0 valid,
.ready(bready) //output ready
);
simul_axi_read #(
.ADDRESS_WIDTH(SIMUL_AXI_READ_WIDTH)
) simul_axi_read_i(
.clk(CLK),
.reset(RST),
.last(rlast),
.data_stb(rstb),
.raddr(ARADDR_IN[SIMUL_AXI_READ_WIDTH+1:2]),
.rlen(ARLEN_IN),
.rcmd(AR_SET_CMD),
.addr_out(SIMUL_AXI_ADDR_W[SIMUL_AXI_READ_WIDTH-1:0]),
.burst(), // burst in progress - just debug
.err_out()); // data last does not match predicted or FIFO over/under run - just debug
......
tb/test_top.v 0 → 100644
View file @ 992333fa
/*******************************************************************************
* Module: tb
* Date: 2015-07-11
* Author: Alexey
* Description: dut inputs control for for tb_top.v
*
* Copyright (c) 2015 Elphel, Inc.
* test_top.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_top.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
/*
* this file is included into tb_top.v due to the compatibility with x393 design testbench
*/
initial
begin
CLK =1'b0;
RST = 1'bx;
AR_SET_CMD_r = 1'b0;
AW_SET_CMD_r = 1'b0;
W_SET_CMD_r = 1'b0;
#500;
// $display ("x393_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.rst=%d",x393_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.rst);
#500;
RST = 1'b1;
NUM_WORDS_EXPECTED =0;
// #99000; // same as glbl
#9000; // same as glbl
repeat (20) @(posedge CLK) ;
RST =1'b0;
end
initial
#10000 $finish;
top.v
View file @ 992333fa
...@@ -18,7 +18,114 @@ ...@@ -18,7 +18,114 @@
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> . * along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/ *******************************************************************************/
module top( /*
* all signals' and modules' names and interconnections are taken from x393.v
* to make the final integration easier - just to make an instance of
* what is called now 'axi_regs' and connect it
*/
`include "system_defines.vh"
`include "axi_regs.v"
module top #(
`include "includes/x393_parameters.vh"
)
(
);
wire [3:0] fclk;
wire [3:0] frst;
wire axi_aclk;
wire axi_rst;
wire comb_rst;
wire [31:0] ARADDR;
wire ARVALID;
wire ARREADY;
wire [11:0] ARID;
wire [1:0] ARLOCK;
wire [3:0] ARCACHE;
wire [2:0] ARPROT;
wire [3:0] ARLEN;
wire [1:0] ARSIZE;
wire [1:0] ARBURST;
wire [3:0] ARQOS;
wire [31:0] RDATA;
wire RVALID;
wire RREADY;
wire [11:0] RID;
wire RLAST;
wire [1:0] RRESP;
wire [31:0] AWADDR;
wire AWVALID;
wire AWREADY;
wire [11:0] AWID;
wire [1:0] AWLOCK;
wire [3:0] AWCACHE;
wire [2:0] AWPROT;
wire [3:0] AWLEN;
wire [1:0] AWSIZE;
wire [1:0] AWBURST;
wire [3:0] AWQOS;
wire [31:0] WDATA;
wire WVALID;
wire WREADY;
wire [11:0] WID;
wire WLAST;
wire [3:0] WSTRB;
wire BVALID;
wire BREADY;
wire [11:0] BID;
wire [1:0] BRESP;
reg axi_rst_pre;
assign comb_rst=~frst[0] | frst[1];
always @(posedge comb_rst or posedge axi_aclk) begin
if (comb_rst) axi_rst_pre <= 1'b1;
else axi_rst_pre <= 1'b0;
end
BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
axi_regs axi_regs(
.ACLK (axi_aclk),
.ARESETN (axi_rst),
.ARADDR (ARADDR),
.ARVALID (ARVALID),
.ARREADY (ARREADY),
.ARID (ARID),
.ARLOCK (ARLOCK),
.ARCACHE (ARCACHE),
.ARPROT (ARPROT),
.ARLEN (ARLEN),
.ARSIZE (ARSIZE),
.ARBURST (ARBURST),
.ARQOS (ARQOS),
.RDATA (RDATA),
.RVALID (RVALID),
.RREADY (RREADY),
.RID (RID),
.RLAST (RLAST),
.RRESP (RRESP),
.AWADDR (AWADDR),
.AWVALID (AWVALID),
.AWREADY (AWREADY),
.AWID (AWID),
.AWLOCK (AWLOCK),
.AWCACHE (AWCACHE),
.AWPROT (AWPROT),
.AWLEN (AWLEN),
.AWSIZE (AWSIZE),
.AWBURST (AWBURST),
.AWQOS (AWQOS),
.WDATA (WDATA),
.WVALID (WVALID),
.WREADY (WREADY),
.WID (WID),
.WLAST (WLAST),
.WSTRB (WSTRB),
.BVALID (BVALID),
.BREADY (BREADY),
.BID (BID),
.BRESP (BRESP)
); );
PS7 ps7_i ( PS7 ps7_i (
...@@ -93,7 +200,7 @@ PS7 ps7_i ( ...@@ -93,7 +200,7 @@ PS7 ps7_i (
.EMIOENET1MDIOI(), // MDIO 1 MD data input, input .EMIOENET1MDIOI(), // MDIO 1 MD data input, input
// EMIO GPIO // EMIO GPIO
.EMIOGPIOO(), // EMIO GPIO Data out[63:0], output .EMIOGPIOO(), // EMIO GPIO Data out[63:0], output
.EMIOGPIOI(gpio_in[63:0]), // EMIO GPIO Data in[63:0], input .EMIOGPIOI(/*gpio_in[63:0]*/), // EMIO GPIO Data in[63:0], input
.EMIOGPIOTN(), // EMIO GPIO OutputEnable[63:0], output .EMIOGPIOTN(), // EMIO GPIO OutputEnable[63:0], output
// EMIO I2C 0 // EMIO I2C 0
.EMIOI2C0SCLO(), // I2C 0 SCL OUT, output // manual says input .EMIOI2C0SCLO(), // I2C 0 SCL OUT, output // manual says input
...@@ -332,51 +439,51 @@ PS7 ps7_i ( ...@@ -332,51 +439,51 @@ PS7 ps7_i (
// AXI PS Master GP1 // AXI PS Master GP1
// AXI PS Master GP1: Clock, Reset // AXI PS Master GP1: Clock, Reset
.MAXIGP1ACLK(), // AXI PS Master GP1 Clock , input .MAXIGP1ACLK (axi_aclk), // AXI PS Master GP1 Clock , input
.MAXIGP1ARESETN(), // AXI PS Master GP1 Reset, output .MAXIGP1ARESETN (axi_rst), // AXI PS Master GP1 Reset, output
// AXI PS Master GP1: Read Address // AXI PS Master GP1: Read Address
.MAXIGP1ARADDR(), // AXI PS Master GP1 ARADDR[31:0], output .MAXIGP1ARADDR (ARADDR), // AXI PS Master GP1 ARADDR[31:0], output
.MAXIGP1ARVALID(), // AXI PS Master GP1 ARVALID, output .MAXIGP1ARVALID (ARVALID), // AXI PS Master GP1 ARVALID, output
.MAXIGP1ARREADY(), // AXI PS Master GP1 ARREADY, input .MAXIGP1ARREADY (ARREADY), // AXI PS Master GP1 ARREADY, input
.MAXIGP1ARID(), // AXI PS Master GP1 ARID[11:0], output .MAXIGP1ARID (ARID), // AXI PS Master GP1 ARID[11:0], output
.MAXIGP1ARLOCK(), // AXI PS Master GP1 ARLOCK[1:0], output .MAXIGP1ARLOCK (ARLOCK), // AXI PS Master GP1 ARLOCK[1:0], output
.MAXIGP1ARCACHE(), // AXI PS Master GP1 ARCACHE[3:0], output .MAXIGP1ARCACHE (ARCACHE), // AXI PS Master GP1 ARCACHE[3:0], output
.MAXIGP1ARPROT(), // AXI PS Master GP1 ARPROT[2:0], output .MAXIGP1ARPROT (ARPROT), // AXI PS Master GP1 ARPROT[2:0], output
.MAXIGP1ARLEN(), // AXI PS Master GP1 ARLEN[3:0], output .MAXIGP1ARLEN (ARLEN), // AXI PS Master GP1 ARLEN[3:0], output
.MAXIGP1ARSIZE(), // AXI PS Master GP1 ARSIZE[1:0], output .MAXIGP1ARSIZE (ARSIZE), // AXI PS Master GP1 ARSIZE[1:0], output
.MAXIGP1ARBURST(), // AXI PS Master GP1 ARBURST[1:0], output .MAXIGP1ARBURST (ARBURST), // AXI PS Master GP1 ARBURST[1:0], output
.MAXIGP1ARQOS(), // AXI PS Master GP1 ARQOS[3:0], output .MAXIGP1ARQOS (ARQOS), // AXI PS Master GP1 ARQOS[3:0], output
// AXI PS Master GP1: Read Data // AXI PS Master GP1: Read Data
.MAXIGP1RDATA(), // AXI PS Master GP1 RDATA[31:0], input .MAXIGP1RDATA (RDATA), // AXI PS Master GP1 RDATA[31:0], input
.MAXIGP1RVALID(), // AXI PS Master GP1 RVALID, input .MAXIGP1RVALID (RVALID), // AXI PS Master GP1 RVALID, input
.MAXIGP1RREADY(), // AXI PS Master GP1 RREADY, output .MAXIGP1RREADY (RREADY), // AXI PS Master GP1 RREADY, output
.MAXIGP1RID(), // AXI PS Master GP1 RID[11:0], input .MAXIGP1RID (RID), // AXI PS Master GP1 RID[11:0], input
.MAXIGP1RLAST(), // AXI PS Master GP1 RLAST, input .MAXIGP1RLAST (RLAST), // AXI PS Master GP1 RLAST, input
.MAXIGP1RRESP(), // AXI PS Master GP1 RRESP[1:0], input .MAXIGP1RRESP (RRESP), // AXI PS Master GP1 RRESP[1:0], input
// AXI PS Master GP1: Write Address // AXI PS Master GP1: Write Address
.MAXIGP1AWADDR(), // AXI PS Master GP1 AWADDR[31:0], output .MAXIGP1AWADDR (AWADDR), // AXI PS Master GP1 AWADDR[31:0], output
.MAXIGP1AWVALID(), // AXI PS Master GP1 AWVALID, output .MAXIGP1AWVALID (AWVALID), // AXI PS Master GP1 AWVALID, output
.MAXIGP1AWREADY(), // AXI PS Master GP1 AWREADY, input .MAXIGP1AWREADY (AWREADY), // AXI PS Master GP1 AWREADY, input
.MAXIGP1AWID(), // AXI PS Master GP1 AWID[11:0], output .MAXIGP1AWID (AWID), // AXI PS Master GP1 AWID[11:0], output
.MAXIGP1AWLOCK(), // AXI PS Master GP1 AWLOCK[1:0], output .MAXIGP1AWLOCK (AWLOCK), // AXI PS Master GP1 AWLOCK[1:0], output
.MAXIGP1AWCACHE(), // AXI PS Master GP1 AWCACHE[3:0], output .MAXIGP1AWCACHE (AWCACHE), // AXI PS Master GP1 AWCACHE[3:0], output
.MAXIGP1AWPROT(), // AXI PS Master GP1 AWPROT[2:0], output .MAXIGP1AWPROT (AWPROT), // AXI PS Master GP1 AWPROT[2:0], output
.MAXIGP1AWLEN(), // AXI PS Master GP1 AWLEN[3:0], output .MAXIGP1AWLEN (AWLEN), // AXI PS Master GP1 AWLEN[3:0], output
.MAXIGP1AWSIZE(), // AXI PS Master GP1 AWSIZE[1:0], output .MAXIGP1AWSIZE (AWSIZE), // AXI PS Master GP1 AWSIZE[1:0], output
.MAXIGP1AWBURST(), // AXI PS Master GP1 AWBURST[1:0], output .MAXIGP1AWBURST (AWBURST), // AXI PS Master GP1 AWBURST[1:0], output
.MAXIGP1AWQOS(), // AXI PS Master GP1 AWQOS[3:0], output .MAXIGP1AWQOS (AWQOS), // AXI PS Master GP1 AWQOS[3:0], output
// AXI PS Master GP1: Write Data // AXI PS Master GP1: Write Data
.MAXIGP1WDATA(), // AXI PS Master GP1 WDATA[31:0], output .MAXIGP1WDATA (WDATA), // AXI PS Master GP1 WDATA[31:0], output
.MAXIGP1WVALID(), // AXI PS Master GP1 WVALID, output .MAXIGP1WVALID (WVALID), // AXI PS Master GP1 WVALID, output
.MAXIGP1WREADY(), // AXI PS Master GP1 WREADY, input .MAXIGP1WREADY (WREADY), // AXI PS Master GP1 WREADY, input
.MAXIGP1WID(), // AXI PS Master GP1 WID[11:0], output .MAXIGP1WID (WID), // AXI PS Master GP1 WID[11:0], output
.MAXIGP1WLAST(), // AXI PS Master GP1 WLAST, output .MAXIGP1WLAST (WLAST), // AXI PS Master GP1 WLAST, output
.MAXIGP1WSTRB(), // AXI PS Master GP1 WSTRB[3:0], output .MAXIGP1WSTRB (WSTRB), // AXI PS Master GP1 WSTRB[3:0], output
// AXI PS Master GP1: Write Responce // AXI PS Master GP1: Write Responce
.MAXIGP1BVALID(), // AXI PS Master GP1 BVALID, input .MAXIGP1BVALID (BVALID), // AXI PS Master GP1 BVALID, input
.MAXIGP1BREADY(), // AXI PS Master GP1 BREADY, output .MAXIGP1BREADY (BREADY), // AXI PS Master GP1 BREADY, output
.MAXIGP1BID(), // AXI PS Master GP1 BID[11:0], input .MAXIGP1BID (BID), // AXI PS Master GP1 BID[11:0], input
.MAXIGP1BRESP(), // AXI PS Master GP1 BRESP[1:0], input .MAXIGP1BRESP (BRESP), // AXI PS Master GP1 BRESP[1:0], input
// AXI PS Slave GP0 // AXI PS Slave GP0
// AXI PS Slave GP0: Clock, Reset // AXI PS Slave GP0: Clock, Reset
......
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