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x393_sata
Commit 98d19134 authored by Andrey Filippov's avatar Andrey Filippov
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allowing CTBA align to just 8 bytes, not 128

parent 8961bd29
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.project
View file @ 98d19134
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160228005230775.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160229131258090.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160228005230775.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160229131258090.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160228005230775.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160229131258090.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160228005230775.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160229131258090.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160228005230775.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160229131258090.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160228005230775.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160229131258090.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160228005230775.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160229131105264.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160228005230775.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160229131258090.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160228005230775.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160229131105264.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160228005230775.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160229131258090.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160228005230775.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160229131105264.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-phys.dcp</name> <name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160228005230775.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160229131258090.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-power.dcp</name> <name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160228005230775.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160229131258090.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt.dcp</name> <name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160228005230775.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160229131258090.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-place.dcp</name> <name>vivado_state/x393_sata-place.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160228005230775.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160229131258090.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-route.dcp</name> <name>vivado_state/x393_sata-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160228005230775.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160229131258090.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-synth.dcp</name> <name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160228005230775.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160229131105264.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
ahci/ahci_dma.v
View file @ 98d19134
...@@ -41,7 +41,9 @@ module ahci_dma ( ...@@ -41,7 +41,9 @@ module ahci_dma (
input mclk, // for command/status input mclk, // for command/status
input hclk, // global clock to run axi_hp @ 150MHz input hclk, // global clock to run axi_hp @ 150MHz
// Control interface (@mclk) // Control interface (@mclk)
input [31:7] ctba, // command table base address // Documentation insists 6 LSBs should be 0, but AHCI driver seems to ignore it. Will align to just 128 bits.
// input [31:7] ctba, // command table base address
input [31:4] ctba, // command table base address
input ctba_ld, // load command table base address input ctba_ld, // load command table base address
input [15:0] prdtl, // number of entries in PRD table (valid at cmd_start) input [15:0] prdtl, // number of entries in PRD table (valid at cmd_start)
input dev_wr, // write to device (valid at start) input dev_wr, // write to device (valid at start)
...@@ -157,7 +159,8 @@ module ahci_dma ( ...@@ -157,7 +159,8 @@ module ahci_dma (
reg [31:0] ct_data_ram [0:31]; reg [31:0] ct_data_ram [0:31];
reg [3:0] int_data_addr; // internal (ct,prd) data address reg [3:0] int_data_addr; // internal (ct,prd) data address
reg [31:7] ctba_r; // reg [31:7] ctba_r;
reg [31:4] ctba_r; // Seems that AHCI driver ignores requirement to have 6 LSB==0
reg [15:0] prdtl_mclk; reg [15:0] prdtl_mclk;
wire cmd_start_hclk; wire cmd_start_hclk;
reg prd_start_r; reg prd_start_r;
...@@ -342,7 +345,8 @@ module ahci_dma ( ...@@ -342,7 +345,8 @@ module ahci_dma (
if (ct_re[0]) ct_data_reg <= ct_data_ram[ct_addr]; if (ct_re[0]) ct_data_reg <= ct_data_ram[ct_addr];
if (ct_re[1]) ct_data <= ct_data_reg; if (ct_re[1]) ct_data <= ct_data_reg;
if (ctba_ld) ctba_r <= ctba[31:7]; // if (ctba_ld) ctba_r <= ctba[31:7];
if (ctba_ld) ctba_r <= ctba[31:4];
if (cmd_start) prdtl_mclk <= prdtl; if (cmd_start) prdtl_mclk <= prdtl;
...@@ -395,7 +399,8 @@ module ahci_dma ( ...@@ -395,7 +399,8 @@ module ahci_dma (
else if (cmd_start_hclk) prd_enabled <= 0; else if (cmd_start_hclk) prd_enabled <= 0;
if (cmd_start_hclk) ct_maddr[31:4] <= {ctba_r[31:7],3'b0}; // if (cmd_start_hclk) ct_maddr[31:4] <= {ctba_r[31:7],3'b0};
if (cmd_start_hclk) ct_maddr[31:4] <= ctba_r[31:4];
else if (ct_done) ct_maddr[31:4] <= ct_maddr[31:4] + 8; // 16; else if (ct_done) ct_maddr[31:4] <= ct_maddr[31:4] + 8; // 16;
else if (wcount_set) ct_maddr[31:4] <= ct_maddr[31:4] + 1; else if (wcount_set) ct_maddr[31:4] <= ct_maddr[31:4] + 1;
......
ahci/ahci_top.v
View file @ 98d19134
...@@ -884,7 +884,8 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0] ...@@ -884,7 +884,8 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0]
.hrst (hrst), // input .hrst (hrst), // input
.mclk (mclk), // input .mclk (mclk), // input
.hclk (hclk), // input .hclk (hclk), // input
.ctba (regs_dout[31:7]),// input[31:7] // .ctba (regs_dout[31:7]),// input[31:7]
.ctba (regs_dout[31:4]),// input[31:4]
.ctba_ld (ctba_ld), // input .ctba_ld (ctba_ld), // input
.prdtl (prdtl), // input[15:0] .prdtl (prdtl), // input[15:0]
.dev_wr (dev_wr), // input .dev_wr (dev_wr), // input
......
py393sata/x393sata.py
View file @ 98d19134
...@@ -1236,8 +1236,8 @@ mem.mem_save('/mnt/mmc/regs_dump',0x80000000,0x3000) ...@@ -1236,8 +1236,8 @@ mem.mem_save('/mnt/mmc/regs_dump',0x80000000,0x3000)
_=mem.mem_dump(0x3813fff8,0x2,4) _=mem.mem_dump(0x3813fff8,0x2,4)
mem.mem_save('/mnt/mmc/data/regs_dump_01',0x80000000,0x3000) mem.mem_save('/mnt/mmc/data/regs_dump_04',0x80000000,0x3000)
mem.mem_save('/mnt/mmc/data/mem0x3000_dump_01',0x38140000,0x13e000) mem.mem_save('/mnt/mmc/data/mem0x3000_dump_04',0x38140000,0x13e000)
......
tb/tb_ahci.tf
View file @ 98d19134
...@@ -800,10 +800,13 @@ localparam HBA_PORT0_OFFS32 = 'h40; ...@@ -800,10 +800,13 @@ localparam HBA_PORT0_OFFS32 = 'h40;
localparam PXSIG_OFFS32 = HBA_OFFS32 + HBA_PORT0_OFFS32 + 'h9; localparam PXSIG_OFFS32 = HBA_OFFS32 + HBA_PORT0_OFFS32 + 'h9;
localparam PXTFD_OFFS32 = HBA_OFFS32 + HBA_PORT0_OFFS32 + 'h8; localparam PXTFD_OFFS32 = HBA_OFFS32 + HBA_PORT0_OFFS32 + 'h8;
localparam SYS_MEM_START = 32'h3fffc000; // 16384 bytes (4096 DWORDs of teh system memory for R/W over AXI_HP) //localparam SYS_MEM_START = 32'h3fffc000; // 16384 bytes (4096 DWORDs of the system memory for R/W over AXI_HP)
localparam SYS_MEM_START = 32'h24180000; // 16384 bytes (4096 DWORDs of the system memory for R/W over AXI_HP)
localparam SYS_MEM_SIZE = 16384; // bytes - size of system memory localparam SYS_MEM_SIZE = 16384; // bytes - size of system memory
// realtive to the system memory area // realtive to the system memory area
localparam COMMAND_TABLE = 32'h3f00; // 256 bytes for a command table in the system memory ///localparam COMMAND_TABLE = 32'h3f00; // 256 bytes for a command table in the system memory
localparam COMMAND_TABLE = 32'h1000; // 256 bytes for a command table in the system memory
//0x24181000
localparam IDENTIFY_BUF = 32'h3d00; // 512 bytes for a command table in the system memory localparam IDENTIFY_BUF = 32'h3d00; // 512 bytes for a command table in the system memory
localparam PRD_OFFSET = 'h80; // start of PRD table - 128-th byte in command table localparam PRD_OFFSET = 'h80; // start of PRD table - 128-th byte in command table
localparam ATA_IDFY = 'hec; // Identify command localparam ATA_IDFY = 'hec; // Identify command
......
tb_ahci_01.sav
View file @ 98d19134
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