Commit 98d19134 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

allowing CTBA align to just 8 bytes, not 128

parent 8961bd29
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+17 −17
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@@ -52,87 +52,87 @@
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+9 −4
Original line number Diff line number Diff line
@@ -41,7 +41,9 @@ module ahci_dma (
    input                         mclk, // for command/status
    input                         hclk,   // global clock to run axi_hp @ 150MHz
    // Control interface  (@mclk)
    input                  [31:7] ctba,         // command table base address
    // Documentation insists 6 LSBs should be 0, but AHCI driver seems to ignore it. Will align to just 128 bits.
//    input                  [31:7] ctba,         // command table base address
    input                  [31:4] ctba,         // command table base address
    input                         ctba_ld,      // load command table base address
    input                  [15:0] prdtl,        // number of entries in PRD table (valid at cmd_start)
    input                         dev_wr,       // write to device (valid at start)
@@ -157,7 +159,8 @@ module ahci_dma (

    reg     [31:0] ct_data_ram [0:31];
    reg      [3:0] int_data_addr;    // internal (ct,prd) data address
    reg     [31:7] ctba_r;
//    reg     [31:7] ctba_r;
    reg     [31:4] ctba_r; // Seems that AHCI driver ignores requirement to have 6 LSB==0
    reg     [15:0] prdtl_mclk;
    wire           cmd_start_hclk;
    reg            prd_start_r;
@@ -342,7 +345,8 @@ module ahci_dma (
        if (ct_re[0]) ct_data_reg <=  ct_data_ram[ct_addr];
        if (ct_re[1]) ct_data <=      ct_data_reg;
        
        if (ctba_ld) ctba_r <=        ctba[31:7];
//        if (ctba_ld) ctba_r <=        ctba[31:7];
        if (ctba_ld) ctba_r <=        ctba[31:4];
        
        if (cmd_start) prdtl_mclk <=  prdtl;
        
@@ -395,7 +399,8 @@ module ahci_dma (
        else if (cmd_start_hclk)         prd_enabled <= 0;
    
    
        if (cmd_start_hclk)  ct_maddr[31:4] <= {ctba_r[31:7],3'b0};
//        if (cmd_start_hclk)  ct_maddr[31:4] <= {ctba_r[31:7],3'b0};
        if (cmd_start_hclk)  ct_maddr[31:4] <= ctba_r[31:4];
        else if (ct_done)    ct_maddr[31:4] <= ct_maddr[31:4] + 8; // 16;
        else if (wcount_set) ct_maddr[31:4] <= ct_maddr[31:4] + 1;
        
+2 −1
Original line number Diff line number Diff line
@@ -884,7 +884,8 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0]
        .hrst                  (hrst),          // input
        .mclk                  (mclk),          // input
        .hclk                  (hclk),          // input
        .ctba                  (regs_dout[31:7]),// input[31:7] 
//        .ctba                  (regs_dout[31:7]),// input[31:7] 
        .ctba                  (regs_dout[31:4]),// input[31:4] 
        .ctba_ld               (ctba_ld),       // input
        .prdtl                 (prdtl),         // input[15:0] 
        .dev_wr                (dev_wr),        // input
+2 −2
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@@ -1236,8 +1236,8 @@ mem.mem_save('/mnt/mmc/regs_dump',0x80000000,0x3000)


_=mem.mem_dump(0x3813fff8,0x2,4)
mem.mem_save('/mnt/mmc/data/regs_dump_01',0x80000000,0x3000)
mem.mem_save('/mnt/mmc/data/mem0x3000_dump_01',0x38140000,0x13e000)
mem.mem_save('/mnt/mmc/data/regs_dump_04',0x80000000,0x3000)
mem.mem_save('/mnt/mmc/data/mem0x3000_dump_04',0x38140000,0x13e000)



+5 −2
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@@ -800,10 +800,13 @@ localparam HBA_PORT0_OFFS32 = 'h40;
localparam PXSIG_OFFS32 = HBA_OFFS32 + HBA_PORT0_OFFS32 + 'h9; 
localparam PXTFD_OFFS32 = HBA_OFFS32 + HBA_PORT0_OFFS32 + 'h8;

localparam SYS_MEM_START = 32'h3fffc000; // 16384 bytes (4096 DWORDs of teh system memory for R/W over AXI_HP) 
//localparam SYS_MEM_START = 32'h3fffc000; // 16384 bytes (4096 DWORDs of the system memory for R/W over AXI_HP) 
localparam SYS_MEM_START = 32'h24180000; // 16384 bytes (4096 DWORDs of the system memory for R/W over AXI_HP) 
localparam SYS_MEM_SIZE =  16384; // bytes - size of system memory 
// realtive to the system memory area
localparam COMMAND_TABLE = 32'h3f00; // 256 bytes for a command table in the system memory
///localparam COMMAND_TABLE = 32'h3f00; // 256 bytes for a command table in the system memory
localparam COMMAND_TABLE = 32'h1000; // 256 bytes for a command table in the system memory
//0x24181000
localparam IDENTIFY_BUF =  32'h3d00; // 512 bytes for a command table in the system memory
localparam PRD_OFFSET = 'h80;        // start of PRD table - 128-th byte in command table
localparam ATA_IDFY =     'hec; // Identify command
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