Commit 90a85abd authored by Andrey Filippov's avatar Andrey Filippov
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trying to clean up resynchronization, make async reset propagate to control... 

trying to clean up resynchronization, make async reset propagate to control outputs even with no clocks
parent e150ca2f

.project

+1 −1
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ 
		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20151221195334703.log</location>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20151222105615706.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>