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Commit 90a85abd authored by Andrey Filippov's avatar Andrey Filippov
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trying to clean up resynchronization, make async reset propagate to control... 

trying to clean up resynchronization, make async reset propagate to control outputs even with no clocks
parent e150ca2f
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.project
View file @ 90a85abd
......@@ -46,7 +46,7 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20151221195334703.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20151222105615706.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
......
dma/top.v
View file @ 90a85abd
......@@ -49,83 +49,83 @@ wire axi_aclk;
wire axi_rst;
wire hclk;
wire comb_rst;
wire [31:0] ARADDR;
wire ARVALID;
wire ARREADY;
wire [11:0] ARID;
wire [3:0] ARLEN;
wire [1:0] ARSIZE;
wire [1:0] ARBURST;
wire [31:0] RDATA;
wire RVALID;
wire RREADY;
wire [11:0] RID;
wire RLAST;
wire [1:0] RRESP;
wire [31:0] AWADDR;
wire AWVALID;
wire AWREADY;
wire [11:0] AWID;
wire [3:0] AWLEN;
wire [1:0] AWSIZE;
wire [1:0] AWBURST;
wire [31:0] WDATA;
wire WVALID;
wire WREADY;
wire [11:0] WID;
wire WLAST;
wire [3:0] WSTRB;
wire BVALID;
wire BREADY;
wire [11:0] BID;
wire [1:0] BRESP;
wire [31:0] maxi1_araddr;
wire maxi1_arvalid;
wire maxi1_arready;
wire [11:0] maxi1_arid;
wire [3:0] maxi1_arlen;
wire [1:0] maxi1_arsize;
wire [1:0] maxi1_arburst;
wire [31:0] maxi1_rdata;
wire maxi1_rvalid;
wire maxi1_rready;
wire [11:0] maxi1_rid;
wire maxi1_rlast;
wire [1:0] maxi1_rresp;
wire [31:0] maxi1_awaddr;
wire maxi1_awvalid;
wire maxi1_awready;
wire [11:0] maxi1_awid;
wire [3:0] maxi1_awlen;
wire [1:0] maxi1_awsize;
wire [1:0] maxi1_awburst;
wire [31:0] maxi1_wdata;
wire maxi1_wvalid;
wire maxi1_wready;
wire [11:0] maxi1_wid;
wire maxi1_wlast;
wire [3:0] maxi1_wstb;
wire maxi1_bvalid;
wire maxi1_bready;
wire [11:0] maxi1_bid;
wire [1:0] maxi1_bresp;
reg axi_rst_pre;
// membridge
wire [31:0] afi0_awaddr; // output[31:0]
wire afi0_awvalid; // output
wire afi0_awready; // input
wire [ 5:0] afi0_awid; // output[5:0]
wire [ 1:0] afi0_awlock; // output[1:0]
wire [ 3:0] afi0_awcache; // output[3:0]
wire [ 2:0] afi0_awprot; // output[2:0]
wire [ 3:0] afi0_awlen; // output[3:0]
wire [ 1:0] afi0_awsize; // output[2:0]
wire [ 1:0] afi0_awburst; // output[1:0]
wire [ 3:0] afi0_awqos; // output[3:0]
wire [63:0] afi0_wdata; // output[63:0]
wire afi0_wvalid; // output
wire afi0_wready; // input
wire [ 5:0] afi0_wid; // output[5:0]
wire afi0_wlast; // output
wire [ 7:0] afi0_wstrb; // output[7:0]
wire afi0_bvalid; // input
wire afi0_bready; // output
wire [ 5:0] afi0_bid; // input[5:0]
wire [ 1:0] afi0_bresp; // input[1:0]
wire [ 7:0] afi0_wcount; // input[7:0]
wire [ 5:0] afi0_wacount; // input[5:0]
wire afi0_wrissuecap1en; // output
wire [31:0] afi0_araddr; // output[31:0]
wire afi0_arvalid; // output
wire afi0_arready; // input
wire [ 5:0] afi0_arid; // output[5:0]
wire [ 1:0] afi0_arlock; // output[1:0]
wire [ 3:0] afi0_arcache; // output[3:0]
wire [ 2:0] afi0_arprot; // output[2:0]
wire [ 3:0] afi0_arlen; // output[3:0]
wire [ 1:0] afi0_arsize; // output[2:0]
wire [ 1:0] afi0_arburst; // output[1:0]
wire [ 3:0] afi0_arqos; // output[3:0]
wire [63:0] afi0_rdata; // input[63:0]
wire afi0_rvalid; // input
wire afi0_rready; // output
wire [ 5:0] afi0_rid; // input[5:0]
wire afi0_rlast; // input
wire [ 1:0] afi0_rresp; // input[2:0]
wire [ 7:0] afi0_rcount; // input[7:0]
wire [ 2:0] afi0_racount; // input[2:0]
wire afi0_rdissuecap1en; // output
wire [31:0] afi3_awaddr; // output[31:0]
wire afi3_awvalid; // output
wire afi3_awready; // input
wire [ 5:0] afi3_awid; // output[5:0]
wire [ 1:0] afi3_awlock; // output[1:0]
wire [ 3:0] afi3_awcache; // output[3:0]
wire [ 2:0] afi3_awprot; // output[2:0]
wire [ 3:0] afi3_awlen; // output[3:0]
wire [ 1:0] afi3_awsize; // output[2:0]
wire [ 1:0] afi3_awburst; // output[1:0]
wire [ 3:0] afi3_awqos; // output[3:0]
wire [63:0] afi3_wdata; // output[63:0]
wire afi3_wvalid; // output
wire afi3_wready; // input
wire [ 5:0] afi3_wid; // output[5:0]
wire afi3_wlast; // output
wire [ 7:0] afi3_wstrb; // output[7:0]
wire afi3_bvalid; // input
wire afi3_bready; // output
wire [ 5:0] afi3_bid; // input[5:0]
wire [ 1:0] afi3_bresp; // input[1:0]
wire [ 7:0] afi3_wcount; // input[7:0]
wire [ 5:0] afi3_wacount; // input[5:0]
wire afi3_wrissuecap1en; // output
wire [31:0] afi3_araddr; // output[31:0]
wire afi3_arvalid; // output
wire afi3_arready; // input
wire [ 5:0] afi3_arid; // output[5:0]
wire [ 1:0] afi3_arlock; // output[1:0]
wire [ 3:0] afi3_arcache; // output[3:0]
wire [ 2:0] afi3_arprot; // output[2:0]
wire [ 3:0] afi3_arlen; // output[3:0]
wire [ 1:0] afi3_arsize; // output[2:0]
wire [ 1:0] afi3_arburst; // output[1:0]
wire [ 3:0] afi3_arqos; // output[3:0]
wire [63:0] afi3_rdata; // input[63:0]
wire afi3_rvalid; // input
wire afi3_rready; // output
wire [ 5:0] afi3_rid; // input[5:0]
wire afi3_rlast; // input
wire [ 1:0] afi3_rresp; // input[2:0]
wire [ 7:0] afi3_rcount; // input[7:0]
wire [ 2:0] afi3_racount; // input[2:0]
wire afi3_rdissuecap1en; // output
assign comb_rst=~frst[0] | frst[1];
always @(posedge comb_rst or posedge axi_aclk0) begin
......@@ -159,95 +159,95 @@ sata_top sata_top(
.ACLK (axi_aclk0),
.ARESETN (axi_rst/* | sata_rst*/),
// AXI PS Master GP1: Read Address
.ARADDR (ARADDR),
.ARVALID (ARVALID),
.ARREADY (ARREADY),
.ARID (ARID),
.ARLEN (ARLEN),
.ARSIZE (ARSIZE),
.ARBURST (ARBURST),
.ARADDR (maxi1_araddr),
.ARVALID (maxi1_arvalid),
.ARREADY (maxi1_arready),
.ARID (maxi1_arid),
.ARLEN (maxi1_arlen),
.ARSIZE (maxi1_arsize),
.ARBURST (maxi1_arburst),
// AXI PS Master GP1: Read Data
.RDATA (RDATA),
.RVALID (RVALID),
.RREADY (RREADY),
.RID (RID),
.RLAST (RLAST),
.RRESP (RRESP),
.RDATA (maxi1_rdata),
.RVALID (maxi1_rvalid),
.RREADY (maxi1_rready),
.RID (maxi1_rid),
.RLAST (maxi1_rlast),
.RRESP (maxi1_rresp),
// AXI PS Master GP1: Write Address
.AWADDR (AWADDR),
.AWVALID (AWVALID),
.AWREADY (AWREADY),
.AWID (AWID),
.AWLEN (AWLEN),
.AWSIZE (AWSIZE),
.AWBURST (AWBURST),
.AWADDR (maxi1_awaddr),
.AWVALID (maxi1_awvalid),
.AWREADY (maxi1_awready),
.AWID (maxi1_awid),
.AWLEN (maxi1_awlen),
.AWSIZE (maxi1_awsize),
.AWBURST (maxi1_awburst),
// AXI PS Master GP1: Write Data
.WDATA (WDATA),
.WVALID (WVALID),
.WREADY (WREADY),
.WID (WID),
.WLAST (WLAST),
.WSTRB (WSTRB),
.WDATA (maxi1_wdata),
.WVALID (maxi1_wvalid),
.WREADY (maxi1_wready),
.WID (maxi1_wid),
.WLAST (maxi1_wlast),
.WSTRB (maxi1_wstb),
// AXI PS Master GP1: Write Responce
.BVALID (BVALID),
.BREADY (BREADY),
.BID (BID),
.BRESP (BRESP),
.BVALID (maxi1_bvalid),
.BREADY (maxi1_bready),
.BID (maxi1_bid),
.BRESP (maxi1_bresp),
/*
* Data interface
*/
.afi_awaddr (afi0_awaddr),
.afi_awvalid (afi0_awvalid),
.afi_awready (afi0_awready),
.afi_awid (afi0_awid),
.afi_awlock (afi0_awlock),
.afi_awcache (afi0_awcache),
.afi_awprot (afi0_awprot),
.afi_awlen (afi0_awlen),
.afi_awsize (afi0_awsize),
.afi_awburst (afi0_awburst),
.afi_awqos (afi0_awqos),
.afi_awaddr (afi3_awaddr),
.afi_awvalid (afi3_awvalid),
.afi_awready (afi3_awready),
.afi_awid (afi3_awid),
.afi_awlock (afi3_awlock),
.afi_awcache (afi3_awcache),
.afi_awprot (afi3_awprot),
.afi_awlen (afi3_awlen),
.afi_awsize (afi3_awsize),
.afi_awburst (afi3_awburst),
.afi_awqos (afi3_awqos),
// write data
.afi_wdata (afi0_wdata),
.afi_wvalid (afi0_wvalid),
.afi_wready (afi0_wready),
.afi_wid (afi0_wid),
.afi_wlast (afi0_wlast),
.afi_wstrb (afi0_wstrb),
.afi_wdata (afi3_wdata),
.afi_wvalid (afi3_wvalid),
.afi_wready (afi3_wready),
.afi_wid (afi3_wid),
.afi_wlast (afi3_wlast),
.afi_wstrb (afi3_wstrb),
// write response
.afi_bvalid (afi0_bvalid),
.afi_bready (afi0_bready),
.afi_bid (afi0_bid),
.afi_bresp (afi0_bresp),
.afi_bvalid (afi3_bvalid),
.afi_bready (afi3_bready),
.afi_bid (afi3_bid),
.afi_bresp (afi3_bresp),
// PL extra (non-AXI) signal
.afi_wcount (afi0_wcount),
.afi_wacount (afi0_wacount),
.afi_wrissuecap1en (afi0_wrissuecap1en),
.afi_wcount (afi3_wcount),
.afi_wacount (afi3_wacount),
.afi_wrissuecap1en (afi3_wrissuecap1en),
// AXI_HP signals - read channel
// read address
.afi_araddr (afi0_araddr),
.afi_arvalid (afi0_arvalid),
.afi_arready (afi0_arready),
.afi_arid (afi0_arid),
.afi_arlock (afi0_arlock),
.afi_arcache (afi0_arcache),
.afi_arprot (afi0_arprot),
.afi_arlen (afi0_arlen),
.afi_arsize (afi0_arsize),
.afi_arburst (afi0_arburst),
.afi_arqos (afi0_arqos),
.afi_araddr (afi3_araddr),
.afi_arvalid (afi3_arvalid),
.afi_arready (afi3_arready),
.afi_arid (afi3_arid),
.afi_arlock (afi3_arlock),
.afi_arcache (afi3_arcache),
.afi_arprot (afi3_arprot),
.afi_arlen (afi3_arlen),
.afi_arsize (afi3_arsize),
.afi_arburst (afi3_arburst),
.afi_arqos (afi3_arqos),
// read data
.afi_rdata (afi0_rdata),
.afi_rvalid (afi0_rvalid),
.afi_rready (afi0_rready),
.afi_rid (afi0_rid),
.afi_rlast (afi0_rlast),
.afi_rresp (afi0_rresp),
.afi_rdata (afi3_rdata),
.afi_rvalid (afi3_rvalid),
.afi_rready (afi3_rready),
.afi_rid (afi3_rid),
.afi_rlast (afi3_rlast),
.afi_rresp (afi3_rresp),
// PL extra (non-AXI) signal
.afi_rcount (afi0_rcount),
.afi_racount (afi0_racount),
.afi_rdissuecap1en (afi0_rdissuecap1en),
.afi_rcount (afi3_rcount),
.afi_racount (afi3_racount),
.afi_rdissuecap1en (afi3_rdissuecap1en),
/*
* PHY
......@@ -575,48 +575,48 @@ PS7 ps7_i (
.MAXIGP1ACLK (axi_aclk0), // AXI PS Master GP1 Clock , input
.MAXIGP1ARESETN (), // AXI PS Master GP1 Reset, output
// AXI PS Master GP1: Read Address
.MAXIGP1ARADDR (ARADDR), // AXI PS Master GP1 ARADDR[31:0], output
.MAXIGP1ARVALID (ARVALID), // AXI PS Master GP1 ARVALID, output
.MAXIGP1ARREADY (ARREADY), // AXI PS Master GP1 ARREADY, input
.MAXIGP1ARID (ARID), // AXI PS Master GP1 ARID[11:0], output
.MAXIGP1ARADDR (maxi1_araddr), // AXI PS Master GP1 ARADDR[31:0], output
.MAXIGP1ARVALID (maxi1_arvalid), // AXI PS Master GP1 ARVALID, output
.MAXIGP1ARREADY (maxi1_arready), // AXI PS Master GP1 ARREADY, input
.MAXIGP1ARID (maxi1_arid), // AXI PS Master GP1 ARID[11:0], output
.MAXIGP1ARLOCK (), // AXI PS Master GP1 ARLOCK[1:0], output
.MAXIGP1ARCACHE (), // AXI PS Master GP1 ARCACHE[3:0], output
.MAXIGP1ARPROT (), // AXI PS Master GP1 ARPROT[2:0], output
.MAXIGP1ARLEN (ARLEN), // AXI PS Master GP1 ARLEN[3:0], output
.MAXIGP1ARSIZE (ARSIZE), // AXI PS Master GP1 ARSIZE[1:0], output
.MAXIGP1ARBURST (ARBURST), // AXI PS Master GP1 ARBURST[1:0], output
.MAXIGP1ARLEN (maxi1_arlen), // AXI PS Master GP1 ARLEN[3:0], output
.MAXIGP1ARSIZE (maxi1_arsize), // AXI PS Master GP1 ARSIZE[1:0], output
.MAXIGP1ARBURST (maxi1_arburst), // AXI PS Master GP1 ARBURST[1:0], output
.MAXIGP1ARQOS (), // AXI PS Master GP1 ARQOS[3:0], output
// AXI PS Master GP1: Read Data
.MAXIGP1RDATA (RDATA), // AXI PS Master GP1 RDATA[31:0], input
.MAXIGP1RVALID (RVALID), // AXI PS Master GP1 RVALID, input
.MAXIGP1RREADY (RREADY), // AXI PS Master GP1 RREADY, output
.MAXIGP1RID (RID), // AXI PS Master GP1 RID[11:0], input
.MAXIGP1RLAST (RLAST), // AXI PS Master GP1 RLAST, input
.MAXIGP1RRESP (RRESP), // AXI PS Master GP1 RRESP[1:0], input
.MAXIGP1RDATA (maxi1_rdata), // AXI PS Master GP1 RDATA[31:0], input
.MAXIGP1RVALID (maxi1_rvalid), // AXI PS Master GP1 RVALID, input
.MAXIGP1RREADY (maxi1_rready), // AXI PS Master GP1 RREADY, output
.MAXIGP1RID (maxi1_rid), // AXI PS Master GP1 RID[11:0], input
.MAXIGP1RLAST (maxi1_rlast), // AXI PS Master GP1 RLAST, input
.MAXIGP1RRESP (maxi1_rresp), // AXI PS Master GP1 RRESP[1:0], input
// AXI PS Master GP1: Write Address
.MAXIGP1AWADDR (AWADDR), // AXI PS Master GP1 AWADDR[31:0], output
.MAXIGP1AWVALID (AWVALID), // AXI PS Master GP1 AWVALID, output
.MAXIGP1AWREADY (AWREADY), // AXI PS Master GP1 AWREADY, input
.MAXIGP1AWID (AWID), // AXI PS Master GP1 AWID[11:0], output
.MAXIGP1AWADDR (maxi1_awaddr), // AXI PS Master GP1 AWADDR[31:0], output
.MAXIGP1AWVALID (maxi1_awvalid), // AXI PS Master GP1 AWVALID, output
.MAXIGP1AWREADY (maxi1_awready), // AXI PS Master GP1 AWREADY, input
.MAXIGP1AWID (maxi1_awid), // AXI PS Master GP1 AWID[11:0], output
.MAXIGP1AWLOCK (), // AXI PS Master GP1 AWLOCK[1:0], output
.MAXIGP1AWCACHE (), // AXI PS Master GP1 AWCACHE[3:0], output
.MAXIGP1AWPROT (), // AXI PS Master GP1 AWPROT[2:0], output
.MAXIGP1AWLEN (AWLEN), // AXI PS Master GP1 AWLEN[3:0], output
.MAXIGP1AWSIZE (AWSIZE), // AXI PS Master GP1 AWSIZE[1:0], output
.MAXIGP1AWBURST (AWBURST), // AXI PS Master GP1 AWBURST[1:0], output
.MAXIGP1AWLEN (maxi1_awlen), // AXI PS Master GP1 AWLEN[3:0], output
.MAXIGP1AWSIZE (maxi1_awsize), // AXI PS Master GP1 AWSIZE[1:0], output
.MAXIGP1AWBURST (maxi1_awburst), // AXI PS Master GP1 AWBURST[1:0], output
.MAXIGP1AWQOS (), // AXI PS Master GP1 AWQOS[3:0], output
// AXI PS Master GP1: Write Data
.MAXIGP1WDATA (WDATA), // AXI PS Master GP1 WDATA[31:0], output
.MAXIGP1WVALID (WVALID), // AXI PS Master GP1 WVALID, output
.MAXIGP1WREADY (WREADY), // AXI PS Master GP1 WREADY, input
.MAXIGP1WID (WID), // AXI PS Master GP1 WID[11:0], output
.MAXIGP1WLAST (WLAST), // AXI PS Master GP1 WLAST, output
.MAXIGP1WSTRB (WSTRB), // AXI PS Master GP1 WSTRB[3:0], output
.MAXIGP1WDATA (maxi1_wdata), // AXI PS Master GP1 WDATA[31:0], output
.MAXIGP1WVALID (maxi1_wvalid), // AXI PS Master GP1 WVALID, output
.MAXIGP1WREADY (maxi1_wready), // AXI PS Master GP1 WREADY, input
.MAXIGP1WID (maxi1_wid), // AXI PS Master GP1 WID[11:0], output
.MAXIGP1WLAST (maxi1_wlast), // AXI PS Master GP1 WLAST, output
.MAXIGP1WSTRB (maxi1_wstb), // AXI PS Master GP1 maxi1_wstb[3:0], output
// AXI PS Master GP1: Write Responce
.MAXIGP1BVALID (BVALID), // AXI PS Master GP1 BVALID, input
.MAXIGP1BREADY (BREADY), // AXI PS Master GP1 BREADY, output
.MAXIGP1BID (BID), // AXI PS Master GP1 BID[11:0], input
.MAXIGP1BRESP (BRESP), // AXI PS Master GP1 BRESP[1:0], input
.MAXIGP1BVALID (maxi1_bvalid), // AXI PS Master GP1 BVALID, input
.MAXIGP1BREADY (maxi1_bready), // AXI PS Master GP1 BREADY, output
.MAXIGP1BID (maxi1_bid), // AXI PS Master GP1 BID[11:0], input
.MAXIGP1BRESP (maxi1_bresp), // AXI PS Master GP1 BRESP[1:0], input
// AXI PS Slave GP0
// AXI PS Slave GP0: Clock, Reset
......@@ -881,54 +881,54 @@ PS7 ps7_i (
.SAXIHP3ACLK (hclk), // AXI PS Slave HP3 Clock , input
.SAXIHP3ARESETN(), // AXI PS Slave HP3 Reset, output
// AXI PS Slave HP3: Read Address
.SAXIHP3ARADDR (afi0_araddr), // AXI PS Slave HP3 ARADDR[31:0], input
.SAXIHP3ARVALID (afi0_arvalid), // AXI PS Slave HP3 ARVALID, input
.SAXIHP3ARREADY (afi0_arready), // AXI PS Slave HP3 ARREADY, output
.SAXIHP3ARID (afi0_arid), // AXI PS Slave HP3 ARID[5:0], input
.SAXIHP3ARLOCK (afi0_arlock), // AXI PS Slave HP3 ARLOCK[1:0], input
.SAXIHP3ARCACHE (afi0_arcache), // AXI PS Slave HP3 ARCACHE[3:0], input
.SAXIHP3ARPROT (afi0_arprot), // AXI PS Slave HP3 ARPROT[2:0], input
.SAXIHP3ARLEN (afi0_arlen), // AXI PS Slave HP3 ARLEN[3:0], input
.SAXIHP3ARSIZE (afi0_arsize), // AXI PS Slave HP3 ARSIZE[2:0], input
.SAXIHP3ARBURST (afi0_arburst), // AXI PS Slave HP3 ARBURST[1:0], input
.SAXIHP3ARQOS (afi0_arqos), // AXI PS Slave HP3 ARQOS[3:0], input
.SAXIHP3ARADDR (afi3_araddr), // AXI PS Slave HP3 ARADDR[31:0], input
.SAXIHP3ARVALID (afi3_arvalid), // AXI PS Slave HP3 ARVALID, input
.SAXIHP3ARREADY (afi3_arready), // AXI PS Slave HP3 ARREADY, output
.SAXIHP3ARID (afi3_arid), // AXI PS Slave HP3 ARID[5:0], input
.SAXIHP3ARLOCK (afi3_arlock), // AXI PS Slave HP3 ARLOCK[1:0], input
.SAXIHP3ARCACHE (afi3_arcache), // AXI PS Slave HP3 ARCACHE[3:0], input
.SAXIHP3ARPROT (afi3_arprot), // AXI PS Slave HP3 ARPROT[2:0], input
.SAXIHP3ARLEN (afi3_arlen), // AXI PS Slave HP3 ARLEN[3:0], input
.SAXIHP3ARSIZE (afi3_arsize), // AXI PS Slave HP3 ARSIZE[2:0], input
.SAXIHP3ARBURST (afi3_arburst), // AXI PS Slave HP3 ARBURST[1:0], input
.SAXIHP3ARQOS (afi3_arqos), // AXI PS Slave HP3 ARQOS[3:0], input
// AXI PS Slave HP3: Read Data
.SAXIHP3RDATA (afi0_rdata), // AXI PS Slave HP3 RDATA[63:0], output
.SAXIHP3RVALID (afi0_rvalid), // AXI PS Slave HP3 RVALID, output
.SAXIHP3RREADY (afi0_rready), // AXI PS Slave HP3 RREADY, input
.SAXIHP3RID (afi0_rid), // AXI PS Slave HP3 RID[5:0], output
.SAXIHP3RLAST (afi0_rlast), // AXI PS Slave HP3 RLAST, output
.SAXIHP3RRESP (afi0_rresp), // AXI PS Slave HP3 RRESP[1:0], output
.SAXIHP3RCOUNT (afi0_rcount), // AXI PS Slave HP3 RCOUNT[7:0], output
.SAXIHP3RACOUNT (afi0_racount), // AXI PS Slave HP3 RACOUNT[2:0], output
.SAXIHP3RDISSUECAP1EN (afi0_rdissuecap1en), // AXI PS Slave HP3 RDISSUECAP1EN, input
.SAXIHP3RDATA (afi3_rdata), // AXI PS Slave HP3 RDATA[63:0], output
.SAXIHP3RVALID (afi3_rvalid), // AXI PS Slave HP3 RVALID, output
.SAXIHP3RREADY (afi3_rready), // AXI PS Slave HP3 RREADY, input
.SAXIHP3RID (afi3_rid), // AXI PS Slave HP3 RID[5:0], output
.SAXIHP3RLAST (afi3_rlast), // AXI PS Slave HP3 RLAST, output
.SAXIHP3RRESP (afi3_rresp), // AXI PS Slave HP3 RRESP[1:0], output
.SAXIHP3RCOUNT (afi3_rcount), // AXI PS Slave HP3 RCOUNT[7:0], output
.SAXIHP3RACOUNT (afi3_racount), // AXI PS Slave HP3 RACOUNT[2:0], output
.SAXIHP3RDISSUECAP1EN (afi3_rdissuecap1en), // AXI PS Slave HP3 RDISSUECAP1EN, input
// AXI PS Slave HP3: Write Address
.SAXIHP3AWADDR (afi0_awaddr), // AXI PS Slave HP3 AWADDR[31:0], input
.SAXIHP3AWVALID (afi0_awvalid), // AXI PS Slave HP3 AWVALID, input
.SAXIHP3AWREADY (afi0_awready), // AXI PS Slave HP3 AWREADY, output
.SAXIHP3AWID (afi0_awid), // AXI PS Slave HP3 AWID[5:0], input
.SAXIHP3AWLOCK (afi0_awlock), // AXI PS Slave HP3 AWLOCK[1:0], input
.SAXIHP3AWCACHE (afi0_awcache), // AXI PS Slave HP3 AWCACHE[3:0], input
.SAXIHP3AWPROT (afi0_awprot), // AXI PS Slave HP3 AWPROT[2:0], input
.SAXIHP3AWLEN (afi0_awlen), // AXI PS Slave HP3 AWLEN[3:0], input
.SAXIHP3AWSIZE (afi0_awsize), // AXI PS Slave HP3 AWSIZE[1:0], input
.SAXIHP3AWBURST (afi0_awburst), // AXI PS Slave HP3 AWBURST[1:0], input
.SAXIHP3AWQOS (afi0_awqos), // AXI PS Slave HP3 AWQOS[3:0], input
.SAXIHP3AWADDR (afi3_awaddr), // AXI PS Slave HP3 AWADDR[31:0], input
.SAXIHP3AWVALID (afi3_awvalid), // AXI PS Slave HP3 AWVALID, input
.SAXIHP3AWREADY (afi3_awready), // AXI PS Slave HP3 AWREADY, output
.SAXIHP3AWID (afi3_awid), // AXI PS Slave HP3 AWID[5:0], input
.SAXIHP3AWLOCK (afi3_awlock), // AXI PS Slave HP3 AWLOCK[1:0], input
.SAXIHP3AWCACHE (afi3_awcache), // AXI PS Slave HP3 AWCACHE[3:0], input
.SAXIHP3AWPROT (afi3_awprot), // AXI PS Slave HP3 AWPROT[2:0], input
.SAXIHP3AWLEN (afi3_awlen), // AXI PS Slave HP3 AWLEN[3:0], input
.SAXIHP3AWSIZE (afi3_awsize), // AXI PS Slave HP3 AWSIZE[1:0], input
.SAXIHP3AWBURST (afi3_awburst), // AXI PS Slave HP3 AWBURST[1:0], input
.SAXIHP3AWQOS (afi3_awqos), // AXI PS Slave HP3 AWQOS[3:0], input
// AXI PS Slave HP3: Write Data
.SAXIHP3WDATA (afi0_wdata), // AXI PS Slave HP3 WDATA[63:0], input
.SAXIHP3WVALID (afi0_wvalid), // AXI PS Slave HP3 WVALID, input
.SAXIHP3WREADY (afi0_wready), // AXI PS Slave HP3 WREADY, output
.SAXIHP3WID (afi0_wid), // AXI PS Slave HP3 WID[5:0], input
.SAXIHP3WLAST (afi0_wlast), // AXI PS Slave HP3 WLAST, input
.SAXIHP3WSTRB (afi0_wstrb), // AXI PS Slave HP3 WSTRB[7:0], input
.SAXIHP3WCOUNT (afi0_wcount), // AXI PS Slave HP3 WCOUNT[7:0], output
.SAXIHP3WACOUNT (afi0_wacount), // AXI PS Slave HP3 WACOUNT[5:0], output
.SAXIHP3WRISSUECAP1EN (afi0_wrissuecap1en), // AXI PS Slave HP3 WRISSUECAP1EN, input
.SAXIHP3WDATA (afi3_wdata), // AXI PS Slave HP3 WDATA[63:0], input
.SAXIHP3WVALID (afi3_wvalid), // AXI PS Slave HP3 WVALID, input
.SAXIHP3WREADY (afi3_wready), // AXI PS Slave HP3 WREADY, output
.SAXIHP3WID (afi3_wid), // AXI PS Slave HP3 WID[5:0], input
.SAXIHP3WLAST (afi3_wlast), // AXI PS Slave HP3 WLAST, input
.SAXIHP3WSTRB (afi3_wstrb), // AXI PS Slave HP3 WSTRB[7:0], input
.SAXIHP3WCOUNT (afi3_wcount), // AXI PS Slave HP3 WCOUNT[7:0], output
.SAXIHP3WACOUNT (afi3_wacount), // AXI PS Slave HP3 WACOUNT[5:0], output
.SAXIHP3WRISSUECAP1EN (afi3_wrissuecap1en), // AXI PS Slave HP3 WRISSUECAP1EN, input
// AXI PS Slave HP3: Write Responce
.SAXIHP3BVALID (afi0_bvalid), // AXI PS Slave HP3 BVALID, output
.SAXIHP3BREADY (afi0_bready), // AXI PS Slave HP3 BREADY, input
.SAXIHP3BID (afi0_bid), // AXI PS Slave HP3 BID[5:0], output
.SAXIHP3BRESP (afi0_bresp), // AXI PS Slave HP3 BRESP[1:0], output
.SAXIHP3BVALID (afi3_bvalid), // AXI PS Slave HP3 BVALID, output
.SAXIHP3BREADY (afi3_bready), // AXI PS Slave HP3 BREADY, input
.SAXIHP3BID (afi3_bid), // AXI PS Slave HP3 BID[5:0], output
.SAXIHP3BRESP (afi3_bresp), // AXI PS Slave HP3 BRESP[1:0], output
// AXI PS Slave ACP
// AXI PS Slave ACP: Clock, Reset
......
host/gtx_wrap.v
View file @ 90a85abd
......@@ -129,7 +129,61 @@ generate
if (DATA_BYTE_WIDTH == 4) begin
// resync to txusrclk
// 2*Fin = Fout => WIDTHin = 2*WIDTHout
wire txdata_resync_nempty;
// Andrey:
reg txdata_resync_strobe;
reg [15:0] txdata_enc_in_r;
reg [ 1:0] txcharisk_enc_in_r;
wire [38:0] txdata_resync_out;
wire txdata_resync_valid;
reg txcomwake_gtx_f;
reg txcominit_gtx_f;
reg txelecidle_gtx_f;
resync_data #( // TODO: update output register.. OK as it is
.DATA_WIDTH(39),
.DATA_DEPTH(3),
.INITIAL_VALUE(39'h4000000000) // All 0 but txelecidle_gtx
) txdata_resynchro (
.arst (txreset), // input
.srst (~wrap_txreset_), // input
.wclk (txusrclk2), // input
.rclk (txusrclk), // input
.we (1'b1), // input
.re (txdata_resync_strobe), // input
.data_in ({txelecidle, txcominit, txcomwake, txcharisk, txdata}), // input[15:0]
.data_out (txdata_resync_out), // output[15:0] reg
.valid (txdata_resync_valid) // output reg
);
always @ (posedge txreset or posedge txusrclk) begin
if (txreset) txdata_resync_strobe <= 0;
else if (txdata_resync_valid) txdata_resync_strobe <= ~txdata_resync_strobe[0];
if (txreset) begin
txdata_enc_in_r <= 0;
txcharisk_enc_in_r <= 0;
end else if (txdata_resync_valid) begin
txdata_enc_in_r <= txdata_resync_strobe? txdata_resync_out[31:16]: txdata_resync_out[15:0];
txcharisk_enc_in_r <= txdata_resync_strobe? txdata_resync_out[35:34]: txdata_resync_out[33:32];
end
if (txreset) begin
txcomwake_gtx_f <= 0;
txcominit_gtx_f <= 0;
txelecidle_gtx_f <= 0;
end else begin
txcomwake_gtx_f <= txdata_resync_out[36];
txcominit_gtx_f <= txdata_resync_out[37];
txelecidle_gtx_f <= txdata_resync_out[38];
end
end
assign txdata_enc_in = txdata_enc_in_r;
assign txcharisk_enc_in = txcharisk_enc_in_r;
assign txcominit_gtx = txcominit_gtx_f;
assign txcomwake_gtx = txcomwake_gtx_f;
assign txelecidle_gtx = txelecidle_gtx_f;
/*wire txdata_resync_nempty;
reg txdata_resync_nempty_r;
reg txdata_resync_nempty_rr;
reg txdata_resync_strobe;
......@@ -138,13 +192,14 @@ if (DATA_BYTE_WIDTH == 4) begin
assign txdata_enc_in = {16{~txdata_resync_strobe}} & txdata_resync[15:0] | {16{txdata_resync_strobe}} & txdata_resync[31:16];
assign txcharisk_enc_in = {2{~txdata_resync_strobe}} & txdata_resync[33:32] | {2{txdata_resync_strobe}} & txdata_resync[35:34];
// Andrey: wrap_txreset_ has different clock domain
always @ (posedge txusrclk)
begin
txdata_resync <= ~wrap_txreset_ ? 36'h0 : txdata_resync_nempty & txdata_resync_strobe ? txdata_resync_out[35:0] : txdata_resync;
txdata_resync_strobe <= ~wrap_txreset_ ? 1'b0 : ~txdata_resync_nempty ? txdata_resync_strobe : ~txdata_resync_strobe; // -> 1 once every resynced dword = signal to latch it
txdata_resync <= ~wrap_txreset_ ? 36'h0 : ((txdata_resync_nempty & txdata_resync_strobe) ? txdata_resync_out[35:0] : txdata_resync);
txdata_resync_strobe <= ~wrap_txreset_ ? 1'b0 : ((~txdata_resync_nempty) ? txdata_resync_strobe : ~txdata_resync_strobe); // -> 1 once every resynced dword = signal to latch it
end
// nempty_rr & nempty => shall be at least 2 elements in fifo - safe to read
// nempty_rr & nempty => shall be at least 2 elements in fifo
always @ (posedge txusrclk2)
begin
txdata_resync_nempty_r <= txdata_resync_nempty;
......@@ -182,7 +237,9 @@ if (DATA_BYTE_WIDTH == 4) begin
assign txcomwake_gtx = txcomwake_gtx_f;
assign txcominit_gtx = txcominit_gtx_f;
assign txelecidle_gtx = txelecidle_gtx_f;
*/
end
else
if (DATA_BYTE_WIDTH == 2) begin
// no resync is needed => straightforward assignments
......
host/sata_phy.v
View file @ 90a85abd
......@@ -27,7 +27,7 @@ module sata_phy #(
// initial reset, resets PLL. After pll is locked, an internal sata reset is generated.
input wire extrst,
// sata clk, generated in pll as usrclk2
output wire clk, // 75KHz, bufg
output wire clk, // 75MHz, bufg
output wire rst,
// reliable clock to source drp and cpll lock det circuits
......
tb_top.sav
View file @ 90a85abd
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Wed Sep 9 00:34:20 2015
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Tue Dec 22 20:43:14 2015
[*]
[dumpfile] "/home/alexey/tmp/sata2/simulation/tb_top-20150908183150922.lxt"
[dumpfile_mtime] "Wed Sep 9 00:32:03 2015"
[dumpfile_size] 22508590
[savefile] "/home/alexey/tmp/sata2/tb_top.sav"
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_top-20151221162333769.fst"
[dumpfile_mtime] "Mon Dec 21 23:23:59 2015"
[dumpfile_size] 2362859
[savefile] "/home/andrey/git/x393_sata/tb_top.sav"
[timestart] 0
[size] 1920 1145
[pos] -919 -4
*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[size] 1823 1180
[pos] 1919 -581
*-22.223623 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb.
[treeopen] tb.dut.
[treeopen] tb.dut.sata_top.
[treeopen] tb.dut.sata_top.sata_host.
[sst_width] 202
[sst_width] 403
[signals_width] 214
[sst_expanded] 1
[sst_vpaned_height] 352
[sst_vpaned_height] 790
@c00200
-host link layer
@28
tb.dut.sata_top.sata_host.link.alignes_pair[0]
tb.dut.sata_top.sata_host.link.alignes_pair_0[0]
tb.dut.sata_top.sata_host.link.alignes_pair_1[0]
@22
tb.dut.sata_top.sata_host.link.alignes_timer[8:0]
@28
tb.dut.sata_top.sata_host.link.clk[0]
tb.dut.sata_top.sata_host.link.clr_align[0]
tb.dut.sata_top.sata_host.link.clr_nocomm[0]
tb.dut.sata_top.sata_host.link.clr_nocommerr[0]
tb.dut.sata_top.sata_host.link.clr_rcvr_badend[0]
tb.dut.sata_top.sata_host.link.clr_rcvr_data[0]
tb.dut.sata_top.sata_host.link.clr_rcvr_eof[0]
tb.dut.sata_top.sata_host.link.clr_rcvr_goodcrc[0]
tb.dut.sata_top.sata_host.link.clr_rcvr_goodend[0]
tb.dut.sata_top.sata_host.link.clr_rcvr_rdy[0]
tb.dut.sata_top.sata_host.link.clr_rcvr_rhold[0]
tb.dut.sata_top.sata_host.link.clr_rcvr_shold[0]
tb.dut.sata_top.sata_host.link.clr_rcvr_wait[0]
tb.dut.sata_top.sata_host.link.clr_reset[0]
tb.dut.sata_top.sata_host.link.clr_send_crc[0]
tb.dut.sata_top.sata_host.link.clr_send_data[0]
tb.dut.sata_top.sata_host.link.clr_send_eof[0]
tb.dut.sata_top.sata_host.link.clr_send_rdy[0]
tb.dut.sata_top.sata_host.link.clr_send_rhold[0]
tb.dut.sata_top.sata_host.link.clr_send_shold[0]
tb.dut.sata_top.sata_host.link.clr_send_sof[0]
tb.dut.sata_top.sata_host.link.clr_sync_esc[0]
tb.dut.sata_top.sata_host.link.clr_wait[0]
tb.dut.sata_top.sata_host.link.crc_bad[0]
@22
tb.dut.sata_top.sata_host.link.crc_dword[31:0]
@28
tb.dut.sata_top.sata_host.link.crc_good[0]
tb.dut.sata_top.sata_host.link.data_busy_in[0]
@22
tb.dut.sata_top.sata_host.link.data_in[31:0]
@28
tb.dut.sata_top.sata_host.link.data_last_in[0]
tb.dut.sata_top.sata_host.link.data_last_out[0]
tb.dut.sata_top.sata_host.link.data_mask_in[1:0]
tb.dut.sata_top.sata_host.link.data_mask_out[1:0]
@22
tb.dut.sata_top.sata_host.link.data_out[31:0]
tb.dut.sata_top.sata_host.link.data_out_r[31:0]
tb.dut.sata_top.sata_host.link.data_out_rr[31:0]
@28
tb.dut.sata_top.sata_host.link.data_strobe_out[0]
tb.dut.sata_top.sata_host.link.data_txing[0]
tb.dut.sata_top.sata_host.link.data_val_in[0]
tb.dut.sata_top.sata_host.link.data_val_out[0]
tb.dut.sata_top.sata_host.link.data_val_out_r[0]
tb.dut.sata_top.sata_host.link.data_val_out_rr[0]
tb.dut.sata_top.sata_host.link.dec_err[0]
tb.dut.sata_top.sata_host.link.dword_val[0]
tb.dut.sata_top.sata_host.link.frame_ack[0]
tb.dut.sata_top.sata_host.link.frame_busy[0]
tb.dut.sata_top.sata_host.link.frame_done[0]
tb.dut.sata_top.sata_host.link.frame_done_bad[0]
tb.dut.sata_top.sata_host.link.frame_done_good[0]
tb.dut.sata_top.sata_host.link.frame_rej[0]
tb.dut.sata_top.sata_host.link.frame_req[0]
tb.dut.sata_top.sata_host.link.got_escape[0]
tb.dut.sata_top.sata_host.link.inc_is_data[0]
tb.dut.sata_top.sata_host.link.incom_ack_bad[0]
tb.dut.sata_top.sata_host.link.incom_ack_good[0]
tb.dut.sata_top.sata_host.link.incom_done[0]
tb.dut.sata_top.sata_host.link.incom_invalidate[0]
tb.dut.sata_top.sata_host.link.incom_start[0]
tb.dut.sata_top.sata_host.link.incom_stop_f[0]
tb.dut.sata_top.sata_host.link.incom_stop_req[0]
tb.dut.sata_top.sata_host.link.link_reset[0]
@22
tb.dut.sata_top.sata_host.link.phy_data_in[31:0]
tb.dut.sata_top.sata_host.link.phy_data_out[31:0]
tb.dut.sata_top.sata_host.link.phy_err_in[3:0]
tb.dut.sata_top.sata_host.link.phy_isk_in[3:0]
tb.dut.sata_top.sata_host.link.phy_isk_out[3:0]
@28
tb.dut.sata_top.sata_host.link.phy_ready[0]
@22
tb.dut.sata_top.sata_host.link.rcvd_dword[14:0]
@28
tb.dut.sata_top.sata_host.link.rst[0]
@22
tb.dut.sata_top.sata_host.link.scrambler_out[31:0]
tb.dut.sata_top.sata_host.link.select_prim[14:0]
@28
tb.dut.sata_top.sata_host.link.set_align[0]
tb.dut.sata_top.sata_host.link.set_nocomm[0]
tb.dut.sata_top.sata_host.link.set_nocommerr[0]
tb.dut.sata_top.sata_host.link.set_rcvr_badend[0]
tb.dut.sata_top.sata_host.link.set_rcvr_data[0]
tb.dut.sata_top.sata_host.link.set_rcvr_eof[0]
tb.dut.sata_top.sata_host.link.set_rcvr_goodcrc[0]
tb.dut.sata_top.sata_host.link.set_rcvr_goodend[0]
tb.dut.sata_top.sata_host.link.set_rcvr_rdy[0]
tb.dut.sata_top.sata_host.link.set_rcvr_rhold[0]
tb.dut.sata_top.sata_host.link.set_rcvr_shold[0]
tb.dut.sata_top.sata_host.link.set_rcvr_wait[0]
tb.dut.sata_top.sata_host.link.set_reset[0]
tb.dut.sata_top.sata_host.link.set_send_crc[0]
tb.dut.sata_top.sata_host.link.set_send_data[0]
tb.dut.sata_top.sata_host.link.set_send_eof[0]
tb.dut.sata_top.sata_host.link.set_send_rdy[0]
tb.dut.sata_top.sata_host.link.set_send_rhold[0]
tb.dut.sata_top.sata_host.link.set_send_shold[0]
tb.dut.sata_top.sata_host.link.set_send_sof[0]
tb.dut.sata_top.sata_host.link.set_sync_esc[0]
tb.dut.sata_top.sata_host.link.set_wait[0]
@22
tb.dut.sata_top.sata_host.link.sim_states_concat[22:0]
@28
tb.dut.sata_top.sata_host.link.state_align[0]
tb.dut.sata_top.sata_host.link.state_idle[0]
tb.dut.sata_top.sata_host.link.state_nocomm[0]
tb.dut.sata_top.sata_host.link.state_nocommerr[0]
tb.dut.sata_top.sata_host.link.state_rcvr_badend[0]
tb.dut.sata_top.sata_host.link.state_rcvr_data[0]
tb.dut.sata_top.sata_host.link.state_rcvr_eof[0]
tb.dut.sata_top.sata_host.link.state_rcvr_goodcrc[0]
tb.dut.sata_top.sata_host.link.state_rcvr_goodend[0]
tb.dut.sata_top.sata_host.link.state_rcvr_rdy[0]
tb.dut.sata_top.sata_host.link.state_rcvr_rhold[0]
tb.dut.sata_top.sata_host.link.state_rcvr_shold[0]
tb.dut.sata_top.sata_host.link.state_rcvr_wait[0]
tb.dut.sata_top.sata_host.link.state_reset[0]
tb.dut.sata_top.sata_host.link.state_send_crc[0]
tb.dut.sata_top.sata_host.link.state_send_data[0]
tb.dut.sata_top.sata_host.link.state_send_eof[0]
tb.dut.sata_top.sata_host.link.state_send_rdy[0]
tb.dut.sata_top.sata_host.link.state_send_rhold[0]
tb.dut.sata_top.sata_host.link.state_send_shold[0]
tb.dut.sata_top.sata_host.link.state_send_sof[0]
tb.dut.sata_top.sata_host.link.state_sync_esc[0]
tb.dut.sata_top.sata_host.link.state_wait[0]
tb.dut.sata_top.sata_host.link.sync_escape_ack[0]
tb.dut.sata_top.sata_host.link.sync_escape_req[0]
@22
tb.dut.sata_top.sata_host.link.to_phy_data[31:0]
tb.dut.sata_top.sata_host.link.to_phy_isk[3:0]
@1401200
......@@ -169,92 +49,26 @@ tb.dut.sata_top.sata_host.link.to_phy_isk[3:0]
@22
tb.dut.sata_top.sata_host.command.al_cmd_in[31:0]
tb.dut.sata_top.sata_host.command.al_cmd_out[31:0]
@28
tb.dut.sata_top.sata_host.command.al_cmd_val_in[0]
tb.dut.sata_top.sata_host.command.al_sh_autoact_in[0]
tb.dut.sata_top.sata_host.command.al_sh_autoact_val_in[0]
@22
tb.dut.sata_top.sata_host.command.al_sh_buf_off_in[31:0]
@28
tb.dut.sata_top.sata_host.command.al_sh_buf_off_val_in[0]
@22
tb.dut.sata_top.sata_host.command.al_sh_command_in[7:0]
@28
tb.dut.sata_top.sata_host.command.al_sh_command_val_in[0]
@22
tb.dut.sata_top.sata_host.command.al_sh_control_in[7:0]
@28
tb.dut.sata_top.sata_host.command.al_sh_control_val_in[0]
@22
tb.dut.sata_top.sata_host.command.al_sh_count_in[15:0]
@28
tb.dut.sata_top.sata_host.command.al_sh_count_val_in[0]
@22
tb.dut.sata_top.sata_host.command.al_sh_data_in[31:0]
@28
tb.dut.sata_top.sata_host.command.al_sh_data_strobe_in[0]
tb.dut.sata_top.sata_host.command.al_sh_data_val_in[0]
@22
tb.dut.sata_top.sata_host.command.al_sh_dev_in[7:0]
@28
tb.dut.sata_top.sata_host.command.al_sh_dev_val_in[0]
tb.dut.sata_top.sata_host.command.al_sh_dir_in[0]
tb.dut.sata_top.sata_host.command.al_sh_dir_val_in[0]
@22
tb.dut.sata_top.sata_host.command.al_sh_dma_cnt_in[31:0]
@28
tb.dut.sata_top.sata_host.command.al_sh_dma_cnt_val_in[0]
@22
tb.dut.sata_top.sata_host.command.al_sh_dma_id_hi_in[31:0]
@28
tb.dut.sata_top.sata_host.command.al_sh_dma_id_hi_val_in[0]
@22
tb.dut.sata_top.sata_host.command.al_sh_dma_id_lo_in[31:0]
@28
tb.dut.sata_top.sata_host.command.al_sh_dma_id_lo_val_in[0]
@22
tb.dut.sata_top.sata_host.command.al_sh_feature_in[15:0]
@28
tb.dut.sata_top.sata_host.command.al_sh_feature_val_in[0]
tb.dut.sata_top.sata_host.command.al_sh_inter_in[0]
tb.dut.sata_top.sata_host.command.al_sh_inter_val_in[0]
@22
tb.dut.sata_top.sata_host.command.al_sh_lba_hi_in[23:0]
@28
tb.dut.sata_top.sata_host.command.al_sh_lba_hi_val_in[0]
@22
tb.dut.sata_top.sata_host.command.al_sh_lba_lo_in[23:0]
@28
tb.dut.sata_top.sata_host.command.al_sh_lba_lo_val_in[0]
tb.dut.sata_top.sata_host.command.al_sh_notif_in[0]
tb.dut.sata_top.sata_host.command.al_sh_notif_val_in[0]
@22
tb.dut.sata_top.sata_host.command.al_sh_port_in[3:0]
@28
tb.dut.sata_top.sata_host.command.al_sh_port_val_in[0]
@22
tb.dut.sata_top.sata_host.command.al_sh_tran_cnt_in[15:0]
@28
tb.dut.sata_top.sata_host.command.al_sh_tran_cnt_val_in[0]
tb.dut.sata_top.sata_host.command.clk[0]
@22
tb.dut.sata_top.sata_host.command.cmd[31:0]
@28
tb.dut.sata_top.sata_host.command.cmd_busy[0]
tb.dut.sata_top.sata_host.command.cmd_done_bad[0]
tb.dut.sata_top.sata_host.command.cmd_done_good[0]
@22
tb.dut.sata_top.sata_host.command.cmd_port[3:0]
@28
tb.dut.sata_top.sata_host.command.cmd_type[2:0]
tb.dut.sata_top.sata_host.command.cmd_val[0]
@22
tb.dut.sata_top.sata_host.command.raddr[9:0]
@28
tb.dut.sata_top.sata_host.command.rst[0]
tb.dut.sata_top.sata_host.command.sh_autoact[0]
tb.dut.sata_top.sata_host.command.sh_autoact_out[0]
@22
tb.dut.sata_top.sata_host.command.sh_command[7:0]
tb.dut.sata_top.sata_host.command.sh_command_out[7:0]
tb.dut.sata_top.sata_host.command.sh_control[7:0]
......@@ -263,15 +77,8 @@ tb.dut.sata_top.sata_host.command.sh_count[15:0]
tb.dut.sata_top.sata_host.command.sh_count_out[15:0]
tb.dut.sata_top.sata_host.command.sh_data[31:0]
tb.dut.sata_top.sata_host.command.sh_data_out[31:0]
@28
tb.dut.sata_top.sata_host.command.sh_data_val_out[0]
@22
tb.dut.sata_top.sata_host.command.sh_dev[7:0]
tb.dut.sata_top.sata_host.command.sh_dev_out[7:0]
@28
tb.dut.sata_top.sata_host.command.sh_dir[0]
tb.dut.sata_top.sata_host.command.sh_dir_out[0]
@22
tb.dut.sata_top.sata_host.command.sh_dma_cnt[31:0]
tb.dut.sata_top.sata_host.command.sh_dma_cnt_out[31:0]
tb.dut.sata_top.sata_host.command.sh_dma_id[63:0]
......@@ -284,412 +91,136 @@ tb.dut.sata_top.sata_host.command.sh_estatus[7:0]
tb.dut.sata_top.sata_host.command.sh_estatus_out[7:0]
tb.dut.sata_top.sata_host.command.sh_feature[15:0]
tb.dut.sata_top.sata_host.command.sh_feature_out[15:0]
@28
tb.dut.sata_top.sata_host.command.sh_inter[0]
tb.dut.sata_top.sata_host.command.sh_inter_out[0]
@22
tb.dut.sata_top.sata_host.command.sh_lba[47:0]
tb.dut.sata_top.sata_host.command.sh_lba_out[47:0]
@28
tb.dut.sata_top.sata_host.command.sh_notif[0]
tb.dut.sata_top.sata_host.command.sh_notif_out[0]
@22
tb.dut.sata_top.sata_host.command.sh_port[3:0]
tb.dut.sata_top.sata_host.command.sh_port_out[3:0]
tb.dut.sata_top.sata_host.command.sh_status[7:0]
tb.dut.sata_top.sata_host.command.sh_status_out[7:0]
tb.dut.sata_top.sata_host.command.sh_tran_cnt[15:0]
tb.dut.sata_top.sata_host.command.sh_tran_cnt_out[15:0]
@28
tb.dut.sata_top.sata_host.command.tl_data_busy_out[0]
@22
tb.dut.sata_top.sata_host.command.tl_data_in[31:0]
@28
tb.dut.sata_top.sata_host.command.tl_data_last_in[0]
tb.dut.sata_top.sata_host.command.tl_data_last_out[0]
@22
tb.dut.sata_top.sata_host.command.tl_data_out[31:0]
@28
tb.dut.sata_top.sata_host.command.tl_data_strobe_in[0]
tb.dut.sata_top.sata_host.command.tl_data_val_in[0]
tb.dut.sata_top.sata_host.command.tl_data_val_out[0]
tb.dut.sata_top.sata_host.command.tl_sh_autoact_in[0]
tb.dut.sata_top.sata_host.command.tl_sh_autoact_val_in[0]
@22
tb.dut.sata_top.sata_host.command.tl_sh_command_in[7:0]
@28
tb.dut.sata_top.sata_host.command.tl_sh_command_val_in[0]
@22
tb.dut.sata_top.sata_host.command.tl_sh_count_in[15:0]
@28
tb.dut.sata_top.sata_host.command.tl_sh_count_val_in[0]
@22
tb.dut.sata_top.sata_host.command.tl_sh_dev_in[7:0]
@28
tb.dut.sata_top.sata_host.command.tl_sh_dev_val_in[0]
tb.dut.sata_top.sata_host.command.tl_sh_dir_in[0]
tb.dut.sata_top.sata_host.command.tl_sh_dir_val_in[0]
@22
tb.dut.sata_top.sata_host.command.tl_sh_dma_cnt_in[31:0]
@28
tb.dut.sata_top.sata_host.command.tl_sh_dma_cnt_val_in[0]
@22
tb.dut.sata_top.sata_host.command.tl_sh_dma_id_in[63:0]
@28
tb.dut.sata_top.sata_host.command.tl_sh_dma_id_val_in[0]
@22
tb.dut.sata_top.sata_host.command.tl_sh_dma_off_in[31:0]
@28
tb.dut.sata_top.sata_host.command.tl_sh_dma_off_val_in[0]
@22
tb.dut.sata_top.sata_host.command.tl_sh_err_in[7:0]
@28
tb.dut.sata_top.sata_host.command.tl_sh_err_val_in[0]
@22
tb.dut.sata_top.sata_host.command.tl_sh_estatus_in[7:0]
@28
tb.dut.sata_top.sata_host.command.tl_sh_estatus_val_in[0]
tb.dut.sata_top.sata_host.command.tl_sh_inter_in[0]
tb.dut.sata_top.sata_host.command.tl_sh_inter_val_in[0]
@22
tb.dut.sata_top.sata_host.command.tl_sh_lba_in[47:0]
@28
tb.dut.sata_top.sata_host.command.tl_sh_lba_val_in[0]
tb.dut.sata_top.sata_host.command.tl_sh_notif_in[0]
tb.dut.sata_top.sata_host.command.tl_sh_notif_val_in[0]
@22
tb.dut.sata_top.sata_host.command.tl_sh_port_in[3:0]
@28
tb.dut.sata_top.sata_host.command.tl_sh_port_val_in[0]
@22
tb.dut.sata_top.sata_host.command.tl_sh_status_in[7:0]
@28
tb.dut.sata_top.sata_host.command.tl_sh_status_val_in[0]
@22
tb.dut.sata_top.sata_host.command.tl_sh_tran_cnt_in[15:0]
@28
tb.dut.sata_top.sata_host.command.tl_sh_tran_cnt_val_in[0]
@22
tb.dut.sata_top.sata_host.command.waddr[9:0]
@1401200
-host command layer
@c00200
@800201
-host phy level
@28
tb.dut.sata_top.sata_host.phy.clk[0]
tb.dut.sata_top.sata_host.phy.cplllock[0]
tb.dut.sata_top.sata_host.phy.cplllockdetclk[0]
tb.dut.sata_top.sata_host.phy.cpllreset[0]
tb.dut.sata_top.sata_host.phy.drpclk[0]
tb.dut.sata_top.sata_host.phy.extclk_n[0]
tb.dut.sata_top.sata_host.phy.extclk_p[0]
tb.dut.sata_top.sata_host.phy.extrst[0]
tb.dut.sata_top.sata_host.phy.gtrefclk[0]
tb.dut.sata_top.sata_host.phy.gtx_configured[0]
tb.dut.sata_top.sata_host.phy.gtx_ready[0]
@22
@23
tb.dut.sata_top.sata_host.phy.ll_charisk_in[3:0]
tb.dut.sata_top.sata_host.phy.ll_charisk_out[3:0]
tb.dut.sata_top.sata_host.phy.ll_data_in[31:0]
tb.dut.sata_top.sata_host.phy.ll_data_out[31:0]
tb.dut.sata_top.sata_host.phy.ll_err_out[3:0]
@28
tb.dut.sata_top.sata_host.phy.phy_ready[0]
tb.dut.sata_top.sata_host.phy.recal_tx_done[0]
tb.dut.sata_top.sata_host.phy.rst[0]
tb.dut.sata_top.sata_host.phy.rst_r[0]
@22
tb.dut.sata_top.sata_host.phy.rst_timer[7:0]
@28
tb.dut.sata_top.sata_host.phy.rxbyteisaligned[0]
@22
tb.dut.sata_top.sata_host.phy.rxcharisk[3:0]
tb.dut.sata_top.sata_host.phy.rxcharisk_out[3:0]
@28
tb.dut.sata_top.sata_host.phy.rxcominitdet[0]
tb.dut.sata_top.sata_host.phy.rxcomwakedet[0]
@22
tb.dut.sata_top.sata_host.phy.rxdata[31:0]
tb.dut.sata_top.sata_host.phy.rxdata_out[31:0]
tb.dut.sata_top.sata_host.phy.rxdisperr[3:0]
@28
tb.dut.sata_top.sata_host.phy.rxelecidle[0]
tb.dut.sata_top.sata_host.phy.rxelsempty[0]
tb.dut.sata_top.sata_host.phy.rxelsfull[0]
@22
tb.dut.sata_top.sata_host.phy.rxeyereset_cnt[6:0]
@28
tb.dut.sata_top.sata_host.phy.rxeyereset_done[0]
tb.dut.sata_top.sata_host.phy.rxn[0]
tb.dut.sata_top.sata_host.phy.rxn_in[0]
@22
tb.dut.sata_top.sata_host.phy.rxnotintable[3:0]
@28
tb.dut.sata_top.sata_host.phy.rxp[0]
tb.dut.sata_top.sata_host.phy.rxp_in[0]
tb.dut.sata_top.sata_host.phy.rxreset[0]
tb.dut.sata_top.sata_host.phy.rxreset_ack[0]
tb.dut.sata_top.sata_host.phy.rxreset_oob[0]
@22
tb.dut.sata_top.sata_host.phy.rxreset_oob_cnt[3:0]
@28
tb.dut.sata_top.sata_host.phy.rxreset_oob_stop[0]
tb.dut.sata_top.sata_host.phy.rxreset_req[0]
tb.dut.sata_top.sata_host.phy.rxresetdone[0]
tb.dut.sata_top.sata_host.phy.rxuserrdy[0]
tb.dut.sata_top.sata_host.phy.rxusrclk2[0]
tb.dut.sata_top.sata_host.phy.rxusrclk[0]
tb.dut.sata_top.sata_host.phy.sata_reset_done[0]
@22
tb.dut.sata_top.sata_host.phy.txcharisk[3:0]
tb.dut.sata_top.sata_host.phy.txcharisk_in[3:0]
@28
tb.dut.sata_top.sata_host.phy.txcominit[0]
tb.dut.sata_top.sata_host.phy.txcomwake[0]
@22
tb.dut.sata_top.sata_host.phy.txdata[31:0]
tb.dut.sata_top.sata_host.phy.txdata_in[31:0]
@28
tb.dut.sata_top.sata_host.phy.txelecidle[0]
tb.dut.sata_top.sata_host.phy.txn[0]
tb.dut.sata_top.sata_host.phy.txn_out[0]
tb.dut.sata_top.sata_host.phy.txoutclk[0]
tb.dut.sata_top.sata_host.phy.txp[0]
tb.dut.sata_top.sata_host.phy.txp_out[0]
tb.dut.sata_top.sata_host.phy.txpcsreset[0]
@22
tb.dut.sata_top.sata_host.phy.txpcsreset_cnt[3:0]
@28
tb.dut.sata_top.sata_host.phy.txpcsreset_req[0]
tb.dut.sata_top.sata_host.phy.txpcsreset_stop[0]
@29
tb.dut.sata_top.sata_host.phy.txpmareset_cnt[2:0]
tb.dut.sata_top.sata_host.phy.txpmareset_done[0]
tb.dut.sata_top.sata_host.phy.txreset[0]
tb.dut.sata_top.sata_host.phy.txresetdone[0]
tb.dut.sata_top.sata_host.phy.txuserrdy[0]
tb.dut.sata_top.sata_host.phy.txusrclk2[0]
tb.dut.sata_top.sata_host.phy.txusrclk[0]
tb.dut.sata_top.sata_host.phy.usrclk2[0]
tb.dut.sata_top.sata_host.phy.usrclk[0]
tb.dut.sata_top.sata_host.phy.usrpll_fb_clk[0]
tb.dut.sata_top.sata_host.phy.usrpll_locked[0]
@1401200
@1000201
-host phy level
@c00200
-host transport level
@28
tb.dut.sata_top.sata_host.transport.bad_fis_received[0]
tb.dut.sata_top.sata_host.transport.chk_inc_dword_limit_exceeded[0]
tb.dut.sata_top.sata_host.transport.chk_strobe_while_waitresp[0]
tb.dut.sata_top.sata_host.transport.cl_data_busy_in[0]
@22
tb.dut.sata_top.sata_host.transport.cl_data_in[31:0]
@28
tb.dut.sata_top.sata_host.transport.cl_data_last_in[0]
tb.dut.sata_top.sata_host.transport.cl_data_last_out[0]
tb.dut.sata_top.sata_host.transport.cl_data_mask_in[1:0]
tb.dut.sata_top.sata_host.transport.cl_data_mask_out[1:0]
@22
tb.dut.sata_top.sata_host.transport.cl_data_out[31:0]
@28
tb.dut.sata_top.sata_host.transport.cl_data_strobe_out[0]
tb.dut.sata_top.sata_host.transport.cl_data_val_in[0]
tb.dut.sata_top.sata_host.transport.cl_data_val_out[0]
tb.dut.sata_top.sata_host.transport.clk[0]
tb.dut.sata_top.sata_host.transport.cmd_busy[0]
tb.dut.sata_top.sata_host.transport.cmd_done_bad[0]
tb.dut.sata_top.sata_host.transport.cmd_done_good[0]
@22
tb.dut.sata_top.sata_host.transport.cmd_port[3:0]
tb.dut.sata_top.sata_host.transport.cmd_port_r[3:0]
@28
tb.dut.sata_top.sata_host.transport.cmd_type[2:0]
tb.dut.sata_top.sata_host.transport.cmd_type_r[2:0]
tb.dut.sata_top.sata_host.transport.cmd_val[0]
tb.dut.sata_top.sata_host.transport.data_limit_exceeded[0]
@22
tb.dut.sata_top.sata_host.transport.dword_cnt[13:0]
@28
tb.dut.sata_top.sata_host.transport.frame_ack[0]
tb.dut.sata_top.sata_host.transport.frame_busy[0]
tb.dut.sata_top.sata_host.transport.frame_done_bad[0]
tb.dut.sata_top.sata_host.transport.frame_done_good[0]
tb.dut.sata_top.sata_host.transport.frame_rej[0]
tb.dut.sata_top.sata_host.transport.frame_req[0]
tb.dut.sata_top.sata_host.transport.got_dma_activate[0]
@22
tb.dut.sata_top.sata_host.transport.got_dma_activate_port[3:0]
tb.dut.sata_top.sata_host.transport.header_bist[31:0]
tb.dut.sata_top.sata_host.transport.header_data[31:0]
tb.dut.sata_top.sata_host.transport.header_dmas[31:0]
tb.dut.sata_top.sata_host.transport.header_regfis[31:0]
@28
tb.dut.sata_top.sata_host.transport.incom_ack_bad[0]
tb.dut.sata_top.sata_host.transport.incom_ack_good[0]
tb.dut.sata_top.sata_host.transport.incom_done[0]
tb.dut.sata_top.sata_host.transport.incom_done_bad_r[0]
tb.dut.sata_top.sata_host.transport.incom_done_r[0]
tb.dut.sata_top.sata_host.transport.incom_invalidate[0]
tb.dut.sata_top.sata_host.transport.incom_start[0]
tb.dut.sata_top.sata_host.transport.incom_stop_req[0]
tb.dut.sata_top.sata_host.transport.incom_stop_req_timeout[0]
tb.dut.sata_top.sata_host.transport.ll_data_busy_out[0]
@22
tb.dut.sata_top.sata_host.transport.ll_data_in[31:0]
@28
tb.dut.sata_top.sata_host.transport.ll_data_last_in[0]
tb.dut.sata_top.sata_host.transport.ll_data_last_out[0]
tb.dut.sata_top.sata_host.transport.ll_data_mask_in[1:0]
tb.dut.sata_top.sata_host.transport.ll_data_mask_out[1:0]
@22
tb.dut.sata_top.sata_host.transport.ll_data_out[31:0]
@28
tb.dut.sata_top.sata_host.transport.ll_data_strobe_in[0]
tb.dut.sata_top.sata_host.transport.ll_data_val_in[0]
tb.dut.sata_top.sata_host.transport.ll_data_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.ll_header_dword[31:0]
@28
tb.dut.sata_top.sata_host.transport.ll_header_last[0]
tb.dut.sata_top.sata_host.transport.ll_header_val[0]
tb.dut.sata_top.sata_host.transport.loc_autoact[0]
@22
tb.dut.sata_top.sata_host.transport.loc_command[7:0]
tb.dut.sata_top.sata_host.transport.loc_count[15:0]
tb.dut.sata_top.sata_host.transport.loc_dev[7:0]
@28
tb.dut.sata_top.sata_host.transport.loc_dir[0]
@22
tb.dut.sata_top.sata_host.transport.loc_dma_cnt[31:0]
tb.dut.sata_top.sata_host.transport.loc_dma_id[63:0]
tb.dut.sata_top.sata_host.transport.loc_dma_off[31:0]
tb.dut.sata_top.sata_host.transport.loc_err[7:0]
tb.dut.sata_top.sata_host.transport.loc_estatus[7:0]
@28
tb.dut.sata_top.sata_host.transport.loc_inter[0]
@22
tb.dut.sata_top.sata_host.transport.loc_lba[47:0]
@28
tb.dut.sata_top.sata_host.transport.loc_notif[0]
@22
tb.dut.sata_top.sata_host.transport.loc_port[3:0]
tb.dut.sata_top.sata_host.transport.loc_status[7:0]
tb.dut.sata_top.sata_host.transport.loc_tran_cnt[15:0]
@28
tb.dut.sata_top.sata_host.transport.rst[0]
tb.dut.sata_top.sata_host.transport.sh_autoact_in[0]
tb.dut.sata_top.sata_host.transport.sh_autoact_out[0]
tb.dut.sata_top.sata_host.transport.sh_autoact_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.sh_buf_off_in[31:0]
tb.dut.sata_top.sata_host.transport.sh_command_in[7:0]
tb.dut.sata_top.sata_host.transport.sh_command_out[7:0]
@28
tb.dut.sata_top.sata_host.transport.sh_command_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.sh_control_in[7:0]
tb.dut.sata_top.sata_host.transport.sh_count_in[15:0]
tb.dut.sata_top.sata_host.transport.sh_count_out[15:0]
@28
tb.dut.sata_top.sata_host.transport.sh_count_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.sh_data_in[31:0]
tb.dut.sata_top.sata_host.transport.sh_dev_in[7:0]
tb.dut.sata_top.sata_host.transport.sh_dev_out[7:0]
@28
tb.dut.sata_top.sata_host.transport.sh_dev_val_out[0]
tb.dut.sata_top.sata_host.transport.sh_dir_in[0]
tb.dut.sata_top.sata_host.transport.sh_dir_out[0]
tb.dut.sata_top.sata_host.transport.sh_dir_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.sh_dma_cnt_in[31:0]
tb.dut.sata_top.sata_host.transport.sh_dma_cnt_out[31:0]
@28
tb.dut.sata_top.sata_host.transport.sh_dma_cnt_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.sh_dma_id_in[63:0]
tb.dut.sata_top.sata_host.transport.sh_dma_id_out[63:0]
@28
tb.dut.sata_top.sata_host.transport.sh_dma_id_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.sh_dma_off_out[31:0]
@28
tb.dut.sata_top.sata_host.transport.sh_dma_off_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.sh_err_out[7:0]
@28
tb.dut.sata_top.sata_host.transport.sh_err_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.sh_estatus_out[7:0]
@28
tb.dut.sata_top.sata_host.transport.sh_estatus_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.sh_feature_in[15:0]
@28
tb.dut.sata_top.sata_host.transport.sh_inter_in[0]
tb.dut.sata_top.sata_host.transport.sh_inter_out[0]
tb.dut.sata_top.sata_host.transport.sh_inter_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.sh_lba_in[47:0]
tb.dut.sata_top.sata_host.transport.sh_lba_out[47:0]
@28
tb.dut.sata_top.sata_host.transport.sh_lba_val_out[0]
tb.dut.sata_top.sata_host.transport.sh_notif_in[0]
tb.dut.sata_top.sata_host.transport.sh_notif_out[0]
tb.dut.sata_top.sata_host.transport.sh_notif_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.sh_port_in[3:0]
tb.dut.sata_top.sata_host.transport.sh_port_out[3:0]
@28
tb.dut.sata_top.sata_host.transport.sh_port_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.sh_status_out[7:0]
@28
tb.dut.sata_top.sata_host.transport.sh_status_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.sh_tran_cnt_in[15:0]
tb.dut.sata_top.sata_host.transport.sh_tran_cnt_out[15:0]
@28
tb.dut.sata_top.sata_host.transport.sh_tran_cnt_val_out[0]
@22
tb.dut.sata_top.sata_host.transport.state[7:0]
@28
tb.dut.sata_top.sata_host.transport.sync_escape_ack[0]
tb.dut.sata_top.sata_host.transport.sync_escape_req[0]
tb.dut.sata_top.sata_host.transport.watchdog_dwords[0]
tb.dut.sata_top.sata_host.transport.watchdog_eof[0]
@1401200
-host transport level
@c00200
-shadow registers
@28
tb.dut.sata_top.dma_regs.ACLK[0]
@22
tb.dut.sata_top.dma_regs.bram_raddr[31:0]
tb.dut.sata_top.dma_regs.bram_raddr_r[7:0]
tb.dut.sata_top.dma_regs.bram_rdata[31:0]
tb.dut.sata_top.dma_regs.bram_rdata_r[31:0]
@28
tb.dut.sata_top.dma_regs.bram_regen[0]
tb.dut.sata_top.dma_regs.bram_ren[0]
@22
tb.dut.sata_top.dma_regs.bram_waddr[31:0]
tb.dut.sata_top.dma_regs.bram_wdata[31:0]
@28
tb.dut.sata_top.dma_regs.bram_wen[0]
@22
tb.dut.sata_top.dma_regs.bram_wstb[3:0]
tb.dut.sata_top.dma_regs.cmd_in[31:0]
tb.dut.sata_top.dma_regs.cmd_out[31:0]
@28
tb.dut.sata_top.dma_regs.cmd_val_out[0]
tb.dut.sata_top.dma_regs.dma_done[0]
tb.dut.sata_top.dma_regs.dma_done_aclk[0]
tb.dut.sata_top.dma_regs.dma_issued[0]
tb.dut.sata_top.dma_regs.dma_start[0]
tb.dut.sata_top.dma_regs.dma_start_aclk[0]
tb.dut.sata_top.dma_regs.dma_type[0]
@22
tb.dut.sata_top.dma_regs.lba[31:0]
tb.dut.sata_top.dma_regs.mem_address[31:7]
tb.dut.sata_top.dma_regs.reg00[31:0]
......@@ -698,98 +229,36 @@ tb.dut.sata_top.dma_regs.reg04[31:0]
tb.dut.sata_top.dma_regs.reg08[31:0]
tb.dut.sata_top.dma_regs.reg10[31:0]
tb.dut.sata_top.dma_regs.reg14[31:0]
@28
tb.dut.sata_top.dma_regs.rst[0]
tb.dut.sata_top.dma_regs.sclk[0]
@22
tb.dut.sata_top.dma_regs.sector_cnt[31:0]
@28
tb.dut.sata_top.dma_regs.sh_autoact[0]
tb.dut.sata_top.dma_regs.sh_autoact_in[0]
tb.dut.sata_top.dma_regs.sh_autoact_val[0]
@22
tb.dut.sata_top.dma_regs.sh_buf_off[31:0]
@28
tb.dut.sata_top.dma_regs.sh_buf_off_val[0]
@22
tb.dut.sata_top.dma_regs.sh_command[7:0]
tb.dut.sata_top.dma_regs.sh_command_in[7:0]
@28
tb.dut.sata_top.dma_regs.sh_command_val[0]
@22
tb.dut.sata_top.dma_regs.sh_control[7:0]
tb.dut.sata_top.dma_regs.sh_control_in[7:0]
@28
tb.dut.sata_top.dma_regs.sh_control_val[0]
@22
tb.dut.sata_top.dma_regs.sh_count[15:0]
tb.dut.sata_top.dma_regs.sh_count_in[15:0]
@28
tb.dut.sata_top.dma_regs.sh_count_val[0]
@22
tb.dut.sata_top.dma_regs.sh_data[31:0]
tb.dut.sata_top.dma_regs.sh_data_in[31:0]
@28
tb.dut.sata_top.dma_regs.sh_data_strobe[0]
tb.dut.sata_top.dma_regs.sh_data_val[0]
tb.dut.sata_top.dma_regs.sh_data_val_in[0]
@22
tb.dut.sata_top.dma_regs.sh_dev[7:0]
tb.dut.sata_top.dma_regs.sh_dev_in[7:0]
@28
tb.dut.sata_top.dma_regs.sh_dev_val[0]
tb.dut.sata_top.dma_regs.sh_dir[0]
tb.dut.sata_top.dma_regs.sh_dir_in[0]
tb.dut.sata_top.dma_regs.sh_dir_val[0]
@22
tb.dut.sata_top.dma_regs.sh_dma_cnt[31:0]
tb.dut.sata_top.dma_regs.sh_dma_cnt_in[31:0]
@28
tb.dut.sata_top.dma_regs.sh_dma_cnt_val[0]
@22
tb.dut.sata_top.dma_regs.sh_dma_id_hi[31:0]
@28
tb.dut.sata_top.dma_regs.sh_dma_id_hi_val[0]
@22
tb.dut.sata_top.dma_regs.sh_dma_id_in[63:0]
tb.dut.sata_top.dma_regs.sh_dma_id_lo[31:0]
@28
tb.dut.sata_top.dma_regs.sh_dma_id_lo_val[0]
@22
tb.dut.sata_top.dma_regs.sh_dma_off_in[31:0]
tb.dut.sata_top.dma_regs.sh_err_in[7:0]
tb.dut.sata_top.dma_regs.sh_estatus_in[7:0]
tb.dut.sata_top.dma_regs.sh_feature[15:0]
tb.dut.sata_top.dma_regs.sh_feature_in[15:0]
@28
tb.dut.sata_top.dma_regs.sh_feature_val[0]
tb.dut.sata_top.dma_regs.sh_inter[0]
tb.dut.sata_top.dma_regs.sh_inter_in[0]
tb.dut.sata_top.dma_regs.sh_inter_val[0]
@22
tb.dut.sata_top.dma_regs.sh_lba_hi[23:0]
@28
tb.dut.sata_top.dma_regs.sh_lba_hi_val[0]
@22
tb.dut.sata_top.dma_regs.sh_lba_in[47:0]
tb.dut.sata_top.dma_regs.sh_lba_lo[23:0]
@28
tb.dut.sata_top.dma_regs.sh_lba_lo_val[0]
tb.dut.sata_top.dma_regs.sh_notif[0]
tb.dut.sata_top.dma_regs.sh_notif_in[0]
tb.dut.sata_top.dma_regs.sh_notif_val[0]
@22
tb.dut.sata_top.dma_regs.sh_port[3:0]
tb.dut.sata_top.dma_regs.sh_port_in[3:0]
@28
tb.dut.sata_top.dma_regs.sh_port_val[0]
@22
tb.dut.sata_top.dma_regs.sh_status_in[7:0]
tb.dut.sata_top.dma_regs.sh_tran_cnt[15:0]
tb.dut.sata_top.dma_regs.sh_tran_cnt_in[15:0]
@28
tb.dut.sata_top.dma_regs.sh_tran_cnt_val[0]
@22
tb.dut.sata_top.dma_regs.wdata[31:0]
@1401200
-shadow registers
......
utils/resync_data.v 0 → 100644
View file @ 90a85abd
/*******************************************************************************
* Module: resync_data
* Date:2015-12-22
* Author: Andrey Filippov
* Description: Resynchronize data between clock domains. No over/underruns
* are checker, start with half FIFO full. Async reset sets
* specifies output values regardless of the clocks
*
* Copyright (c) 2014 Elphel, Inc.
* resync_data.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* resync_data.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module resync_data
#(
parameter integer DATA_WIDTH=16,
parameter integer DATA_DEPTH=4, // >= 2
parameter INITIAL_VALUE = 0
) (
input arst, // async reset, active high (global)
input srst, // same as arst, but relies on the clocks
input wclk, // write clock - positive edge
input rclk, // read clock - positive edge
input we, // write enable
input re, // read enable
input [DATA_WIDTH-1:0] data_in, // input data
output reg [DATA_WIDTH-1:0] data_out, // output data
output reg valid // data valid @ rclk
);
localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
reg [DATA_DEPTH-1:0] raddr;
reg [DATA_DEPTH-1:0] waddr;
reg [1:0] rrst = 3;
always @ (posedge rclk or posedge arst) begin
if (arst) valid <= 0;
else if (srst) valid <= 0;
else if (&waddr[DATA_DEPTH-2:0] && we) valid <= 1; // just once set and stays until reset
end
always @ (posedge wclk or posedge arst) begin
if (arst) waddr <= 0;
else if (srst) waddr <= 0;
else if (we) waddr <= waddr + 1;
end
always @ (posedge rclk or posedge arst) begin
if (arst) rrst <= 3;
else if (srst) rrst <= 3; // resync to rclk
else rrst <= rrst << 1;
if (arst) raddr <= 0;
else if (rrst[0]) raddr <= 0;
else if (re || rrst[1]) raddr <= raddr + 1;
if (arst) data_out <= INITIAL_VALUE;
else if (rrst[0]) data_out <= INITIAL_VALUE;
else if (re || rrst[1]) data_out <= ram[raddr];
end
always @ (posedge wclk) begin
if (we) ram[waddr] <= data_in;
end
endmodule
x393 @ 8af3d0c0
Subproject commit 9a17dbfae721f542dc546b8659620ecdc441a9ee
Subproject commit 8af3d0c0ec45090474e57e1501e852187287fdbb
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