Working on AHCI registers

.project

@@ -5,6 +5,11 @@
 	<projects>
 	</projects>
 	<buildSpec>
+		<buildCommand>
+			<name>org.python.pydev.PyDevBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
 		<buildCommand>
 			<name>com.elphel.vdt.veditor.simulateBuilder</name>
 			<arguments>
@@ -41,6 +46,7 @@
 	</buildSpec>
 	<natures>
 		<nature>com.elphel.vdt.veditor.HdlNature</nature>
+		<nature>org.python.pydev.pythonNature</nature>
 	</natures>
 	<linkedResources>
 		<link>

dma/axi_regs.v

@@ -100,6 +100,7 @@ axibram_write(
     .dev_ready      (1'b1),
     .bram_wclk      (),
     .bram_waddr     (bram_waddr[15:0]),
+    .pre_bram_wen   (),
     .bram_wen       (bram_wen),
     .bram_wstb      (bram_wstb),
     .bram_wdata     (bram_wdata)