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Commit 84a54d4f authored by Andrey Filippov's avatar Andrey Filippov
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debugging: passed request/receive 'identify'

parent 3f3c3b83
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Showing with 392 additions and 66 deletions
ahci/ahci_dma.v
View file @ 84a54d4f
...@@ -204,7 +204,7 @@ module ahci_dma ( ...@@ -204,7 +204,7 @@ module ahci_dma (
wire cmd_done_hclk; wire cmd_done_hclk;
wire ct_done_mclk; wire ct_done_mclk;
reg [3:0] afi_alen; reg [3:0] afi_alen;
wire afi_wcount_many = !afi_wcount[7] && !(afi_wcount[6:4]); wire afi_wcount_many = !afi_wcount[7] && !(&afi_wcount[6:4]);
reg data_next_burst; reg data_next_burst;
...@@ -310,8 +310,10 @@ module ahci_dma ( ...@@ -310,8 +310,10 @@ module ahci_dma (
end end
// afi_rd_ctl <= { afi_rd_ctl[0],(ct_busy_r[0] || prd_rd_busy) && ((|afi_rcount[7:SAFE_RD_BITS]) || (afi_rvalid && !(|afi_rd_ctl)))};
wire debug_01 = ct_busy_r[0] || prd_rd_busy ;
wire debug_02 =|afi_rcount[7:SAFE_RD_BITS];
wire debug_03 = (afi_rvalid && !(|afi_rd_ctl));
always @ (posedge hclk) begin always @ (posedge hclk) begin
prd_start_hclk_r <= prd_start_hclk; prd_start_hclk_r <= prd_start_hclk;
...@@ -379,7 +381,7 @@ module ahci_dma ( ...@@ -379,7 +381,7 @@ module ahci_dma (
if (afi_rd_ctl[0] && is_prd_addr && (int_data_addr[0])) data_irq <= afi_rdata[63]; if (afi_rd_ctl[0] && is_prd_addr && (int_data_addr[0])) data_irq <= afi_rdata[63];
if (afi_rd_ctl[0] && is_prd_addr && (int_data_addr[0])) wcount[21:1] <= afi_rdata[37:17]; if (afi_rd_ctl[0] && is_prd_addr && (int_data_addr[0])) wcount[21:1] <= afi_rdata[53:33];
wcount_set <= afi_rd_ctl[0] && is_prd_addr && (int_data_addr[0]); wcount_set <= afi_rd_ctl[0] && is_prd_addr && (int_data_addr[0]);
...@@ -405,10 +407,10 @@ module ahci_dma ( ...@@ -405,10 +407,10 @@ module ahci_dma (
ct_over_prd_enabled[1] <= ct_over_prd_enabled[0]; // detecting 0->1 transition ct_over_prd_enabled[1] <= ct_over_prd_enabled[0]; // detecting 0->1 transition
// generate busy for PRD table entry read // generate busy for PRD table entry read
if (hrst) prd_rd_busy <= 0; if (hrst) prd_rd_busy <= 0;
else if (prd_rd_busy) prd_rd_busy <= 1; // else if (prd_rd_busy) prd_rd_busy <= 1;
else if (wcount_set) prd_rd_busy <= 0; else if (raddr_prd_rq && axi_set_raddr_ready) prd_rd_busy <= 1;
else if (wcount_set) prd_rd_busy <= 0;
if (cmd_start_hclk) dev_wr_hclk <= dev_wr_mclk; // 1: memory -> device, 0: device -> memory if (cmd_start_hclk) dev_wr_hclk <= dev_wr_mclk; // 1: memory -> device, 0: device -> memory
......
ahci/ahci_dma_wr_fifo.v
View file @ 84a54d4f
...@@ -80,14 +80,15 @@ module ahci_dma_wr_fifo#( ...@@ -80,14 +80,15 @@ module ahci_dma_wr_fifo#(
reg [63:16] fifo_do_prev; // only 48 bits are needed reg [63:16] fifo_do_prev; // only 48 bits are needed
reg [(1<<ADDRESS_BITS)-1:0] fifo_full; // set in write clock domain reg [(1<<ADDRESS_BITS)-1:0] fifo_full; // set in write clock domain
reg [(1<<ADDRESS_BITS)-1:0] fifo_nempty;// set in read clock domain reg [(1<<ADDRESS_BITS)-1:0] fifo_nempty;// set in read clock domain
wire fifo_wr = (din_avail && din_rdy) || (waddr[0] && flush_mclk); // flush may add extra write of junk wire fifo_wr = en_fifo_wr && ((din_avail && din_rdy) || (waddr[0] && flush_mclk)); // flush may add extra write of junk
// wire fifo_rd; // wire fifo_rd;
wire [(1<<ADDRESS_BITS)-1:0] fifo_full2 = {fifo_full[0],fifo_full[ADDRESS_NUM-1:1]}; wire [(1<<ADDRESS_BITS)-1:0] fifo_full2 = {~fifo_full[0],fifo_full[ADDRESS_NUM-1:1]};
reg hrst_mclk; reg hrst_mclk;
reg fifo_dav; // @hclk reg fifo_dav; // @hclk
reg fifo_dav2; // @hclk reg fifo_dav2; // @hclk - ??? at least two are available?
reg fifo_half_mclk; // Half Fifo is empty, OK to write reg fifo_half_mclk; // Half Fifo is empty, OK to write
wire [63:0] fifo_do = {fifo1_ram [raddr[ADDRESS_BITS:1]], fifo0_ram [raddr[ADDRESS_BITS:1]]}; /// wire [63:0] fifo_do = {fifo1_ram [raddr[ADDRESS_BITS:1]], fifo0_ram [raddr[ADDRESS_BITS:1]]};
wire [63:0] fifo_do = {fifo1_ram [raddr[ADDRESS_BITS-1:0]], fifo0_ram [raddr[ADDRESS_BITS-1:0]]};
wire dout_we_w; wire dout_we_w;
reg [1:0] dout_we_r; reg [1:0] dout_we_r;
...@@ -125,7 +126,8 @@ module ahci_dma_wr_fifo#( ...@@ -125,7 +126,8 @@ module ahci_dma_wr_fifo#(
wire fifo_out_ready = en_fifo_rd && (!need_fifo || (fifo_dav && (fifo_dav2 || !fifo_rd_r))); wire fifo_out_ready = en_fifo_rd && (!need_fifo || (fifo_dav && (fifo_dav2 || !fifo_rd_r)));
assign flush_hclk = is_last_prd && !flushing && !nfp[1] && last_qword && waddr[0]; // waddr[0] - other clock domain, but OK here, /// assign flush_hclk = is_last_prd && !flushing && !nfp[1] && last_qword && waddr[0]; // waddr[0] - other clock domain, but OK here,
assign flush_hclk = busy && is_last_prd && !flushing && !nfp[1] && last_qword && waddr[0]; // waddr[0] - other clock domain, but OK here,
// it was last 1->0 before previous FIFO read. flush_hclk will only be generated for odd number of dwords // it was last 1->0 before previous FIFO read. flush_hclk will only be generated for odd number of dwords
assign din_rdy = en_fifo_wr && fifo_half_mclk; assign din_rdy = en_fifo_wr && fifo_half_mclk;
...@@ -146,17 +148,20 @@ module ahci_dma_wr_fifo#( ...@@ -146,17 +148,20 @@ module ahci_dma_wr_fifo#(
if (hrst || init) raddr <= 0; if (hrst || init) raddr <= 0;
else if (fifo_rd) raddr <= raddr + 1; else if (fifo_rd) raddr <= raddr + 1; // increment for 64-bit words
// reg [ADDRESS_BITS : 0] raddr; // 1 extra bit // reg [ADDRESS_BITS : 0] raddr; // 1 extra bit
if (hrst || init) fifo_nempty <= {{(ADDRESS_NUM>>1){1'b0}},{(ADDRESS_NUM>>1){1'b1}}};// 8'b00001111 if (hrst || init) fifo_nempty <= {{(ADDRESS_NUM>>1){1'b0}},{(ADDRESS_NUM>>1){1'b1}}};// 8'b00001111
else if (fifo_rd && raddr[0]) fifo_nempty <= {fifo_nempty[ADDRESS_NUM-2:0],raddr[ADDRESS_BITS] ^ raddr[ADDRESS_BITS-1]}; /// else if (fifo_rd && raddr[0]) fifo_nempty <= {fifo_nempty[ADDRESS_NUM-2:0],raddr[ADDRESS_BITS] ^ raddr[ADDRESS_BITS-1]};
else if (fifo_rd) fifo_nempty <= {fifo_nempty[ADDRESS_NUM-2:0],~raddr[ADDRESS_BITS] ^ raddr[ADDRESS_BITS-1]};
fifo_dav <= !init && en_fifo_rd && (fifo_full [raddr[ADDRESS_BITS:1]] ^ raddr[ADDRESS_BITS]); /// fifo_dav <= !init && en_fifo_rd && (fifo_full [raddr[ADDRESS_BITS:1]] ^ raddr[ADDRESS_BITS]);
fifo_dav2 <= !init && en_fifo_rd && (fifo_full2[raddr[ADDRESS_BITS:1]]); fifo_dav <= !init && en_fifo_rd && (fifo_full [raddr[ADDRESS_BITS-1:0]] ^ raddr[ADDRESS_BITS]);
/// fifo_dav2 <= !init && en_fifo_rd && (fifo_full2[raddr[ADDRESS_BITS:1]]); //?^ raddr[ADDRESS_BITS]); // FIXME
fifo_dav2 <= !init && en_fifo_rd && (fifo_full2[raddr[ADDRESS_BITS-1:0]] ^ raddr[ADDRESS_BITS]); //?^ raddr[ADDRESS_BITS]); // FIXME
if (fifo_rd) fifo_do_prev[63:16] <= fifo_do[63:16]; if (fifo_rd) fifo_do_prev[63:16] <= fifo_do[63:16];
...@@ -261,14 +266,16 @@ module ahci_dma_wr_fifo#( ...@@ -261,14 +266,16 @@ module ahci_dma_wr_fifo#(
else if (fifo_wr) waddr <= waddr + 1; else if (fifo_wr) waddr <= waddr + 1;
if (hrst_mclk || init_mclk) fifo_full <= 0; if (hrst_mclk || init_mclk) fifo_full <= 0;
else if (fifo_wr) fifo_full <= {fifo_full[ADDRESS_NUM-2:0], waddr[ADDRESS_BITS+1]}; /// else if (fifo_wr) fifo_full <= {fifo_full[ADDRESS_NUM-2:0], waddr[ADDRESS_BITS+1]};
else if (fifo_wr && waddr[0]) fifo_full <= {fifo_full[ADDRESS_NUM-2:0], ~waddr[ADDRESS_BITS+1]};
fifo_half_mclk <= fifo_nempty [waddr[ADDRESS_BITS:1]] ^ waddr[ADDRESS_BITS+1]; fifo_half_mclk <= en_fifo_wr && fifo_nempty [waddr[ADDRESS_BITS:1]] ^ waddr[ADDRESS_BITS+1];
if (fifo_wr && !waddr[0]) fifo0_ram[waddr[ADDRESS_BITS:1]] <= din; if (fifo_wr && !waddr[0]) fifo0_ram[waddr[ADDRESS_BITS:1]] <= din;
if (fifo_wr && waddr[0]) fifo1_ram[waddr[ADDRESS_BITS:1]] <= din; if (fifo_wr && waddr[0]) fifo1_ram[waddr[ADDRESS_BITS:1]] <= din;
fifo_nempty_mclk <= (fifo_full [raddr[ADDRESS_BITS:1]] ^ raddr[ADDRESS_BITS]); // only valid after read is stopped /// fifo_nempty_mclk <= (fifo_full [raddr[ADDRESS_BITS:1]] ^ raddr[ADDRESS_BITS]); // only valid after read is stopped
fifo_nempty_mclk <= (fifo_full [raddr[ADDRESS_BITS-1:0]] ^ raddr[ADDRESS_BITS]); // only valid after read is stopped
end end
......
ahci/ahci_fis_receive.v
View file @ 84a54d4f
...@@ -192,7 +192,7 @@ localparam DATA_TYPE_ERR = 3; ...@@ -192,7 +192,7 @@ localparam DATA_TYPE_ERR = 3;
reg update_sig_r; reg update_sig_r;
// reg update_pio_r; // reg update_pio_r;
reg update_prdbc_r; reg update_prdbc_r;
reg get_fis_busy_r; reg [1:0] get_fis_busy_r;
reg [7:0] pio_es_r; // value of PIO E_Status reg [7:0] pio_es_r; // value of PIO E_Status
...@@ -207,9 +207,9 @@ localparam DATA_TYPE_ERR = 3; ...@@ -207,9 +207,9 @@ localparam DATA_TYPE_ERR = 3;
reg fis_first_flushing_r; reg fis_first_flushing_r;
// Forward data to DMA (dev->mem) engine // Forward data to DMA (dev->mem) engine
assign dma_in_valid = dma_in_ready && (hba_data_in_type == DATA_TYPE_DMA) && data_in_ready && !too_long_err; assign dma_in_valid = dma_in && dma_in_ready && (hba_data_in_type == DATA_TYPE_DMA) && data_in_ready && !too_long_err;
// Will also try to skip to the end of too long FIS // Will also try to skip to the end of too long FIS
assign dma_skipping_extra = (fis_extra_r || too_long_err) && (hba_data_in_type == DATA_TYPE_DMA) && data_in_ready ; assign dma_skipping_extra = dma_in && (fis_extra_r || too_long_err) && (hba_data_in_type == DATA_TYPE_DMA) && data_in_ready ;
assign dma_in_stop = dma_in && data_in_ready && (hba_data_in_type != DATA_TYPE_DMA); // || assign dma_in_stop = dma_in && data_in_ready && (hba_data_in_type != DATA_TYPE_DMA); // ||
...@@ -225,7 +225,7 @@ localparam DATA_TYPE_ERR = 3; ...@@ -225,7 +225,7 @@ localparam DATA_TYPE_ERR = 3;
assign tfd_err = tf_err_sts[15:8]; assign tfd_err = tf_err_sts[15:8];
assign xfer_cntr = xfer_cntr_r[31:2]; assign xfer_cntr = xfer_cntr_r[31:2];
assign get_fis_busy = get_fis_busy_r; assign get_fis_busy = get_fis_busy_r[0];
// assign data_in_dwords = data_out_dwords_r; // assign data_in_dwords = data_out_dwords_r;
assign data_in_dwords = data_in_dwords_r; assign data_in_dwords = data_in_dwords_r;
...@@ -293,7 +293,7 @@ localparam DATA_TYPE_ERR = 3; ...@@ -293,7 +293,7 @@ localparam DATA_TYPE_ERR = 3;
else if (get_fis) fis_rec_run <= 1; else if (get_fis) fis_rec_run <= 1;
else if (is_fis_end && data_in_ready) fis_rec_run <= 0; else if (is_fis_end && data_in_ready) fis_rec_run <= 0;
if (hba_rst) dwords_over <= 0; if (hba_rst ||get_fis) dwords_over <= 0;
else if (wreg_we_r && !(|fis_dcount)) dwords_over <= 1; else if (wreg_we_r && !(|fis_dcount)) dwords_over <= 1;
if (hba_rst) wreg_we_r <= 0; if (hba_rst) wreg_we_r <= 0;
...@@ -301,14 +301,17 @@ localparam DATA_TYPE_ERR = 3; ...@@ -301,14 +301,17 @@ localparam DATA_TYPE_ERR = 3;
fis_end_r <= {fis_end_r[0], fis_end_w}; fis_end_r <= {fis_end_r[0], fis_end_w};
if (hba_rst) get_fis_busy_r <= 0; if (hba_rst) get_fis_busy_r[0] <= 0;
else if (get_fis) get_fis_busy_r <= 1; else if (get_fis) get_fis_busy_r[0] <= 1;
else if (too_long_err || fis_end_w) get_fis_busy_r <= 0; else if (too_long_err || fis_end_w) get_fis_busy_r[0] <= 0;
get_fis_busy_r[1] <=get_fis_busy_r[0];
get_fis_done <= get_fis_busy_r && (too_long_err || fis_end_w); get_fis_done <= get_fis_busy_r[0] && (too_long_err || fis_end_w);
// if (hba_rst || get_fis) fis_first_vld <= 0; /// if (hba_rst || get_fis) fis_first_vld <= 0;
if (hba_rst || fis_end_w) fis_first_vld <= 0; // is_FIS_HEAD stays on longer than just get_fis /// if (hba_rst || fis_end_w) fis_first_vld <= 0; // is_FIS_HEAD stays on longer than just get_fis
if (hba_rst || (|get_fis_busy_r))fis_first_vld <= 0; // is_FIS_HEAD stays on longer than just get_fis
else if (is_FIS_HEAD) fis_first_vld <= 1; else if (is_FIS_HEAD) fis_first_vld <= 1;
if (hba_rst || get_fis) fis_ok <= 0; if (hba_rst || get_fis) fis_ok <= 0;
...@@ -385,8 +388,8 @@ localparam DATA_TYPE_ERR = 3; ...@@ -385,8 +388,8 @@ localparam DATA_TYPE_ERR = 3;
// Maybe it is not needed if the fsm will send this pulse? // Maybe it is not needed if the fsm will send this pulse?
// data_in_words_apply <= dma_in_stop && (hba_data_in_type == DATA_TYPE_OK); // data_in_words_apply <= dma_in_stop && (hba_data_in_type == DATA_TYPE_OK);
if (hba_rst || get_fis_busy_r) fis_first_invalid_r <= 0; if (hba_rst || (|get_fis_busy_r)) fis_first_invalid_r <= 0;
else fis_first_invalid_r <= is_FIS_NOT_HEAD; else fis_first_invalid_r <= is_FIS_NOT_HEAD;
if (!fis_first_invalid_r) fis_first_flushing_r <= 0; if (!fis_first_invalid_r) fis_first_flushing_r <= 0;
else if (fis_first_flush) fis_first_flushing_r <= 1; else if (fis_first_flush) fis_first_flushing_r <= 1;
......
device/sata_device.v
View file @ 84a54d4f
...@@ -661,6 +661,7 @@ task wait_ready; // @SuppressThisWarning VEditor - Used in testbench ...@@ -661,6 +661,7 @@ task wait_ready; // @SuppressThisWarning VEditor - Used in testbench
end end
endtask endtask
task send_good_status; // @SuppressThisWarning VEditor - Used in testbench task send_good_status; // @SuppressThisWarning VEditor - Used in testbench
input integer id; input integer id;
input [2:0] dev_specific_status_bits; input [2:0] dev_specific_status_bits;
...@@ -673,9 +674,55 @@ task send_good_status; // @SuppressThisWarning VEditor - Used in testbench ...@@ -673,9 +674,55 @@ task send_good_status; // @SuppressThisWarning VEditor - Used in testbench
transmit_data[3] = 1; transmit_data[3] = 1;
transmit_data[4] = 0; transmit_data[4] = 0;
linkTransmitFIS(id, 5, 0, status); linkTransmitFIS(id, 5, 0, status);
// linkTransmitFIS (
end end
endtask endtask
task send_pio_setup; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
input d2h; // 'D' bit: 1 - Data will be D2H, 0 - H2D
input irq; // Set I bit
input [7:0] xmit_status;
input [7:0] xmit_error;
input [7:0] xmit_e_status;
input [15:0] xfer_count;
input [ 7:0] dev;
input [23:0] lba_low; // LBA_low dword
input [23:0] lba_high; // LBA high dword
input [15:0] count; //
output integer status;
begin
transmit_data[0] = FIS_PIOS |
(d2h? 'h2000:0) |
(irq? 'h4000:0) |
(xmit_status << 16) |
(xmit_error << 24);
transmit_data[1] = {dev, lba_low};
transmit_data[2] = {8'b0,lba_high};
transmit_data[3] = {xmit_e_status, 8'b0,count};
transmit_data[4] = {16'b0, xfer_count};
linkTransmitFIS(id, 5, 0, status);
end
endtask
task send_identify_data; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
output integer status;
reg [15:0] identify_data[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i;
begin
$readmemh("input_data/identify.dat",identify_data);
transmit_data[0] = FIS_DATA;
for (i=0;i<128;i=i+1) begin
transmit_data[i+1] = {identify_data[2 * i+1], identify_data[2 * i]};
end
linkTransmitFIS(id, 129, 0, status);
end
endtask
/* /*
* Transmits data to a host. ~Link Transmit FSM * Transmits data to a host. ~Link Transmit FSM
* Correct execution, as it shall be w/o errors from a device side. (except timeouts and data consistency, see below) * Correct execution, as it shall be w/o errors from a device side. (except timeouts and data consistency, see below)
...@@ -774,7 +821,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench ...@@ -774,7 +821,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
// $display("[Device] LINK: Sent data = %h", transmit_data[cnt]); // $display("[Device] LINK: Sent data = %h", transmit_data[cnt]);
DEV_TITLE = "Sent data"; DEV_TITLE = "Sent data";
DEV_DATA = transmit_data[cnt]; DEV_DATA = transmit_data[cnt];
$display("[Device] LINK: %s = %h @%t", DEV_TITLE, DEV_DATA, $time); $display("[Device] LINK: %s = %h (#%d) @%t", DEV_TITLE, DEV_DATA, cnt, $time);
@ (posedge clk) @ (posedge clk)
rprim = linkGetPrim(0); rprim = linkGetPrim(0);
if (rprim == "SYNC") begin if (rprim == "SYNC") begin
......
host/link.v
View file @ 84a54d4f
...@@ -720,17 +720,44 @@ always @ (posedge clk) ...@@ -720,17 +720,44 @@ always @ (posedge clk)
`endif `endif
`ifdef SIMULATION `ifdef SIMULATION
always @ (posedge clk) integer sim_cnt;
begin always @ (posedge clk) begin
if (incom_start) begin
HOST_LINK_TITLE = "Incoming start";
$display("[Host] LINK: %s @%t", HOST_LINK_TITLE, $time);
sim_cnt = 0;
end
if (data_val_out) begin if (data_val_out) begin
// $display("[Host] LINK: From device - received data = %h @%t", data_out, $time);
HOST_LINK_TITLE = "From device - received data"; HOST_LINK_TITLE = "From device - received data";
HOST_LINK_DATA = data_out; HOST_LINK_DATA = data_out;
$display("[Host] LINK: %s = %h @%t", HOST_LINK_TITLE, HOST_LINK_DATA, $time); $display("[Host] LINK: %s = %h (#%d)@%t", HOST_LINK_TITLE, HOST_LINK_DATA, sim_cnt, $time);
//`endif sim_cnt = sim_cnt + 1;
end
if (incom_done) begin
HOST_LINK_TITLE = "Incoming end";
$display("[Host] LINK: %s @%t", HOST_LINK_TITLE, $time);
sim_cnt = 0;
end
if (incom_invalidate) begin
HOST_LINK_TITLE = "Incoming invalidate";
$display("[Host] LINK: %s @%t", HOST_LINK_TITLE, $time);
sim_cnt = 0;
end
if (incom_sync_escape) begin
HOST_LINK_TITLE = "Incoming sync_escape";
$display("[Host] LINK: %s @%t", HOST_LINK_TITLE, $time);
sim_cnt = 0;
end
if (incom_ack_good) begin
HOST_LINK_TITLE = "Incoming ack_good";
$display("[Host] LINK: %s @%t", HOST_LINK_TITLE, $time);
sim_cnt = 0;
end
if (incom_ack_bad) begin
HOST_LINK_TITLE = "Incoming ack_bad";
$display("[Host] LINK: %s @%t", HOST_LINK_TITLE, $time);
sim_cnt = 0;
end end
// if (inc_is_data) begin // if (inc_is_data) begin
// $display("[Host] LINK: From device - received raw data = %h", phy_data_in); // $display("[Host] LINK: From device - received raw data = %h", phy_data_in);
// end // end
......
tb/tb_ahci.tf
View file @ 84a54d4f
...@@ -800,6 +800,13 @@ initial begin //Host ...@@ -800,6 +800,13 @@ initial begin //Host
//HBA_PORT__PxIE__DHRE__MASK = 'h1; //HBA_PORT__PxIE__DHRE__MASK = 'h1;
end end
function func_is_dev_identify;
input [31:0] dw;
begin
func_is_dev_identify = ((dw & 'hff) == FIS_H2DR ) && (((dw >> 16) & 'hff) == ATA_IDFY);
end
endfunction
integer status; integer status;
initial begin //Device initial begin //Device
dev.clear_transmit_pause(0); dev.clear_transmit_pause(0);
...@@ -812,8 +819,39 @@ initial begin //Device ...@@ -812,8 +819,39 @@ initial begin //Device
5, // input [2:0] dev_specific_status_bits; 5, // input [2:0] dev_specific_status_bits;
1, // input irq; 1, // input irq;
status); // output integer status; status); // output integer status;
DEVICE_TITLE = "Device sent D2H RS"; DEVICE_TITLE = "Device sent D2H FIS";
$display("[Dev-TB]: %s, status = 0x%x @%t", DEVICE_TITLE, status, $time); $display("[Dev-TB]: %s, status = 0x%x @%t", DEVICE_TITLE, status, $time);
// Wait for host requests 'identify'
@(dev.receive_id);
if (func_is_dev_identify(dev.receive_data[0])) begin
DEVICE_TITLE = "Got Identify";
$display("[Dev-TB]: %s @%t", DEVICE_TITLE, $time);
$display("[Dev-TB]: %h @%t", dev.receive_data[0], $time);
dev.send_pio_setup (67, // input integer id;
1, // input d2h; // 'D' bit: 1 - Data will be D2H, 0 - H2D
1, // input irq; // Set I bit
'h30, // input [7:0] xmit_status; // something different to check host
0, // input [7:0] xmit_error;
'h60, // input [7:0] xmit_e_status;
512, // input [15:0] xfer_count; Identify block size
0, // input [ 7:0] dev;
0, // input [23:0] lba_low; // LBA_low dword
0, // input [23:0] lba_high; // LBA high dword
0, // input [15:0] count; //
status); // output integer status;
DEVICE_TITLE = "Device sent PIOS FIS";
$display("[Dev-TB]: %s, status = 0x%x @%t", DEVICE_TITLE, status, $time);
dev.send_identify_data(68, // input integer id;
status); // output integer status;
DEVICE_TITLE = "Device sent Data FIS (Identify)";
$display("[Dev-TB]: %s, status = 0x%x @%t", DEVICE_TITLE, status, $time);
end else begin
DEVICE_TITLE = "Expected Identify, got else";
$display("[Dev-TB]: %s @%t", DEVICE_TITLE, $time);
$display("[Dev-TB]: %h @%t", dev.receive_data[0], $time);
end
end end
initial begin initial begin
......
tb_ahci_01.sav
View file @ 84a54d4f
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Tue Jan 26 07:42:26 2016 [*] Wed Jan 27 00:58:43 2016
[*] [*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160126002016009.fst" [dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160126175635551.fst"
[dumpfile_mtime] "Tue Jan 26 07:20:39 2016" [dumpfile_mtime] "Wed Jan 27 00:57:30 2016"
[dumpfile_size] 3075666 [dumpfile_size] 6579639
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav" [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 20289400 [timestart] 0
[size] 1823 1180 [size] 1823 1180
[pos] 1994 0 [pos] 1994 0
*-15.994723 20457430 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-23.000113 25083634 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci. [treeopen] tb_ahci.
[treeopen] tb_ahci.dev. [treeopen] tb_ahci.dev.
[treeopen] tb_ahci.dev.phy. [treeopen] tb_ahci.dev.phy.
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
[treeopen] tb_ahci.dut.sata_top.ahci_top_i. [treeopen] tb_ahci.dut.sata_top.ahci_top_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i. [treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i. [treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i. [treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i. [treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i. [treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.
...@@ -31,7 +32,7 @@ ...@@ -31,7 +32,7 @@
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i. [treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i. [treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i.
[treeopen] tb_ahci.simul_axi_hp_rd_i. [treeopen] tb_ahci.simul_axi_hp_rd_i.
[sst_width] 420 [sst_width] 253
[signals_width] 330 [signals_width] 330
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 618 [sst_vpaned_height] 618
...@@ -49,7 +50,7 @@ tb_ahci.read_and_wait.address[31:0] ...@@ -49,7 +50,7 @@ tb_ahci.read_and_wait.address[31:0]
tb_ahci.dut.TXN tb_ahci.dut.TXN
tb_ahci.dut.RXN tb_ahci.dut.RXN
tb_ahci.dut.irq tb_ahci.dut.irq
@800200 @c00200
-axi_ahci_regs -axi_ahci_regs
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.aclk tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.aclk
...@@ -282,7 +283,6 @@ tb_ahci.rstb ...@@ -282,7 +283,6 @@ tb_ahci.rstb
- -
@1401200 @1401200
-axibram_read -axibram_read
@1000200
-axi_ahci_regs -axi_ahci_regs
@c00200 @c00200
-ahci_sata_layers -ahci_sata_layers
...@@ -433,7 +433,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tfd_err[7:0] ...@@ -433,7 +433,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tfd_err[7:0]
-ahci_fis_receive -ahci_fis_receive
@1401200 @1401200
-ahci_top -ahci_top
@800200 @c00200
-ahci_ctrl_stat -ahci_ctrl_stat
@22 @22
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_addr[9:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_addr[9:0]
...@@ -736,7 +736,6 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen2 ...@@ -736,7 +736,6 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen2
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen3 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen3
@1401200 @1401200
-ssts -ssts
@1000200
-ahci_ctrl_stat -ahci_ctrl_stat
@c00200 @c00200
-axi_ahci_regs -axi_ahci_regs
...@@ -796,9 +795,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0] ...@@ -796,9 +795,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0]
@28 @28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0] (0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0] (1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0]
@29
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0] (2)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_pre_act_w tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_pre_act_w
@1001200 @1001200
-group_end -group_end
...@@ -977,6 +974,58 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st ...@@ -977,6 +974,58 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
@1000200 @1000200
-ahci_fsm -ahci_fsm
@800200 @800200
-ahci_fis_receive
@200
-
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_first_vld
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.get_data_fis
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.get_dsfis
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.get_ignore
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.get_psfis
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.get_rfis
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.get_sdbfis
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.get_ufis
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.get_fis
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.get_fis_busy
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.get_fis_done
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.reg_addr_r[9:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_dcount[3:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_save
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.is_data_fis
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.reg_ps[4:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.wreg_we_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.dwords_over
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_rec_run
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.dma_in_ready
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.is_fis_end
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_end_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.data_in_ready
@800028
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_end_r[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_end_r[1:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_end_r[1:0]
@1001200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_ready
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_type[1:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_valid
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.dma_skipping_extra
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_first_flushing_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.dma_in_valid
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.dma_in
@1000200
-ahci_fis_receive
@c00200
-ahci_fis_transmit -ahci_fis_transmit
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.hba_rst tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.hba_rst
...@@ -1058,9 +1107,9 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.todev_data[31:0] ...@@ -1058,9 +1107,9 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.todev_data[31:0]
@1001200 @1001200
-group_end -group_end
-group_end -group_end
@1000200 @1401200
-ahci_fis_transmit -ahci_fis_transmit
@800200 @c00200
-ahci_sata_layers -ahci_sata_layers
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_ready tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_ready
...@@ -1096,7 +1145,6 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.rreg_full ...@@ -1096,7 +1145,6 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.rreg_full
- -
@1401200 @1401200
-fifo_h2d_control -fifo_h2d_control
@1000200
-ahci_sata_layers -ahci_sata_layers
@800200 @800200
-ahci_dma -ahci_dma
...@@ -1110,6 +1158,157 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.cmd_busy ...@@ -1110,6 +1158,157 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.cmd_busy
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_rd_busy tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_rd_busy
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.cmd_abort tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.cmd_abort
@200 @200
-
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.sys_in[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.sys_nfull
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.sys_we
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_wr
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.dev_wr_hclk
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rdata[63:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.wcount[21:1]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.wcount_set
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rvalid
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_rd
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_rd_busy
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.debug_01
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.debug_02
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.debug_03
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.is_prd_addr
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.is_data_addr
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.int_data_addr[3:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_ct_rq
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_ct_pend
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_data_rq
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_data_pend
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_prd_rq
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_prd_pend
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_raddr_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_raddr_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_raddr_ready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.is_ct_addr
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.is_data_addr
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.is_prd_addr
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wcount_many
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wcount[7:0]
@800200
-dma_d2h_fifo
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.init
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.init_confirm
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.en_fifo_rd
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.en_fifo_wr
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.hclk
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.wcnt[20:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.start
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.dout_av_many
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.dout[63:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.dout_we
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.busy
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty_mclk
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.din[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.din_rdy
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.din_avail
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.waddr[4:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_wr
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.is_last_prd
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.flushing
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.nfp[1:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.last_qword
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.flush_hclk
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.flush_mclk
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.hrst
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.hclk
@800022
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0]
@1001200
-group_end
@28
[color] 3
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.mclk
[color] 2
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_wr
@800022
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0]
@1001200
-group_end
@800022
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0]
@1001200
-group_end
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.waddr[4:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_half_mclk
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.raddr[3:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.mx0[1:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.mx1[2:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.mx2[2:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.mx3[2:0]
@200
-
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_out_ready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.dout_we_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.dout_av_many
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.axi_ready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.need_fifo
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_dav
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_dav2
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_rd_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_rd
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_rd_r
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.raddr[3:0]
@1000200
-dma_d2h_fifo
@200
----- -----
@22 @22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
...@@ -1158,7 +1357,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ct_data[31:0] ...@@ -1158,7 +1357,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ct_data[31:0]
@22 @22
tb_ahci.sysmem_dworda_rd[31:2] tb_ahci.sysmem_dworda_rd[31:2]
tb_ahci.afi_sim_rd_data[63:0] tb_ahci.afi_sim_rd_data[63:0]
@800200 @c00200
-top -top
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.hrst tb_ahci.dut.sata_top.ahci_top_i.hrst
...@@ -1167,7 +1366,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_raddr_ready ...@@ -1167,7 +1366,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_raddr_ready
tb_ahci.afi_sim_rd_ready tb_ahci.afi_sim_rd_ready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_raddr_r tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_raddr_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_raddr_w tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_raddr_w
@800200 @c00200
-simul_axi_hp_rd -simul_axi_hp_rd
-raddr_fifo -raddr_fifo
@28 @28
...@@ -1183,7 +1382,7 @@ tb_ahci.simul_axi_hp_rd_i.raddr_i.we ...@@ -1183,7 +1382,7 @@ tb_ahci.simul_axi_hp_rd_i.raddr_i.we
tb_ahci.simul_axi_hp_rd_i.raddr_i.next_fill[2:0] tb_ahci.simul_axi_hp_rd_i.raddr_i.next_fill[2:0]
@200 @200
- -
@1000200 @1401200
-raddr_fifo -raddr_fifo
@28 @28
tb_ahci.simul_axi_hp_rd_i.aclk tb_ahci.simul_axi_hp_rd_i.aclk
...@@ -1303,7 +1502,7 @@ tb_ahci.simul_axi_hp_rd_i.rvalid ...@@ -1303,7 +1502,7 @@ tb_ahci.simul_axi_hp_rd_i.rvalid
tb_ahci.MEM_SEL tb_ahci.MEM_SEL
@22 @22
tb_ahci.sysmem_dworda_rd[31:2] tb_ahci.sysmem_dworda_rd[31:2]
@800200 @c00200
-rdata_fifo -rdata_fifo
@28 @28
tb_ahci.simul_axi_hp_rd_i.rdata_i.wem tb_ahci.simul_axi_hp_rd_i.rdata_i.wem
...@@ -1315,7 +1514,7 @@ tb_ahci.simul_axi_hp_rd_i.rdata_i.ram_nempty ...@@ -1315,7 +1514,7 @@ tb_ahci.simul_axi_hp_rd_i.rdata_i.ram_nempty
tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full
@200 @200
- -
@1000200 @1401200
-rdata_fifo -rdata_fifo
-simul_axi_hp_rd -simul_axi_hp_rd
-top -top
...@@ -1454,8 +1653,12 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0] ...@@ -1454,8 +1653,12 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
@1401200 @1401200
-gtx8x10enc -gtx8x10enc
-gtx -gtx
@c00200 @800200
-device -device
@22
tb_ahci.dev.receive_id
tb_ahci.dev.receive_lock
tb_ahci.dev.receive_status
@28 @28
tb_ahci.dev.phy_ready tb_ahci.dev.phy_ready
@22 @22
...@@ -1473,7 +1676,6 @@ tb_ahci.dev.phy.ll_charisk_in[3:0] ...@@ -1473,7 +1676,6 @@ tb_ahci.dev.phy.ll_charisk_in[3:0]
- -
@1000200 @1000200
-dev_phy -dev_phy
@1401200
-device -device
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0
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