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x393_sata
Commit 6efdc1f7 authored by Andrey Filippov's avatar Andrey Filippov
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Updated with vdt, adding comments/debug features, implemented required support for CONTp primitive

parent 90a85abd
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.editor_defines
View file @ 6efdc1f7
`define IVERILOG 1
`include "system_defines.vh"
/*
//`define SIMULATION 1
`define CHECKERS_ENABLED 1
//`define OPEN_SOURCE_ONLY 1
`define PRELOAD_BRAMS
//`define IVERILOG 1
//`include "system_defines.vh"
*/
\ No newline at end of file
.project
View file @ 6efdc1f7
......@@ -46,87 +46,87 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20151222105615706.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20151227131114232.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20151221195334703.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20151227131114232.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20151221195334703.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20151227131114232.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20151221195334703.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20151227131114232.log</location>
</link>
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<name>vivado_logs/VivadoPlace.log</name>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20151221195334703.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20151227131114232.log</location>
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<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20151221195334703.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20151227131114232.log</location>
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<name>vivado_logs/VivadoSynthesis.log</name>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20151221195131644.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20151227130259322.log</location>
</link>
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<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20151221195334703.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20151227131114232.log</location>
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<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20151221195131644.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20151227130259322.log</location>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20151221201132195.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20151227131114232.log</location>
</link>
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<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20151221195131644.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20151227130259322.log</location>
</link>
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<name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20151221195334703.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20151227131114232.dcp</location>
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<name>vivado_state/x393_sata-opt-power.dcp</name>
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<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20151221195334703.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20151227131114232.dcp</location>
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<link>
<name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20151221195334703.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20151227131114232.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-place.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20151221195334703.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20151227131114232.dcp</location>
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<name>vivado_state/x393_sata-route.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20151221195334703.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20151227131114232.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20151221195131644.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20151227130259322.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 6efdc1f7
......@@ -3,9 +3,10 @@ VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_124_ConstraintsFiles=top.xdc<-@\#\#@->top_timing.xdc<-@\#\#@->
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_124_ConstraintsFiles<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.iverilog.prefs
View file @ 6efdc1f7
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_122_IVerilogOther<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_122_IVerilogOther<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_119_GTKWaveSavFile<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->iverilog_122_GrepFindErrWarn<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->
eclipse.preferences.version=1
iverilog_101_TopModulesOther=glbl<-@\#\#@->
iverilog_102_TopModulesOther=glbl<-@\#\#@->
iverilog_103_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_103_TopModulesOther=glbl<-@\#\#@->
iverilog_104_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_105_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_105_IncludeDir=${verilog_project_loc}/tb<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->
iverilog_106_IncludeDir=${verilog_project_loc}/tb<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->
iverilog_110_ShowNoProblem=true
iverilog_111_ShowNoProblem=true
iverilog_113_SaveLogsPreprocessor=true
iverilog_114_SaveLogsSimulator=true
iverilog_115_SaveLogsSimulator=true
iverilog_119_GTKWaveSavFile=tb_top_02.sav
iverilog_120_GTKWaveSavFile=tb_top_02.sav
iverilog_122_GrepFindErrWarn=error|warning|sorry
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
......
device/sata_device.v
View file @ 6efdc1f7
This diff is collapsed.
dma/dma_regs.v
View file @ 6efdc1f7
......@@ -39,6 +39,7 @@ module dma_regs(
input wire bram_ren,
input wire bram_regen,
// all registers sh_* outputs valid @ACLK
// tmp to cmd control
output wire cmd_val_out,
output wire [31:0] cmd_out,
......@@ -82,6 +83,7 @@ module dma_regs(
output wire sh_dir_val,
// inputs from sh registers
// No registers, just mux-ed (so @ACLK)
input wire sh_data_val_in,
input wire [31:0] sh_data_in,
input wire [7:0] sh_control_in,
......
dma/sata_top.v
View file @ 6efdc1f7
This diff is collapsed.
dma/top.v
View file @ 6efdc1f7
......@@ -23,7 +23,8 @@
* to make the final integration easier - just to make an instance of
* what is called now 'axi_regs' and connect it
*/
//`include "system_defines.vh"
// Including system defines at the top level can distinguish between simulation and synthesis?
`include "system_defines.vh"
//`include "sata_top.v"
module top #(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - partially used
......
host/command.v
View file @ 6efdc1f7
......@@ -255,6 +255,8 @@ always @ (posedge clk)
always @ (posedge clk)
raddr <= rst ? 10'b0 : al_sh_data_strobe_in ? raddr + 1'b1 : raddr;
// Application layer has different clock ?
ram_1kx32_1kx32 rbuf(
.rclk (clk), // clock for read port
.raddr (raddr), // read address
......
host/gtx_wrap.v
View file @ 6efdc1f7
......@@ -135,9 +135,9 @@ if (DATA_BYTE_WIDTH == 4) begin
reg [ 1:0] txcharisk_enc_in_r;
wire [38:0] txdata_resync_out;
wire txdata_resync_valid;
reg txcomwake_gtx_f;
reg txcominit_gtx_f;
reg txelecidle_gtx_f;
reg [1:0] txcomwake_gtx_f; // 2 registers just to match latency (data to the 3 next) in Alexey's code, probbaly not needed
reg [1:0] txcominit_gtx_f;
reg [1:0] txelecidle_gtx_f;
resync_data #( // TODO: update output register.. OK as it is
.DATA_WIDTH(39),
......@@ -156,7 +156,7 @@ if (DATA_BYTE_WIDTH == 4) begin
);
always @ (posedge txreset or posedge txusrclk) begin
if (txreset) txdata_resync_strobe <= 0;
else if (txdata_resync_valid) txdata_resync_strobe <= ~txdata_resync_strobe[0];
else if (txdata_resync_valid) txdata_resync_strobe <= ~txdata_resync_strobe;
if (txreset) begin
txdata_enc_in_r <= 0;
......@@ -169,18 +169,18 @@ if (DATA_BYTE_WIDTH == 4) begin
if (txreset) begin
txcomwake_gtx_f <= 0;
txcominit_gtx_f <= 0;
txelecidle_gtx_f <= 0;
txelecidle_gtx_f <= ~0;
end else begin
txcomwake_gtx_f <= txdata_resync_out[36];
txcominit_gtx_f <= txdata_resync_out[37];
txelecidle_gtx_f <= txdata_resync_out[38];
txcomwake_gtx_f <= {txdata_resync_out[36],txcomwake_gtx_f[1]};
txcominit_gtx_f <= {txdata_resync_out[37],txcominit_gtx_f[1]};
txelecidle_gtx_f <= {txdata_resync_out[38],txelecidle_gtx_f[1]};
end
end
assign txdata_enc_in = txdata_enc_in_r;
assign txcharisk_enc_in = txcharisk_enc_in_r;
assign txcominit_gtx = txcominit_gtx_f;
assign txcomwake_gtx = txcomwake_gtx_f;
assign txelecidle_gtx = txelecidle_gtx_f;
assign txcominit_gtx = txcominit_gtx_f[0];
assign txcomwake_gtx = txcomwake_gtx_f[0];
assign txelecidle_gtx = txelecidle_gtx_f[0];
/*wire txdata_resync_nempty;
......
host/link.v
View file @ 6efdc1f7
......@@ -100,16 +100,23 @@ module link #(
output wire [DATA_BYTE_WIDTH*8 - 1:0] phy_data_out,
output wire [DATA_BYTE_WIDTH - 1:0] phy_isk_out // charisk
);
`ifdef SIMULATION
reg [639:0] HOST_LINK_TITLE; // to show human-readable state in the GTKWave
reg [31:0] HOST_LINK_DATA;
`endif
// latching data-primitives stream from phy
reg [DATA_BYTE_WIDTH*8 - 1:0] phy_data_in_r;
reg [DATA_BYTE_WIDTH - 1:0] phy_isk_in_r; // charisk
reg [DATA_BYTE_WIDTH - 1:0] phy_err_in_r; // disperr | notintable
always @ (posedge clk)
begin
phy_data_in_r <= phy_data_in;
phy_isk_in_r <= phy_isk_in;
phy_err_in_r <= phy_err_in;
end
//one extra layer to process CONTp
reg [DATA_BYTE_WIDTH*8 - 1:0] phy_data_in_r0;
reg [DATA_BYTE_WIDTH - 1:0] phy_isk_in_r0; // charisk
reg [DATA_BYTE_WIDTH - 1:0] phy_err_in_r0; // disperr | notintable
reg [DATA_BYTE_WIDTH*8 - 1:0] last_not_cont_di; // last primitive dword, but not CONTp
reg rcv_junk; // receiving CONTp junk data
wire is_non_cont_p_w; // got primitive other than CONTp
wire is_cont_p_w; // got CONTp primitive
wire frame_done;
// scrambled data
......@@ -122,25 +129,48 @@ wire crc_bad;
wire [31:0] crc_dword;
// send primitives variety count, including CRC and DATA as primitives
localparam PRIM_NUM = 15;
localparam PRIM_NUM = 16; // 15;
wire [PRIM_NUM - 1:0] rcvd_dword; // shows current processing primitive (or just data dword)
wire dword_val;
// list of bits of rcvd_dword
localparam CODE_DATA = 0;
localparam CODE_CRC = 1;
localparam CODE_SYNCP = 2;
localparam CODE_ALIGNP = 3;
localparam CODE_XRDYP = 4;
localparam CODE_SOFP = 5;
localparam CODE_HOLDAP = 6;
localparam CODE_HOLDP = 7;
localparam CODE_EOFP = 8;
localparam CODE_WTRMP = 9;
localparam CODE_RRDYP = 10;
localparam CODE_IPP = 11;
localparam CODE_DMATP = 12;
localparam CODE_OKP = 13;
localparam CODE_ERRP = 14;
localparam CODE_DATA = 0; // DATA
localparam CODE_CRC = 1; // CRC
localparam CODE_SYNCP = 2; // SYNCp
localparam CODE_ALIGNP = 3; // ALIGNp PHY layer control
localparam CODE_XRDYP = 4; // X_RDYp Transmission data ready
localparam CODE_SOFP = 5; // SOFp Start of Frame
localparam CODE_HOLDAP = 6; // HOLDAp HOLD acknowledge
localparam CODE_HOLDP = 7; // HOLDp Hold data transmission
localparam CODE_EOFP = 8; // EOFp End Of Frame
localparam CODE_WTRMP = 9; // WTRMp Wait for frame termination
localparam CODE_RRDYP = 10; // R_RDYp Receiver ready
localparam CODE_IPP = 11; // R_IPp - Reception in progress
localparam CODE_DMATP = 12; // DMATp - DMA terminate
localparam CODE_OKP = 13; // R_OKp - Reception with no error
localparam CODE_ERRP = 14; // R_ERRp - Reception with Error
localparam CODE_CONTP = 15; // CONTp - Continue repeating
// processing CONTp/junk, delaying everything by 1 clock
always @ (posedge clk) begin
phy_data_in_r0 <= phy_data_in;
phy_isk_in_r0 <= phy_isk_in;
phy_err_in_r0 <= phy_err_in;
if (is_non_cont_p_w) last_not_cont_di <= phy_data_in_r0;
if (rst || is_non_cont_p_w) rcv_junk <= 0;
else if (is_cont_p_w) rcv_junk <= 1;
if (is_cont_p_w || (rcv_junk && !is_non_cont_p_w)) begin
phy_data_in_r <= last_not_cont_di;
phy_isk_in_r <= 1;
end else begin
phy_data_in_r <= phy_data_in_r0;
phy_isk_in_r <= phy_isk_in_r0;
end
phy_err_in_r <= phy_err_in_r0;
end
reg data_txing; // if there are still some data to transmit and the transaction wasn't cancelled
always @ (posedge clk)
......@@ -393,6 +423,9 @@ localparam [15:0] PRIM_OKP_HI = {3'd1, 5'd21, 3'd1, 5'd21};
localparam [15:0] PRIM_OKP_LO = {3'd5, 5'd21, 3'd3, 5'd28};
localparam [15:0] PRIM_ERRP_HI = {3'd2, 5'd22, 3'd2, 5'd22};
localparam [15:0] PRIM_ERRP_LO = {3'd5, 5'd21, 3'd3, 5'd28};
//The transmission of CONTp is optional, but the ability to receive and properly process CONTp is required.
localparam [15:0] PRIM_CONTP_HI = {3'd4, 5'd25, 3'd4, 5'd25};
localparam [15:0] PRIM_CONTP_LO = {3'd2, 5'd10, 3'd3, 5'd28};
wire [DATA_BYTE_WIDTH*8 - 1:0] prim_data [PRIM_NUM - 1:0];
......@@ -417,6 +450,7 @@ begin
assign prim_data[CODE_DMATP] [15:0] = prim_word ? PRIM_DMATP_HI : PRIM_DMATP_LO;
assign prim_data[CODE_OKP] [15:0] = prim_word ? PRIM_OKP_HI : PRIM_OKP_LO;
assign prim_data[CODE_ERRP] [15:0] = prim_word ? PRIM_ERRP_HI : PRIM_ERRP_LO;
assign prim_data[CODE_CONTP] [15:0] = prim_word ? PRIM_CONTP_HI : PRIM_CONTP_LO;
always @ (posedge clk)
begin
$display("%m: unsupported data width");
......@@ -441,6 +475,7 @@ begin
assign prim_data[CODE_DMATP] = {PRIM_DMATP_HI , PRIM_DMATP_LO};
assign prim_data[CODE_OKP] = {PRIM_OKP_HI , PRIM_OKP_LO};
assign prim_data[CODE_ERRP] = {PRIM_ERRP_HI , PRIM_ERRP_LO};
assign prim_data[CODE_CONTP] = {PRIM_CONTP_HI , PRIM_CONTP_LO};
end
else
begin
......@@ -469,6 +504,7 @@ assign select_prim[CODE_IPP] = ~alignes_pair & (state_rcvr_data & ~incom_
assign select_prim[CODE_DMATP] = ~alignes_pair & (state_rcvr_data & incom_stop_f | state_rcvr_shold & incom_stop_f);
assign select_prim[CODE_OKP] = ~alignes_pair & (state_rcvr_goodend);
assign select_prim[CODE_ERRP] = ~alignes_pair & (state_rcvr_badend);
// No sending of CONTp
// primitive selector MUX
always @ (posedge clk)
......@@ -584,6 +620,11 @@ assign rcvd_dword[CODE_DMATP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_B
assign rcvd_dword[CODE_OKP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_OKP ] == phy_data_in_r;
assign rcvd_dword[CODE_ERRP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_ERRP ] == phy_data_in_r;
// CONTp (*_r0 is one cycle ahead of *_r)
assign is_cont_p_w = phy_isk_in_r0[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_CONTP ] == phy_data_in_r0;
assign is_non_cont_p_w = phy_isk_in_r0[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_CONTP ] != phy_data_in_r0;
// phy level errors handling TODO
assign dec_err = |phy_err_in_r;
......@@ -664,7 +705,12 @@ always @ (posedge clk)
always @ (posedge clk)
begin
if (data_val_out) begin
$display("[Host] LINK: From device - received data = %h", data_out);
// $display("[Host] LINK: From device - received data = %h @%t", data_out, $time);
HOST_LINK_TITLE = "From device - received data";
HOST_LINK_DATA = data_out;
$display("[Host] LINK: %s = %h @%t", HOST_LINK_TITLE, HOST_LINK_DATA, $time);
`endif
end
// if (inc_is_data) begin
......
host/oob.v
View file @ 6efdc1f7
......@@ -106,6 +106,12 @@ module oob #(
`endif //OOB_MULTISPEED
);
`ifdef SIMULATION
reg [639:0] HOST_OOB_TITLE; // to show human-readable state in the GTKWave
`endif
// 873.8 us error timer
// = 2621400 SATA2 serial ticks (period = 0.000333 us)
// = 131070 ticks @ 150Mhz
......@@ -401,16 +407,20 @@ endgenerate
always @ (posedge clk)
begin
if (txcominit) begin
$display("[Host] OOB: Issued cominit");
HOST_OOB_TITLE = "Issued cominit";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end
if (txcomwake) begin
$display("[Host] OOB: Issued comwake");
HOST_OOB_TITLE = "Issued comwake";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end
if (state_wait_linkup) begin
$display("[Host] OOB: Link is up");
HOST_OOB_TITLE = "Link is up";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end
if (set_wait_synp) begin
$display("[Host] OOB: Started continious align sending");
HOST_OOB_TITLE = "Started continious align sending";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end
end
`endif
......
system_defines.vh
View file @ 6efdc1f7
......@@ -6,11 +6,16 @@
`ifdef IVERILOG
`define SIMULATION
`define OPEN_SOURCE_ONLY
`define CHECKERS_ENABLED 1
`else
`ifdef CVC
`define SIMULATION
`define OPEN_SOURCE_ONLY
`define CHECKERS_ENABLED 1
`else
`undef OPEN_SOURCE_ONLY
`endif // CVC
`endif // IVERILOG
// will not use simultaneous reset in shift registers, just and input data with ~rst
......
tb/tb_top.v
View file @ 6efdc1f7
......@@ -19,6 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// global defines
`define IVERILOG
`define SIMULATION
`define OPEN_SOURCE_ONLY
`define PRELOAD_BRAMS
......@@ -55,6 +56,9 @@ module tb #(
`endif // CVC
`endif // IVERILOG
reg [639:0] TESTBENCH_TITLE; // to show human-readable state in the GTKWave
reg [31:0] TESTBENCH_DATA;
reg [11:0] TESTBENCH_ID;
initial #1 $display("HI THERE");
......@@ -618,12 +622,21 @@ task maxiMonitorPush;
begin
if (maxi_monitor_raddr == (maxi_monitor_waddr + 1)) begin
$display("[Testbench] maxiMonitorPush: trying to push to a full fifo");
TESTBENCH_TITLE = "trying to push to a full fifo";
$display("[Testbench] maxiMonitorPush %s = %h, id = %h @%t", TESTBENCH_TITLE, $time);
$finish;
end
maxi_monitor_fifo[maxi_monitor_waddr][31:0] = data;
maxi_monitor_fifo[maxi_monitor_waddr][43:32] = id;
maxi_monitor_fifo_empty = 1'b0;
$display("[Testbench] MAXI: Got data = %h, id = %h", data, id);
// $display("[Testbench] MAXI: Got data = %h, id = %h", data, id);
TESTBENCH_TITLE = "Got data";
TESTBENCH_DATA = data;
TESTBENCH_ID = id;
$display("[Testbench] MAXI %s = %h, id = %h @%t", TESTBENCH_TITLE, TESTBENCH_DATA, TESTBENCH_ID, $time);
//[Testbench] MAXI: %
maxi_monitor_waddr = (maxi_monitor_waddr + 1) % maxi_monitor_fifo_size;
end
endtask
......@@ -637,6 +650,8 @@ initial forever @ (posedge CLK) begin
end
// testing itself
`include "test_top.v" // SuppressThisWarning VEditor - to avoid strange warnings
`include "test_top.v" // S uppressThisWarning VEditor - to avoid strange warnings
endmodule
//`include "x393/glbl.v" // SuppressThisWarning VEditor - duplicate module
tb/test_top.v
View file @ 6efdc1f7
......@@ -21,6 +21,7 @@
/*
* this file is included into tb_top.v due to the compatibility with x393 design testbench
*/
reg [639:0] TEST_TITLE; // to show human-readable state in the GTKWave
// external clock to gtx
......@@ -81,7 +82,10 @@ begin
axi_write_single({30'h5, 2'b00}, 32'hEC);
// start!
axi_write_single({30'hf, 2'b00}, 32'h0108);
$display("[Test] H2D Reg with pio cmd issued");
// $display("[Test]: H2D Reg with pio cmd issued");
TEST_TITLE = "H2D Reg with pio cmd issued";
$display("[Test]: %s @%t", TEST_TITLE, $time);
// wait until reception
while (dev.receive_id != 1) begin
repeat (100)
......@@ -89,11 +93,15 @@ begin
end
if (dev.receive_status != 0) begin
$display("[Test] Failed");
// $display("[Test]: Failed 1");
TEST_TITLE = "Failed #1";
$display("[Test]: %s @%t", TEST_TITLE, $time);
$finish;
end
$display("[Test] H2D Reg with pio cmd received by dev");
// $display("[Test]: H2D Reg with pio cmd received by dev");
TEST_TITLE = "H2D Reg with pio cmd received by dev";
$display("[Test]: %s @%t", TEST_TITLE, $time);
// send dev2host reg fis with BSY flag
repeat (100)
@ (posedge dev.clk);
......@@ -108,17 +116,23 @@ begin
dev.linkTransmitFIS(66, 5, 0, status);
if (status != 0) begin
$display("[Test] Failed");
// $display("[Test]: Failed 2");
TEST_TITLE = "Failed #2";
$display("[Test]: %s @%t", TEST_TITLE, $time);
$finish;
end
$display("[Test] Dev sent BSY flag");
// $display("[Test]: Dev sent BSY flag");
TEST_TITLE = "Dev sent BSY flag";
$display("[Test]: %s @%t", TEST_TITLE, $time);
// checks if BSY is set up // only on waves TODO
axi_read_addr(12'h555, {30'h11, 2'b00}, 4'h3, 2'b01);
repeat (50)
@ (posedge dev.clk);
$display("[Test] Device sends PIO Setup");
// $display("[Test]: Device sends PIO Setup");
TEST_TITLE = "Device sends PIO Setup";
$display("[Test]: %s @%t", TEST_TITLE, $time);
dev.transmit_data[0] = 32'h0080205f; // direction d2h, type = 5f
dev.transmit_data[1] = 32'hdeadbeef; // whatever
dev.transmit_data[2] = 32'hdeadbeef; // whatever
......@@ -126,11 +140,15 @@ begin
dev.transmit_data[4] = 32'h00000014; // let it be 20 bytes to be transfered
dev.linkTransmitFIS(11, 5, 0, status);
if (status != 0) begin
$display("[Test] Failed");
// $display("[Test]: Failed 3");
TEST_TITLE = "Failed #3";
$display("[Test]: %s @%t", TEST_TITLE, $time);
$finish;
end
$display("[Test] Device sends data FIS");
// $display("[Test]: Device sends data FIS");
TEST_TITLE = "Device sends data FIS";
$display("[Test]: %s @%t", TEST_TITLE, $time);
dev.transmit_data[0] = 32'h00000046; // type = 46
dev.transmit_data[1] = 32'hfeeddeaf;
dev.transmit_data[2] = 32'ha114bea7;
......@@ -139,7 +157,10 @@ begin
dev.transmit_data[5] = 32'hdeadbeef;
dev.linkTransmitFIS(22, 6, 0, status);
if (status != 0) begin
$display("[Test] Failed");
// $display("[Test]: Failed 4");
TEST_TITLE = "Failed #4";
$display("[Test]: %s @%t", TEST_TITLE, $time);
$finish;
end
......@@ -152,19 +173,30 @@ begin
end
// imitating PIO reads
$display("[Test] Read data word 0");
// $display("[Test]: Read data word 0");
TEST_TITLE = "Read data word 0";
$display("[Test]: %s @%t", TEST_TITLE, $time);
axi_read_addr(12'h660, {30'h00, 2'b00}, 4'h0, 2'b01);
$display("[Test] Read data word 1");
// $display("[Test]: Read data word 1");
TEST_TITLE = "Read data word 1";
$display("[Test]: %s @%t", TEST_TITLE, $time);
axi_read_addr(12'h661, {30'h00, 2'b00}, 4'h0, 2'b01);
$display("[Test] Read data word 2");
// $display("[Test]: Read data word 2");
TEST_TITLE = "Read data word 2";
$display("[Test]: %s @%t", TEST_TITLE, $time);
axi_read_addr(12'h662, {30'h00, 2'b00}, 4'h0, 2'b01);
$display("[Test] Read data word 3");
// $display("[Test]: Read data word 3");
TEST_TITLE = "Read data word 3";
$display("[Test]: %s @%t", TEST_TITLE, $time);
axi_read_addr(12'h663, {30'h00, 2'b00}, 4'h0, 2'b01);
$display("[Test] Read data word 4");
// $display("[Test]: Read data word 4");
TEST_TITLE = "Read data word 4";
$display("[Test]: %s @%t", TEST_TITLE, $time);
axi_read_addr(12'h664, {30'h00, 2'b00}, 4'h0, 2'b01);
// check if all ok
......@@ -172,12 +204,18 @@ begin
while (~maxiMonitorIsEmpty(0)) begin
maxiMonitorPop(data, id);
if (dev.transmit_data[i] != data) begin
$display("[Test] Data check failed");
// $display("[Test]: Data check failed");
TEST_TITLE = "Data check failed";
$display("[Test]: %s @%t", TEST_TITLE, $time);
$finish;
end
i = i + 1;
end
$display("[Test] Data check OK");
// $display("[Test]: Data check OK");
TEST_TITLE = "Data check OK";
$display("[Test]: %s @%t", TEST_TITLE, $time);
......@@ -188,6 +226,7 @@ begin
$display("data received : %h", dev.receive_data[i]);
end*/
$display("============= DONE =============");
TEST_TITLE = "DONE";
$finish;
// test SAXI3 iface
......@@ -241,7 +280,10 @@ end
*/
initial begin
#150000;
$display("[Test] Failed");
// $display("[Test]: Failed");
TEST_TITLE = "Failed (timelimit)";
$display("[Test]: %s @%t", TEST_TITLE, $time);
$display("============= TIMELIMIT =============");
$finish;
end
wrapper/gtxe2_channel_wrapper.v
View file @ 6efdc1f7
......@@ -18,6 +18,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "system_defines.vh"
module gtxe2_channel_wrapper(
// clocking ports, UG476 p.37
input [2:0] CPLLREFCLKSEL,
......
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