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Commit 6efdc1f7 authored by Andrey Filippov's avatar Andrey Filippov
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Updated with vdt, adding comments/debug features, implemented required support for CONTp primitive

parent 90a85abd
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.editor_defines
View file @ 6efdc1f7
`define IVERILOG 1
`include "system_defines.vh"
/*
//`define SIMULATION 1 //`define SIMULATION 1
`define CHECKERS_ENABLED 1 `define CHECKERS_ENABLED 1
//`define OPEN_SOURCE_ONLY 1 //`define OPEN_SOURCE_ONLY 1
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
//`define IVERILOG 1 //`define IVERILOG 1
//`include "system_defines.vh" //`include "system_defines.vh"
*/
\ No newline at end of file
.project
View file @ 6efdc1f7
...@@ -46,87 +46,87 @@ ...@@ -46,87 +46,87 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20151222105615706.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20151227131114232.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20151221195334703.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20151227131114232.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20151221195334703.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20151227131114232.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20151221195334703.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20151227131114232.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20151221195334703.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20151227131114232.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20151221195334703.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20151227131114232.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20151221195131644.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20151227130259322.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20151221195334703.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20151227131114232.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20151221195131644.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20151227130259322.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20151221201132195.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20151227131114232.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20151221195131644.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20151227130259322.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-phys.dcp</name> <name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20151221195334703.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20151227131114232.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-power.dcp</name> <name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20151221195334703.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20151227131114232.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt.dcp</name> <name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20151221195334703.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20151227131114232.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-place.dcp</name> <name>vivado_state/x393_sata-place.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20151221195334703.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20151227131114232.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-route.dcp</name> <name>vivado_state/x393_sata-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20151221195334703.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20151227131114232.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-synth.dcp</name> <name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20151221195131644.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20151227130259322.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 6efdc1f7
...@@ -3,9 +3,10 @@ VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@-> ...@@ -3,9 +3,10 @@ VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@-> VivadoSynthesis_121_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@-> VivadoSynthesis_122_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_124_ConstraintsFiles=top.xdc<-@\#\#@->top_timing.xdc<-@\#\#@->
VivadoSynthesis_127_verbose=true VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1 VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@-> VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=false VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@-> com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_124_ConstraintsFiles<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.iverilog.prefs
View file @ 6efdc1f7
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_122_IVerilogOther<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@-> com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_122_IVerilogOther<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_119_GTKWaveSavFile<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->iverilog_122_GrepFindErrWarn<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
iverilog_101_TopModulesOther=glbl<-@\#\#@-> iverilog_101_TopModulesOther=glbl<-@\#\#@->
iverilog_102_TopModulesOther=glbl<-@\#\#@-> iverilog_102_TopModulesOther=glbl<-@\#\#@->
iverilog_103_ExtraFiles=x393/glbl.v<-@\#\#@-> iverilog_103_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_103_TopModulesOther=glbl<-@\#\#@->
iverilog_104_ExtraFiles=x393/glbl.v<-@\#\#@-> iverilog_104_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@-> iverilog_104_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_105_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_105_IncludeDir=${verilog_project_loc}/tb<-@\#\#@->${verilog_project_loc}/host<-@\#\#@-> iverilog_105_IncludeDir=${verilog_project_loc}/tb<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->
iverilog_106_IncludeDir=${verilog_project_loc}/tb<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->
iverilog_110_ShowNoProblem=true iverilog_110_ShowNoProblem=true
iverilog_111_ShowNoProblem=true
iverilog_113_SaveLogsPreprocessor=true iverilog_113_SaveLogsPreprocessor=true
iverilog_114_SaveLogsSimulator=true iverilog_114_SaveLogsSimulator=true
iverilog_115_SaveLogsSimulator=true
iverilog_119_GTKWaveSavFile=tb_top_02.sav
iverilog_120_GTKWaveSavFile=tb_top_02.sav
iverilog_122_GrepFindErrWarn=error|warning|sorry
iverilog_77_Param_Exe=/usr/local/bin/iverilog iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
......
device/sata_device.v
View file @ 6efdc1f7
...@@ -28,6 +28,11 @@ module sata_device( ...@@ -28,6 +28,11 @@ module sata_device(
input wire EXTCLK_P, input wire EXTCLK_P,
input wire EXTCLK_N input wire EXTCLK_N
); );
//`ifdef SIMULATION
reg [639:0] DEV_TITLE; // to show human-readable state in the GTKWave
// reg [31:0] DEV_DATA;
integer DEV_DATA;
//`endif
wire phy_ready; wire phy_ready;
...@@ -130,7 +135,7 @@ initial forever @ (posedge clk) begin ...@@ -130,7 +135,7 @@ initial forever @ (posedge clk) begin
end end
end end
function [31:0] scrambleFunc; function [31:0] scrambleFunc; //SuppressThisWarning VEditor: VDT bug? it is used
input [31:0] context; input [31:0] context;
reg [31:0] next; reg [31:0] next;
reg [15:0] now; reg [15:0] now;
...@@ -175,7 +180,7 @@ function [31:0] scrambleFunc; ...@@ -175,7 +180,7 @@ function [31:0] scrambleFunc;
end end
endfunction endfunction
function [31:0] calculateCRC; function [31:0] calculateCRC; //SuppressThisWarning VEditor VDT bug, it is used
input [31:0] seed; input [31:0] seed;
input [31:0] data; input [31:0] data;
reg [31:0] crc_bit; reg [31:0] crc_bit;
...@@ -265,10 +270,13 @@ function [31:0] calculateCRC; ...@@ -265,10 +270,13 @@ function [31:0] calculateCRC;
endfunction endfunction
// stub TODO // stub TODO
function tranCheckFIS; function tranCheckFIS; //SuppressThisWarning VEditor: VDT bug - the function is used in conditional expression
input count; input count;
begin begin
$display("[Device] TRANSPORT: Says the FIS is valid"); // $display("[Device] TRANSPORT: Says the FIS is valid");
DEV_TITLE = "Says the FIS is valid";
$display("[Device] TRANSPORT: %s @%t", DEV_TITLE, $time);
tranCheckFIS = 0; // always tell LL the FIS os OK tranCheckFIS = 0; // always tell LL the FIS os OK
end end
endfunction endfunction
...@@ -319,16 +327,24 @@ task linkMonitorFIS; ...@@ -319,16 +327,24 @@ task linkMonitorFIS;
cnt = 0; cnt = 0;
// current rprim = XRDY // current rprim = XRDY
rprim = "XRDY"; rprim = "XRDY";
$display("[Device] LINK: Detected incoming transmission"); DEV_TITLE = "Detected incoming transmission";
$display("[Device] LINK: Waiting %h cycles to empty input buffer", pause); $display("[Device] LINK: %s @%t", DEV_TITLE, $time);
DEV_TITLE = "Waiting to empty input buffer";
DEV_DATA = pause;
// $display("[Device] LINK: Waiting %h cycles to empty input buffer", pause);
$display("[Device] LINK: %s, pause = %d @%t", DEV_TITLE, DEV_DATA, $time);
while (pause > 0) begin while (pause > 0) begin
// L_RcvWaitFifo // L_RcvWaitFifo
if (~phy_ready) begin if (~phy_ready) begin
$display("[Device] LINK: Unexpected line disconnect"); DEV_TITLE = "Unexpected line disconnect #1";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
$finish; $finish;
end end
if (rprim != "XRDY") begin if (rprim != "XRDY") begin
$display("[Device] LINK: Reception terminated by the host, reception id = %d", id); // $display("[Device] LINK: Reception terminated by the host, reception id = %d", id);
DEV_TITLE = "Reception terminated by the host #1";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
$finish; $finish;
end end
@ (posedge clk) @ (posedge clk)
...@@ -336,24 +352,37 @@ task linkMonitorFIS; ...@@ -336,24 +352,37 @@ task linkMonitorFIS;
end end
// L_RcvChkRdy // L_RcvChkRdy
if (~phy_ready) begin if (~phy_ready) begin
$display("[Device] LINK: Unexpected line disconnect"); // $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #2";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
$finish; $finish;
end end
if (rprim != "XRDY") begin if (rprim != "XRDY") begin
$display("[Device] LINK: Reception terminated by the host, reception id = %d", id); // $display("[Device] LINK: Reception terminated by the host, reception id = %d", id);
DEV_TITLE = "Reception terminated by the host #2";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
$finish; $finish;
end end
linkSendPrim("RRDY"); linkSendPrim("RRDY");
$display("[Device] LINK: Starting the reception"); // $display("[Device] LINK: Starting the reception");
DEV_TITLE = "Starting the reception";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
@ (posedge clk) @ (posedge clk)
rprim = linkGetPrim(0); rprim = linkGetPrim(0);
while (rprim != "SOF") begin while (rprim != "SOF") begin
if (~phy_ready) begin if (~phy_ready) begin
$display("[Device] LINK: Unexpected line disconnect"); // $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #3";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
$finish; $finish;
end end
if (rprim != "XRDY") begin if (rprim != "XRDY") begin
$display("[Device] LINK: Reception terminated by the host, reception id = %d", id); // $display("[Device] LINK: Reception terminated by the host, reception id = %d", id);
DEV_TITLE = "Reception terminated by the host #3";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
$finish; $finish;
end end
@ (posedge clk) @ (posedge clk)
...@@ -361,29 +390,44 @@ task linkMonitorFIS; ...@@ -361,29 +390,44 @@ task linkMonitorFIS;
end end
// L_RcvData // L_RcvData
if (~phy_ready) begin if (~phy_ready) begin
$display("[Device] LINK: Unexpected line disconnect"); // $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #4";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
$finish; $finish;
end end
$display("[Device] LINK: Detected Start of FIS"); // $display("[Device] LINK: Detected Start of FIS");
DEV_TITLE = "Detected Start of FIS";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
linkSendPrim("IP"); linkSendPrim("IP");
@ (posedge clk) @ (posedge clk)
rprim = linkGetPrim(0); rprim = linkGetPrim(0);
pause = 0; pause = 0;
while (rcv_stop == 0) begin while (rcv_stop == 0) begin
if (~phy_ready) begin if (~phy_ready) begin
$display("[Device] LINK: Unexpected line disconnect"); // $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #5";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
$finish; $finish;
end end
if (rprim == "SYNC") begin if (rprim == "SYNC") begin
$display("[Device] LINK: Reception terminated by the host, reception id = %d", id); // $display("[Device] LINK: Reception terminated by the host, reception id = %d", id);
DEV_TITLE = "Reception terminated by the host #4";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
$finish; $finish;
end end
if (rprim == "SCRAP") begin if (rprim == "SCRAP") begin
$display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, reception id = %d", linkIsData(0), linkGetData(0), id); // $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, reception id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #1";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
$finish; $finish;
end end
if (rprim == "EOF") begin if (rprim == "EOF") begin
$display("[Device] LINK: Detected End of FIS"); // $display("[Device] LINK: Detected End of FIS");
DEV_TITLE = "Detected End of FIS";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
rcv_stop = 1; rcv_stop = 1;
end end
else else
...@@ -391,17 +435,23 @@ task linkMonitorFIS; ...@@ -391,17 +435,23 @@ task linkMonitorFIS;
pause = pause - 1; pause = pause - 1;
linkSendPrim("HOLD"); linkSendPrim("HOLD");
if (rprim == "HOLDA") begin if (rprim == "HOLDA") begin
$display("[Device] LINK: The pause is acknowledged by the host, chilling out"); // $display("[Device] LINK: The pause is acknowledged by the host, chilling out");
DEV_TITLE = "The pause is acknowledged by the host, chilling out";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
rcv_ignore = 1; rcv_ignore = 1;
end end
else begin else begin
$display("[Device] LINK: Asked for a pause"); // $display("[Device] LINK: Asked for a pause");
DEV_TITLE = "Asked for a pause";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
rcv_ignore = 0; rcv_ignore = 0;
end end
end end
else else
if (rprim == "HOLD") begin if (rprim == "HOLD") begin
$display("[Device] LINK: the host asked for a pause, acknowledging"); // $display("[Device] LINK: the host asked for a pause, acknowledging");
DEV_TITLE = "the host asked for a pause, acknowledging";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
linkSendPrim("HOLDA"); linkSendPrim("HOLDA");
rcv_ignore = 1; rcv_ignore = 1;
end end
...@@ -410,20 +460,31 @@ task linkMonitorFIS; ...@@ -410,20 +460,31 @@ task linkMonitorFIS;
rcv_ignore = 0; rcv_ignore = 0;
end end
if (rprim == "WTRM") begin if (rprim == "WTRM") begin
$display("[Device] LINK: Host invalidated the reception, reception id = %d", id); // $display("[Device] LINK: Host invalidated the reception, reception id = %d", id);
DEV_TITLE = "Host invalidated the reception";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
rcv_stop = 2; rcv_stop = 2;
end end
if ((rcv_stop == 0) && (rcv_ignore == 0)) begin if ((rcv_stop == 0) && (rcv_ignore == 0)) begin
if (cnt > 2048) begin if (cnt > 2048) begin
$display("[Device] LINK: Wrong data dwords count received, reception id = %d", id); // $display("[Device] LINK: Wrong data dwords count received, reception id = %d", id);
DEV_TITLE = "Wrong data dwords count received";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
$finish; $finish;
end end
if (cnt >= dmat_index) begin if (cnt >= dmat_index) begin
linkSendPrim("DMAT"); linkSendPrim("DMAT");
end end
scrambler_value = scrambleFunc(scrambler_value[31:16]); // scrambler_value = scrambleFunc(scrambler_value[31:16]);
scrambler_value = scrambleFunc({16'b0,scrambler_value[31:16]});
receive_data[cnt] = linkGetData(0) ^ scrambler_value; receive_data[cnt] = linkGetData(0) ^ scrambler_value;
$display("[Device] LINK: Got data = %h", receive_data[cnt]); // $display("[Device] LINK: Got data = %h", receive_data[cnt]);
DEV_TITLE = "Got data";
DEV_DATA = receive_data[cnt];
$display("[Device] LINK: %s = %d @%t", DEV_TITLE, DEV_DATA, $time);
pause = pause + receive_data_pause[cnt]; pause = pause + receive_data_pause[cnt];
crc = calculateCRC(crc, receive_data[cnt]); // running crc. shall be 0 crc = calculateCRC(crc, receive_data[cnt]); // running crc. shall be 0
cnt = cnt + 1; cnt = cnt + 1;
...@@ -434,44 +495,72 @@ task linkMonitorFIS; ...@@ -434,44 +495,72 @@ task linkMonitorFIS;
rprim = linkGetPrim(0); rprim = linkGetPrim(0);
end end
if (cnt < 2) begin if (cnt < 2) begin
$display("[Device] LINK: Incorrect number of received words"); // $display("[Device] LINK: Incorrect number of received words");
DEV_TITLE = "Incorrect number of received words";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
$finish; $finish;
end end
$display("[Device] LINK: Running CRC after all data was received = %h", crc); // $display("[Device] LINK: Running CRC after all data was received = %h", crc);
DEV_TITLE = "Running CRC after all data was received";
DEV_DATA = crc;
$display("[Device] LINK: %s = %h @%t", DEV_TITLE, DEV_DATA, $time);
if (crc != 32'h88c21025) begin // running disparity when data crc matches actual received crc if (crc != 32'h88c21025) begin // running disparity when data crc matches actual received crc
$display("[Device] LINK: Running CRC check failed"); // $display("[Device] LINK: Running CRC check failed");
DEV_TITLE = "Running CRC check failed";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
rcv_stop = 2; rcv_stop = 2;
end end
else begin else begin
$display("[Device] LINK: Running CRC OK"); // $display("[Device] LINK: Running CRC OK");
DEV_TITLE = "Running CRC OK";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
end end
if (rcv_stop == 1) begin // ordinary path if (rcv_stop == 1) begin // ordinary path
// L_RcvEOF // L_RcvEOF
if (~phy_ready) begin if (~phy_ready) begin
$display("[Device] LINK: Unexpected line disconnect"); // $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #6";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
$finish; $finish;
end end
if (rprim == "SYNC") begin if (rprim == "SYNC") begin
$display("[Device] LINK: Reception terminated by the host, reception id = %d", id); // $display("[Device] LINK: Reception terminated by the host, reception id = %d", id);
DEV_TITLE = "Reception terminated by the host #5";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
$finish; $finish;
end end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin if ((rprim == "SCRAP") || (rprim == "DATA")) begin
$display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, reception id = %d", linkIsData(0), linkGetData(0), id); // $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, reception id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #2";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
$finish; $finish;
end end
@ (posedge clk) @ (posedge clk)
rprim = linkGetPrim(0); rprim = linkGetPrim(0);
// L_GoodCRC // L_GoodCRC
if (~phy_ready) begin if (~phy_ready) begin
$display("[Device] LINK: Unexpected line disconnect"); // $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #7";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
$finish; $finish;
end end
if (rprim == "SYNC") begin if (rprim == "SYNC") begin
$display("[Device] LINK: Reception terminated by the host, reception id = %d", id); // $display("[Device] LINK: Reception terminated by the host, reception id = %d", id);
DEV_TITLE = "Reception terminated by the host #6";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
$finish; $finish;
end end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin if ((rprim == "SCRAP") || (rprim == "DATA")) begin
$display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, reception id = %d", linkIsData(0), linkGetData(0), id); // $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, reception id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #3";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
$finish; $finish;
end end
if (tranCheckFIS(cnt - 1)) begin if (tranCheckFIS(cnt - 1)) begin
...@@ -482,7 +571,10 @@ task linkMonitorFIS; ...@@ -482,7 +571,10 @@ task linkMonitorFIS;
// L_BadEnd // L_BadEnd
status = 1; status = 1;
linkSendPrim("ERR"); linkSendPrim("ERR");
$display("[Device] LINK: Found an error"); // $display("[Device] LINK: Found an error");
DEV_TITLE = "Found an error";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
end end
else begin else begin
// L_GoodEnd // L_GoodEnd
...@@ -493,11 +585,16 @@ task linkMonitorFIS; ...@@ -493,11 +585,16 @@ task linkMonitorFIS;
rprim = linkGetPrim(0); rprim = linkGetPrim(0);
while (rprim != "SYNC") begin while (rprim != "SYNC") begin
if (~phy_ready) begin if (~phy_ready) begin
$display("[Device] LINK: Unexpected line disconnect"); // $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #8";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
$finish; $finish;
end end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin if ((rprim == "SCRAP") || (rprim == "DATA")) begin
$display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, reception id = %d", linkIsData(0), linkGetData(0), id); // $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, reception id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #4";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
$finish; $finish;
end end
@ (posedge clk) @ (posedge clk)
...@@ -506,11 +603,18 @@ task linkMonitorFIS; ...@@ -506,11 +603,18 @@ task linkMonitorFIS;
// L_IDLE // L_IDLE
linkSendPrim("SYNC"); linkSendPrim("SYNC");
if (status == 1) begin if (status == 1) begin
$display("[Device] LINK: Reception done, errors detected, reception id = %d", id); // $display("[Device] LINK: Reception done, errors detected, reception id = %d", id);
DEV_TITLE = "Reception done, errors detected";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
end end
else else
if (status == 0) begin if (status == 0) begin
$display("[Device] LINK: Reception done OK, reception id = %d", id); // $display("[Device] LINK: Reception done OK, reception id = %d", id);
DEV_TITLE = "Reception done OK";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
end end
end end
endtask endtask
...@@ -519,7 +623,7 @@ endtask ...@@ -519,7 +623,7 @@ endtask
reg [31:0] transmit_data [2047:0]; reg [31:0] transmit_data [2047:0];
reg [31:0] transmit_data_pause [2047:0]; reg [31:0] transmit_data_pause [2047:0];
reg [31:0] transmit_crc; reg [31:0] transmit_crc; // never assigned
/* /*
* Transmits data to a host. ~Link Transmit FSM * Transmits data to a host. ~Link Transmit FSM
* Correct execution, as it shall be w/o errors from a device side. (except timeouts and data consistency, see below) * Correct execution, as it shall be w/o errors from a device side. (except timeouts and data consistency, see below)
...@@ -561,12 +665,19 @@ task linkTransmitFIS; ...@@ -561,12 +665,19 @@ task linkTransmitFIS;
transmit_lock = 1; transmit_lock = 1;
// DL_SendChkRdy // DL_SendChkRdy
linkSendPrim("XRDY"); linkSendPrim("XRDY");
$display("[Device] LINK: Started outcoming transmission"); // $display("[Device] LINK: Started outcoming transmission");
DEV_TITLE = "Started outcoming transmission";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
rprim = linkGetPrim(0); rprim = linkGetPrim(0);
$display("[Device] LINK: Waiting for acknowledgement"); // $display("[Device] LINK: Waiting for acknowledgement");
DEV_TITLE = "Waiting for acknowledgement";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
while (rprim != "RRDY") begin while (rprim != "RRDY") begin
if (~phy_ready) begin if (~phy_ready) begin
$display("[Device] LINK: Unexpected line disconnect"); // $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #9";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
$finish; $finish;
end end
@ (posedge clk) @ (posedge clk)
...@@ -574,54 +685,81 @@ task linkTransmitFIS; ...@@ -574,54 +685,81 @@ task linkTransmitFIS;
end end
// L_SendSOF // L_SendSOF
linkSendPrim("SOF"); linkSendPrim("SOF");
$display("[Device] LINK: Sending Start of FIS"); // $display("[Device] LINK: Sending Start of FIS");
DEV_TITLE = "Sending Start of FIS";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
@ (posedge clk) @ (posedge clk)
rprim = linkGetPrim(0); rprim = linkGetPrim(0);
if (~phy_ready) begin if (~phy_ready) begin
$display("[Device] LINK: Unexpected line disconnect"); // $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #10";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
$finish; $finish;
end end
if (rprim == "SYNC") begin if (rprim == "SYNC") begin
$display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id); // $display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id);
DEV_TITLE = "Transmission terminated by the host #1";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
$finish; $finish;
end end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin if ((rprim == "SCRAP") || (rprim == "DATA")) begin
$display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id); // $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #5";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
$finish; $finish;
end end
// L_SendData + L_RcvrHold + L_SendHold // L_SendData + L_RcvrHold + L_SendHold
cnt = 0; cnt = 0;
pause = transmit_data_pause[0]; pause = transmit_data_pause[0];
while (cnt < size) begin while (cnt < size) begin
scrambler_value = scrambleFunc(scrambler_value[31:16]); // scrambler_value = scrambleFunc(scrambler_value[31:16]);
// $display("[Device] LINK: Scrambler = %h", scrambler_value); scrambler_value = scrambleFunc({16'b0,scrambler_value[31:16]});
// $display("[Device] LINK: Scrambler = %h", scrambler_value);
linkSendData(transmit_data[cnt] ^ scrambler_value); linkSendData(transmit_data[cnt] ^ scrambler_value);
crc = calculateCRC(crc, transmit_data[cnt]); crc = calculateCRC(crc, transmit_data[cnt]);
$display("[Device] LINK: Sent data = %h", transmit_data[cnt]); // $display("[Device] LINK: Sent data = %h", transmit_data[cnt]);
DEV_TITLE = "Sent data";
DEV_DATA = transmit_data[cnt];
$display("[Device] LINK: %s = %h @%t", DEV_TITLE, DEV_DATA, $time);
@ (posedge clk) @ (posedge clk)
rprim = linkGetPrim(0); rprim = linkGetPrim(0);
if (rprim == "SYNC") begin if (rprim == "SYNC") begin
$display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id); // $display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id);
DEV_TITLE = "Transmission terminated by the host #2";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
$finish; $finish;
end end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin if ((rprim == "SCRAP") || (rprim == "DATA")) begin
$display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id); // $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #6";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
$finish; $finish;
end end
else else
if (rprim == "DMAT") begin if (rprim == "DMAT") begin
$display("[Device] LINK: Transmission terminated by the host via DMAT, transmission id = %d", id); // $display("[Device] LINK: Transmission terminated by the host via DMAT, transmission id = %d", id);
DEV_TITLE = "Transmission terminated by the hostvia DMAT";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
$finish; $finish;
end end
else else
if (pause > 0) begin if (pause > 0) begin
$display("[Device] LINK: Transmission is paused"); // $display("[Device] LINK: Transmission is paused");
DEV_TITLE = "Transmission is paused";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
linkSendPrim("HOLD"); linkSendPrim("HOLD");
pause = pause - 1; pause = pause - 1;
end end
else else
if (rprim == "HOLD") begin if (rprim == "HOLD") begin
$display("[Device] LINK: The host asked for a pause, acknowledging"); // $display("[Device] LINK: The host asked for a pause, acknowledging");
DEV_TITLE = "The host asked for a pause, acknowledging transmission paused";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
linkSendPrim("HOLDA"); linkSendPrim("HOLDA");
end end
else begin else begin
...@@ -631,73 +769,116 @@ task linkTransmitFIS; ...@@ -631,73 +769,116 @@ task linkTransmitFIS;
end end
end end
// L_SendCRC // L_SendCRC
scrambler_value = scrambleFunc(scrambler_value[31:16]); // scrambler_value = scrambleFunc(scrambler_value[31:16]);
scrambler_value = scrambleFunc({16'b0,scrambler_value[31:16]});
if (transmit_custom_crc != 0) begin if (transmit_custom_crc != 0) begin
crc = transmit_crc; crc = transmit_crc;
end end
linkSendData(crc ^ scrambler_value); linkSendData(crc ^ scrambler_value);
$display("[Device] LINK: Sent crc = %h", crc); // $display("[Device] LINK: Sent crc = %h", crc);
DEV_TITLE = "Sent crc";
DEV_DATA = crc;
$display("[Device] LINK: %s = %h @%t", DEV_TITLE, DEV_DATA, $time);
@ (posedge clk) @ (posedge clk)
rprim = linkGetPrim(0); rprim = linkGetPrim(0);
if (~phy_ready) begin if (~phy_ready) begin
$display("[Device] LINK: Unexpected line disconnect"); // $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #11";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
$finish; $finish;
end end
if (rprim == "SYNC") begin if (rprim == "SYNC") begin
$display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id); // $display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id);
DEV_TITLE = "Transmission terminated by the host #3";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
$finish; $finish;
end end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin if ((rprim == "SCRAP") || (rprim == "DATA")) begin
$display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id); // $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #7";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
$finish; $finish;
end end
// L_SendEOF // L_SendEOF
linkSendPrim("EOF"); linkSendPrim("EOF");
$display("[Device] LINK: Sent End of FIS"); // $display("[Device] LINK: Sent End of FIS");
DEV_TITLE = "Sent End of FIS";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
@ (posedge clk) @ (posedge clk)
rprim = linkGetPrim(0); rprim = linkGetPrim(0);
if (~phy_ready) begin if (~phy_ready) begin
$display("[Device] LINK: Unexpected line disconnect"); // $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #12";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
$finish; $finish;
end end
if (rprim == "SYNC") begin if (rprim == "SYNC") begin
$display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id); // $display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id);
DEV_TITLE = "Transmission terminated by the host #4";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
$finish; $finish;
end end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin if ((rprim == "SCRAP") || (rprim == "DATA")) begin
$display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id); // $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #8";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
$finish; $finish;
end end
// L_Wait // L_Wait
linkSendPrim("WTRM"); linkSendPrim("WTRM");
$display("[Device] LINK: Waiting for a response from the host"); // $display("[Device] LINK: Waiting for a response from the host");
DEV_TITLE = "Waiting for a response from the host";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
@ (posedge clk) @ (posedge clk)
rprim = linkGetPrim(0); rprim = linkGetPrim(0);
status = 0; status = 0;
while ((rprim != "OK") && (status == 0)) begin while ((rprim != "OK") && (status == 0)) begin
if (~phy_ready) begin if (~phy_ready) begin
$display("[Device] LINK: Unexpected line disconnect"); //$display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #13";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
$finish; $finish;
end end
if (rprim == "SYNC") begin if (rprim == "SYNC") begin
$display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id); // $display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id);
DEV_TITLE = "Transmission terminated by the host #5";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
$finish; $finish;
end end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin if ((rprim == "SCRAP") || (rprim == "DATA")) begin
$display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id); // $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #9";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
$finish; $finish;
end end
if (rprim == "ERR") begin if (rprim == "ERR") begin
$display("[Device] LINK: Host invalidated the transmission, transmission id = %d", id); // $display("[Device] LINK: Host invalidated the transmission, transmission id = %d", id);
DEV_TITLE = "Host invalidated the transmission";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
status = 1; status = 1;
end end
@ (posedge clk) @ (posedge clk)
rprim = linkGetPrim(0); rprim = linkGetPrim(0);
end end
if (status == 0) if (status == 0)
$display("[Device] LINK: Transmission done OK, id = %d", id); // $display("[Device] LINK: Transmission done OK, id = %d", id);
DEV_TITLE = "Transmission done OK";
DEV_DATA = id;
$display("[Device] LINK: %s, id = %d @%t", DEV_TITLE, DEV_DATA, $time);
if (status == 1) if (status == 1)
$display("[Device] LINK: Transmission done with ERRORs, id = %d", id); // $display("[Device] LINK: Transmission done with ERRORs, id = %d", id);
DEV_TITLE = "Transmission done with ERRORS";
DEV_DATA = id;
$display("[Device] LINK: %s, id = %d @%t", DEV_TITLE, DEV_DATA, $time);
// L_IDLE // L_IDLE
linkSendPrim("SYNC"); linkSendPrim("SYNC");
@ (posedge clk); @ (posedge clk);
......
dma/dma_regs.v
View file @ 6efdc1f7
...@@ -39,6 +39,7 @@ module dma_regs( ...@@ -39,6 +39,7 @@ module dma_regs(
input wire bram_ren, input wire bram_ren,
input wire bram_regen, input wire bram_regen,
// all registers sh_* outputs valid @ACLK
// tmp to cmd control // tmp to cmd control
output wire cmd_val_out, output wire cmd_val_out,
output wire [31:0] cmd_out, output wire [31:0] cmd_out,
...@@ -82,6 +83,7 @@ module dma_regs( ...@@ -82,6 +83,7 @@ module dma_regs(
output wire sh_dir_val, output wire sh_dir_val,
// inputs from sh registers // inputs from sh registers
// No registers, just mux-ed (so @ACLK)
input wire sh_data_val_in, input wire sh_data_val_in,
input wire [31:0] sh_data_in, input wire [31:0] sh_data_in,
input wire [7:0] sh_control_in, input wire [7:0] sh_control_in,
......
dma/sata_top.v
View file @ 6efdc1f7
...@@ -291,228 +291,229 @@ always @ (posedge hclk) ...@@ -291,228 +291,229 @@ always @ (posedge hclk)
axi_regs axi_regs( axi_regs axi_regs(
// axi iface // axi iface
.ACLK (ACLK), .ACLK (ACLK), // input wire
.ARESETN (ARESETN), .ARESETN (ARESETN), // input wire
.ARADDR (ARADDR), .ARADDR (ARADDR), // input[31:0] wire
.ARVALID (ARVALID), .ARVALID (ARVALID), // input wire
.ARREADY (ARREADY), .ARREADY (ARREADY), // output wire
.ARID (ARID), .ARID (ARID), // input[11:0] wire
.ARLEN (ARLEN), .ARLEN (ARLEN), // input[3:0] wire
.ARSIZE (ARSIZE), .ARSIZE (ARSIZE), // input[1:0] wire
.ARBURST (ARBURST), .ARBURST (ARBURST), // input[1:0] wire
.RDATA (RDATA), .RDATA (RDATA), // output[31:0] wire
.RVALID (RVALID), .RVALID (RVALID), // output wire
.RREADY (RREADY), .RREADY (RREADY), // input wire
.RID (RID), .RID (RID), // output[11:0] wire
.RLAST (RLAST), .RLAST (RLAST), // output wire
.RRESP (RRESP), .RRESP (RRESP), // output[1:0] wire
.AWADDR (AWADDR), .AWADDR (AWADDR), // input[31:0] wire
.AWVALID (AWVALID), .AWVALID (AWVALID), // input wire
.AWREADY (AWREADY), .AWREADY (AWREADY), // output wire
.AWID (AWID), .AWID (AWID), // input[11:0] wire
.AWLEN (AWLEN), .AWLEN (AWLEN), // input[3:0] wire
.AWSIZE (AWSIZE), .AWSIZE (AWSIZE), // input[1:0] wire
.AWBURST (AWBURST), .AWBURST (AWBURST), // input[1:0] wire
.WDATA (WDATA), .WDATA (WDATA), // input[31:0] wire
.WVALID (WVALID), .WVALID (WVALID), // input wire
.WREADY (WREADY), .WREADY (WREADY), // output wire
.WID (WID), .WID (WID), // input[11:0] wire
.WLAST (WLAST), .WLAST (WLAST), // input wire
.WSTRB (WSTRB), .WSTRB (WSTRB), // input wire
.BVALID (BVALID), .BVALID (BVALID), // output wire
.BREADY (BREADY), .BREADY (BREADY), // input wire
.BID (BID), .BID (BID), // output[11:0] wire
.BRESP (BRESP), .BRESP (BRESP), // output[1:0] wire
// registers iface // registers iface
.bram_rdata (bram_rdata), .bram_rdata (bram_rdata),// input[31:0] wire
.bram_waddr (bram_waddr), .bram_waddr (bram_waddr),// output[31:0] wire
.bram_wdata (bram_wdata), .bram_wdata (bram_wdata),// output[31:0] wire
.bram_raddr (bram_raddr), .bram_raddr (bram_raddr),// output[31:0] wire
.bram_wstb (bram_wstb), .bram_wstb (bram_wstb), // output[3:0] wire
.bram_wen (bram_wen), .bram_wen (bram_wen), // output wire
.bram_ren (bram_ren), .bram_ren (bram_ren), // output wire
.bram_regen (bram_regen) .bram_regen (bram_regen) // output wire
); );
/* /*
* Programmable sata controller registers * Programmable sata controller registers
*/ */
dma_regs dma_regs( dma_regs dma_regs(
.rst (ARESETN), .rst (ARESETN), // input wire
.ACLK (ACLK), .ACLK (ACLK), // input wire
.sclk (sclk), .sclk (sclk), // input wire
// control iface // control iface
.mem_address (mem_address[31:7]), .mem_address (mem_address[31:7]), // output[31:7] wire
.lba (lba), .lba (lba), // output[31:0] wire
.sector_cnt (sector_cnt), .sector_cnt (sector_cnt), // output[31:0] wire
.dma_type (dma_type), .dma_type (dma_type), // output wire
.dma_start (dma_start), .dma_start (dma_start), // output wire
.dma_done (dma_done), .dma_done (dma_done), // input wire
// axi buffer iface // axi buffer iface
.bram_rdata (bram_rdata), .bram_rdata (bram_rdata), // output[31:0] wire
.bram_raddr (bram_raddr), .bram_raddr (bram_raddr), // input[31:0] wire
.bram_waddr (bram_waddr), .bram_waddr (bram_waddr), // input[31:0] wire
.bram_wdata (bram_wdata), .bram_wdata (bram_wdata), // input[31:0] wire
.bram_wstb (bram_wstb), .bram_wstb (bram_wstb), // input[ 3:0] wire
.bram_wen (bram_wen), .bram_wen (bram_wen), // input wire
.bram_ren (bram_ren), .bram_ren (bram_ren), // input wire
.bram_regen (bram_regen), .bram_regen (bram_regen), // input wire
// direct connections to the host // direct connections to the host
// tmp to cmd control // tmp to cmd control
.cmd_val_out (cmd_val_out), .cmd_val_out (cmd_val_out), // output wire
.cmd_out (cmd_out), .cmd_out (cmd_out), // output[31:0] wire
// tmp to shadow registers // tmp to shadow registers
.sh_data (sh_data), // write data .sh_data (sh_data), // output[31:0] wire : write data
.sh_data_val (sh_data_val), // write strobe .sh_data_val (sh_data_val), // output wire: write strobe
.sh_data_strobe (sh_data_strobe), // read strobe .sh_data_strobe (sh_data_strobe), // output wire: read strobe
.sh_feature (sh_feature), .sh_feature (sh_feature), // output[15:0] wire
.sh_feature_val (sh_feature_val), .sh_feature_val (sh_feature_val), // output wire
.sh_lba_lo (sh_lba_lo), .sh_lba_lo (sh_lba_lo), // output[23:0] wire
.sh_lba_lo_val (sh_lba_lo_val), .sh_lba_lo_val (sh_lba_lo_val), // output wire
.sh_lba_hi (sh_lba_hi), .sh_lba_hi (sh_lba_hi), // output[23:0] wire
.sh_lba_hi_val (sh_lba_hi_val), .sh_lba_hi_val (sh_lba_hi_val), // output wire
.sh_count (sh_count), .sh_count (sh_count), // output[15:0] wire
.sh_count_val (sh_count_val), .sh_count_val (sh_count_val), // output wire
.sh_command (sh_command), .sh_command (sh_command), // output[7:0] wire
.sh_command_val (sh_command_val), .sh_command_val (sh_command_val), // output wire
.sh_dev (sh_dev), .sh_dev (sh_dev), // output[7:0] wire
.sh_dev_val (sh_dev_val), .sh_dev_val (sh_dev_val), // output wire
.sh_control (sh_control), .sh_control (sh_control), // output[7:0] wire
.sh_control_val (sh_control_val), .sh_control_val (sh_control_val), // output wire
.sh_dma_id_lo (sh_dma_id_lo), .sh_dma_id_lo (sh_dma_id_lo), // output[31:0] wire
.sh_dma_id_lo_val (sh_dma_id_lo_val), .sh_dma_id_lo_val (sh_dma_id_lo_val),// output wire
.sh_dma_id_hi (sh_dma_id_hi), .sh_dma_id_hi (sh_dma_id_hi), // output[31:0] wire
.sh_dma_id_hi_val (sh_dma_id_hi_val), .sh_dma_id_hi_val (sh_dma_id_hi_val),// output wire
.sh_buf_off (sh_buf_off), .sh_buf_off (sh_buf_off), // output[31:0] wire
.sh_buf_off_val (sh_buf_off_val), .sh_buf_off_val (sh_buf_off_val), // output wire
.sh_dma_cnt (sh_dma_cnt), .sh_dma_cnt (sh_dma_cnt), // output[31:0] wire
.sh_dma_cnt_val (sh_dma_cnt_val), .sh_dma_cnt_val (sh_dma_cnt_val), // output wire
.sh_tran_cnt (sh_tran_cnt), .sh_tran_cnt (sh_tran_cnt), // output[15:0] wire
.sh_tran_cnt_val (sh_tran_cnt_val), .sh_tran_cnt_val (sh_tran_cnt_val), // output wire
.sh_autoact (sh_autoact), .sh_autoact (sh_autoact), // output wire
.sh_autoact_val (sh_autoact_val), .sh_autoact_val (sh_autoact_val), // output wire
.sh_inter (sh_inter), .sh_inter (sh_inter), // output wire
.sh_inter_val (sh_inter_val), .sh_inter_val (sh_inter_val), // output wire
.sh_port (sh_port), .sh_port (sh_port), // output[3:0] wire
.sh_port_val (sh_port_val), .sh_port_val (sh_port_val), // output wire
.sh_notif (sh_notif), .sh_notif (sh_notif), // output wire
.sh_notif_val (sh_notif_val), .sh_notif_val (sh_notif_val), // output wire
.sh_dir (sh_dir), .sh_dir (sh_dir), // output wire
.sh_dir_val (sh_dir_val), .sh_dir_val (sh_dir_val), // output wire
// inputs from sh registers // inputs from sh registers
.sh_data_val_in (sh_data_val_in), .sh_data_val_in (sh_data_val_in), // input wire
.sh_data_in (sh_data_in), .sh_data_in (sh_data_in), // input[31:0] wire
.sh_control_in (sh_control_in), .sh_control_in (sh_control_in), // input[7:0] wire
.sh_feature_in (sh_feature_in), .sh_feature_in (sh_feature_in), // input[15:0] wire
.sh_lba_in (sh_lba_in), .sh_lba_in (sh_lba_in), // input[47:0] wire
.sh_count_in (sh_count_in), .sh_count_in (sh_count_in), // input[15:0] wire
.sh_command_in (sh_command_in), .sh_command_in (sh_command_in), // input[7:0] wire
.sh_err_in (sh_err_in), .sh_err_in (sh_err_in), // input[7:0] wire
.sh_status_in (sh_status_in), .sh_status_in (sh_status_in), // input[7:0] wire
.sh_estatus_in (sh_estatus_in), // E_Status .sh_estatus_in (sh_estatus_in), // input[7:0] wire : E_Status
.sh_dev_in (sh_dev_in), .sh_dev_in (sh_dev_in), // input[7:0] wire
.sh_port_in (sh_port_in), .sh_port_in (sh_port_in), // input[3:0] wire
.sh_inter_in (sh_inter_in), .sh_inter_in (sh_inter_in), // input wire
.sh_dir_in (sh_dir_in), .sh_dir_in (sh_dir_in), // input wire
.sh_dma_id_in (sh_dma_id_in), .sh_dma_id_in (sh_dma_id_in), // input[63:0] wire
.sh_dma_off_in (sh_dma_off_in), .sh_dma_off_in (sh_dma_off_in), // input[31:0] wire
.sh_dma_cnt_in (sh_dma_cnt_in), .sh_dma_cnt_in (sh_dma_cnt_in), // input[31:0] wire
.sh_tran_cnt_in (sh_tran_cnt_in), // Transfer Count .sh_tran_cnt_in (sh_tran_cnt_in), // Transfer Count
.sh_notif_in (sh_notif_in), .sh_notif_in (sh_notif_in), // input wire
.sh_autoact_in (sh_autoact_in), .sh_autoact_in (sh_autoact_in), // input wire
// inputs from cmd control // inputs from cmd control
.cmd_in (cmd_in) .cmd_in (cmd_in) // input[31:0] wire
); );
dma_control dma_control( dma_control dma_control(
.sclk (sclk), .sclk (sclk), // input wire
.hclk (hclk), .hclk (hclk), // input wire
.rst (sata_rst), .rst (sata_rst), // input wire
// registers iface // registers iface
.mem_address (mem_address[31:7]), .mem_address (mem_address[31:7]), // input[31:7] wire
.lba (lba), .lba (lba), // input[31:0] wire
.sector_cnt (sector_cnt), .sector_cnt (sector_cnt), // input[31:0] wire
.dma_type (dma_type), .dma_type (dma_type), // input wire
.dma_start (dma_start), .dma_start (dma_start), // input wire
.dma_done (dma_done), .dma_done (dma_done), // output wire
// adapter command iface // adapter command iface
.adp_busy (adp_busy), .adp_busy (adp_busy), // input wire
.adp_addr (adp_addr[31:7]), .adp_addr (adp_addr[31:7]), // output[31:7] wire
.adp_type (adp_type), .adp_type (adp_type), // output wire
.adp_val (adp_val), .adp_val (adp_val), // output wire
// sata host command iface // sata host command iface
.host_ready_for_cmd (host_ready_for_cmd), .host_ready_for_cmd (host_ready_for_cmd), // input wire
.host_new_cmd (host_new_cmd), .host_new_cmd (host_new_cmd), // output wire
.host_cmd_type (host_cmd_type), .host_cmd_type (host_cmd_type), // output[1:0] wire
.host_sector_count (host_sector_count), .host_sector_count (host_sector_count), // output[31:0] wire
.host_sector_addr (host_sector_addr), .host_sector_addr (host_sector_addr), // output[31:0] wire
// adapter data iface // adapter data iface
// to main memory // to main memory
.to_data (to_data), .to_data (to_data), // output[63:0] wire
.to_val (to_val), .to_val (to_val), // output wire
.to_ack (to_ack), .to_ack (to_ack), // input wire
// from main memory // from main memory
.from_data (from_data), .from_data (from_data), // input[63:0] wire
.from_val (from_val), .from_val (from_val), // input wire
.from_ack (from_ack), .from_ack (from_ack), // output wire
// sata host iface // sata host iface
// data from sata host // data from sata host
.in_data (in_data), .in_data (in_data), // input[31:0] wire
.in_val (in_val), .in_val (in_val), // output wire
.in_busy (in_busy), .in_busy (in_busy), // input wire
// data to sata host // data to sata host
.out_data (out_data), .out_data (out_data), // output[31:0] wire
.out_val (out_val), .out_val (out_val), // output wire
.out_busy (out_busy) .out_busy (out_busy) // input wire
); );
//assign rdata_done = membridge.is_last_in_page & membridge.afi_rready; //assign rdata_done = membridge.is_last_in_page & membridge.afi_rready;
dma_adapter dma_adapter( dma_adapter dma_adapter(
.clk (hclk), .clk (hclk), // input wire
.rst (hrst), .rst (hrst), // input wire
// command iface // command iface
.cmd_type (adp_type), .cmd_type (adp_type), // input wire
.cmd_val (adp_val), .cmd_val (adp_val), // input wire
.cmd_addr (adp_addr[31:7]), .cmd_addr (adp_addr[31:7]), // input[31:7] wire
.cmd_busy (adp_busy), .cmd_busy (adp_busy), // output wire
// data iface // data iface
.wr_data_in (to_data), .wr_data_in (to_data), // input[63:0] wire
.wr_val_in (to_val), .wr_val_in (to_val), // input wire
.wr_ack_out (to_ack), .wr_ack_out (to_ack), // output wire
.rd_data_out (from_data), .rd_data_out (from_data), // output[63:0] wire
.rd_val_out (from_val), .rd_val_out (from_val), // output wire
.rd_ack_in (from_ack), .rd_ack_in (from_ack), // input wire
// membridge iface // membridge iface
.cmd_ad (cmd_ad), .cmd_ad (cmd_ad), // output[7:0] wire
.cmd_stb (cmd_stb), .cmd_stb (cmd_stb), // output wire
.status_ad (status_ad), .status_ad (status_ad), // input[7:0] wire Not used
.status_rq (status_rq), .status_rq (status_rq), // input wire Not used
.status_start (status_start), .status_start (status_start), // output wire
.frame_start_chn (frame_start_chn), .frame_start_chn (frame_start_chn), // input wire Not used
.next_page_chn (next_page_chn), .next_page_chn (next_page_chn), // input wire Not used
.cmd_wrmem (cmd_wrmem), .cmd_wrmem (cmd_wrmem), // output wire
.page_ready_chn (page_ready_chn), .page_ready_chn (page_ready_chn), // output wire
.frame_done_chn (frame_done_chn), .frame_done_chn (frame_done_chn), // output wire
.line_unfinished_chn1 (line_unfinished_chn1), .line_unfinished_chn1 (line_unfinished_chn1),// output[15:0] wire Not used
.suspend_chn1 (suspend_chn1), .suspend_chn1 (suspend_chn1), // input wire Not used
.xfer_reset_page_rd (xfer_reset_page_rd), .xfer_reset_page_rd (xfer_reset_page_rd), // output wire
.buf_wpage_nxt (buf_wpage_nxt), .buf_wpage_nxt (buf_wpage_nxt), // output wire
.buf_wr (buf_wr), .buf_wr (buf_wr), // output wire
.buf_wdata (buf_wdata), .buf_wdata (buf_wdata), // output[63:0] wire
.xfer_reset_page_wr (xfer_reset_page_wr), .xfer_reset_page_wr (xfer_reset_page_wr), // output wire
.buf_rpage_nxt (buf_rpage_nxt), .buf_rpage_nxt (buf_rpage_nxt), // output wire
.buf_rd (buf_rd), .buf_rd (buf_rd), // output wire
.buf_rdata (buf_rdata), .buf_rdata (buf_rdata), // input[63:0] wire
.rdata_done (rdata_done) .rdata_done (rdata_done) // input wire
); );
...@@ -531,75 +532,75 @@ V .MEMBRIDGE_ADDR (), ...@@ -531,75 +532,75 @@ V .MEMBRIDGE_ADDR (),
.FRAME_HEIGHT_BITS (), .FRAME_HEIGHT_BITS (),
.FRAME_WIDTH_BITS () .FRAME_WIDTH_BITS ()
)*/ membridge( )*/ membridge(
.mrst (hrst), // input .mrst (sata_rst), // hrst), // input Andrey: Wrong, should be @sclk
.hrst (hrst), // input .hrst (hrst), // input
.mclk (sclk), // input .mclk (sclk), // input
.hclk (hclk), // input .hclk (hclk), // input
.cmd_ad (cmd_ad), .cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), .cmd_stb (cmd_stb), // input // Nothing here
.status_ad (status_ad), .status_ad (status_ad), // output[7:0]
.status_rq (status_rq), .status_rq (status_rq), // output
.status_start (status_start), .status_start (status_start), // input
.frame_start_chn (frame_start_chn), .frame_start_chn (frame_start_chn), // output
.next_page_chn (next_page_chn), .next_page_chn (next_page_chn), // output
.cmd_wrmem (cmd_wrmem), .cmd_wrmem (cmd_wrmem), // input
.page_ready_chn (page_ready_chn), .page_ready_chn (page_ready_chn), // input
.frame_done_chn (frame_done_chn), .frame_done_chn (frame_done_chn), // input
.line_unfinished_chn1 (line_unfinished_chn1), .line_unfinished_chn1 (line_unfinished_chn1), // input[15:0]
.suspend_chn1 (suspend_chn1), .suspend_chn1 (suspend_chn1), // output
.xfer_reset_page_rd (xfer_reset_page_rd), .xfer_reset_page_rd (xfer_reset_page_rd), // input
.buf_wpage_nxt (buf_wpage_nxt), .buf_wpage_nxt (buf_wpage_nxt), // input
.buf_wr (buf_wr), .buf_wr (buf_wr), // input
.buf_wdata (buf_wdata), .buf_wdata (buf_wdata), // input[63:0]
.xfer_reset_page_wr (xfer_reset_page_wr), .xfer_reset_page_wr (xfer_reset_page_wr), // input
.buf_rpage_nxt (buf_rpage_nxt), .buf_rpage_nxt (buf_rpage_nxt), // input
.buf_rd (buf_rd), .buf_rd (buf_rd), // input
.buf_rdata (buf_rdata), .buf_rdata (buf_rdata), // output[63:0]
.afi_awaddr (afi_awaddr), // output[31:0] .afi_awaddr (afi_awaddr), // output[31:0]
.afi_awvalid (afi_awvalid), // output .afi_awvalid (afi_awvalid), // output
.afi_awready (afi_awready), // input .afi_awready (afi_awready), // input
.afi_awid (afi_awid), // output[5:0] .afi_awid (afi_awid), // output[5:0]
.afi_awlock (afi_awlock), // output[1:0] .afi_awlock (afi_awlock), // output[1:0]
.afi_awcache (afi_awcache), // output[3:0] .afi_awcache (afi_awcache), // output[3:0]
.afi_awprot (afi_awprot), // output[2:0] .afi_awprot (afi_awprot), // output[2:0]
.afi_awlen (afi_awlen), // output[3:0] .afi_awlen (afi_awlen), // output[3:0]
.afi_awsize (afi_awsize), // output[2:0] .afi_awsize (afi_awsize), // output[2:0]
.afi_awburst (afi_awburst), // output[1:0] .afi_awburst (afi_awburst), // output[1:0]
.afi_awqos (afi_awqos), // output[3:0] .afi_awqos (afi_awqos), // output[3:0]
.afi_wdata (afi_wdata), // output[63:0] .afi_wdata (afi_wdata), // output[63:0]
.afi_wvalid (afi_wvalid), // output .afi_wvalid (afi_wvalid), // output
.afi_wready (afi_wready), // input .afi_wready (afi_wready), // input
.afi_wid (afi_wid), // output[5:0] .afi_wid (afi_wid), // output[5:0]
.afi_wlast (afi_wlast), // output .afi_wlast (afi_wlast), // output
.afi_wstrb (afi_wstrb), // output[7:0] .afi_wstrb (afi_wstrb), // output[7:0]
.afi_bvalid (afi_bvalid), // input .afi_bvalid (afi_bvalid), // input
.afi_bready (afi_bready), // output .afi_bready (afi_bready), // output
.afi_bid (afi_bid), // input[5:0] .afi_bid (afi_bid), // input[5:0]
.afi_bresp (afi_bresp), // input[1:0] .afi_bresp (afi_bresp), // input[1:0]
.afi_wcount (afi_wcount), // input[7:0] .afi_wcount (afi_wcount), // input[7:0]
.afi_wacount (afi_wacount), // input[5:0] .afi_wacount (afi_wacount), // input[5:0]
.afi_wrissuecap1en (afi_wrissuecap1en), // output .afi_wrissuecap1en (afi_wrissuecap1en), // output
.afi_araddr (afi_araddr), // output[31:0] .afi_araddr (afi_araddr), // output[31:0]
.afi_arvalid (afi_arvalid), // output .afi_arvalid (afi_arvalid), // output
.afi_arready (afi_arready), // input .afi_arready (afi_arready), // input
.afi_arid (afi_arid), // output[5:0] .afi_arid (afi_arid), // output[5:0]
.afi_arlock (afi_arlock), // output[1:0] .afi_arlock (afi_arlock), // output[1:0]
.afi_arcache (afi_arcache), // output[3:0] .afi_arcache (afi_arcache), // output[3:0]
.afi_arprot (afi_arprot), // output[2:0] .afi_arprot (afi_arprot), // output[2:0]
.afi_arlen (afi_arlen), // output[3:0] .afi_arlen (afi_arlen), // output[3:0]
.afi_arsize (afi_arsize), // output[2:0] .afi_arsize (afi_arsize), // output[2:0]
.afi_arburst (afi_arburst), // output[1:0] .afi_arburst (afi_arburst), // output[1:0]
.afi_arqos (afi_arqos), // output[3:0] .afi_arqos (afi_arqos), // output[3:0]
.afi_rdata (afi_rdata), // input[63:0] .afi_rdata (afi_rdata), // input[63:0]
.afi_rvalid (afi_rvalid), // input .afi_rvalid (afi_rvalid), // input
.afi_rready (afi_rready), // output .afi_rready (afi_rready), // output
.afi_rid (afi_rid), // input[5:0] .afi_rid (afi_rid), // input[5:0]
.afi_rlast (afi_rlast), // input .afi_rlast (afi_rlast), // input
.afi_rresp (afi_rresp), // input[2:0] .afi_rresp (afi_rresp), // input[2:0]
.afi_rcount (afi_rcount), // input[7:0] .afi_rcount (afi_rcount), // input[7:0]
.afi_racount (afi_racount), // input[2:0] .afi_racount (afi_racount), // input[2:0]
.afi_rdissuecap1en (afi_rdissuecap1en)/*, // output .afi_rdissuecap1en (afi_rdissuecap1en)/*, // output
.rdata_done (rdata_done)*/ .rdata_done (rdata_done)*/
); );
assign rdata_done = 1'b0; assign rdata_done = 1'b0;
...@@ -657,7 +658,7 @@ sata_host sata_host( ...@@ -657,7 +658,7 @@ sata_host sata_host(
.al_sh_port_in (sh_port), .al_sh_port_in (sh_port),
.al_sh_port_val_in (sh_port_val), .al_sh_port_val_in (sh_port_val),
// outputs from shadow registers // outputs from shadow registers - no registers, just MUX-ed and read @ACLK
.sh_data_val_out (sh_data_val_in), .sh_data_val_out (sh_data_val_in),
.sh_data_out (sh_data_in), .sh_data_out (sh_data_in),
......
dma/top.v
View file @ 6efdc1f7
...@@ -21,9 +21,10 @@ ...@@ -21,9 +21,10 @@
/* /*
* all signals' and modules' names and interconnections are taken from x393.v * all signals' and modules' names and interconnections are taken from x393.v
* to make the final integration easier - just to make an instance of * to make the final integration easier - just to make an instance of
* what is called now 'axi_regs' and connect it * what is called now 'axi_regs' and connect it
*/ */
//`include "system_defines.vh" // Including system defines at the top level can distinguish between simulation and synthesis?
`include "system_defines.vh"
//`include "sata_top.v" //`include "sata_top.v"
module top #( module top #(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - partially used `include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - partially used
......
host/command.v
View file @ 6efdc1f7
...@@ -255,12 +255,14 @@ always @ (posedge clk) ...@@ -255,12 +255,14 @@ always @ (posedge clk)
always @ (posedge clk) always @ (posedge clk)
raddr <= rst ? 10'b0 : al_sh_data_strobe_in ? raddr + 1'b1 : raddr; raddr <= rst ? 10'b0 : al_sh_data_strobe_in ? raddr + 1'b1 : raddr;
// Application layer has different clock ?
ram_1kx32_1kx32 rbuf( ram_1kx32_1kx32 rbuf(
.rclk (clk), // clock for read port .rclk (clk), // clock for read port
.raddr (raddr), // read address .raddr (raddr), // read address
.ren (al_sh_data_strobe_in), // read port enable .ren (al_sh_data_strobe_in), // read port enable
.regen (1'b0), // output register enable .regen (1'b0), // output register enable
.data_out (sh_data), // data out .data_out (sh_data), // data out
.wclk (clk), // clock for read port .wclk (clk), // clock for read port
.waddr (waddr), // write address .waddr (waddr), // write address
......
host/gtx_wrap.v
View file @ 6efdc1f7
...@@ -135,9 +135,9 @@ if (DATA_BYTE_WIDTH == 4) begin ...@@ -135,9 +135,9 @@ if (DATA_BYTE_WIDTH == 4) begin
reg [ 1:0] txcharisk_enc_in_r; reg [ 1:0] txcharisk_enc_in_r;
wire [38:0] txdata_resync_out; wire [38:0] txdata_resync_out;
wire txdata_resync_valid; wire txdata_resync_valid;
reg txcomwake_gtx_f; reg [1:0] txcomwake_gtx_f; // 2 registers just to match latency (data to the 3 next) in Alexey's code, probbaly not needed
reg txcominit_gtx_f; reg [1:0] txcominit_gtx_f;
reg txelecidle_gtx_f; reg [1:0] txelecidle_gtx_f;
resync_data #( // TODO: update output register.. OK as it is resync_data #( // TODO: update output register.. OK as it is
.DATA_WIDTH(39), .DATA_WIDTH(39),
...@@ -156,7 +156,7 @@ if (DATA_BYTE_WIDTH == 4) begin ...@@ -156,7 +156,7 @@ if (DATA_BYTE_WIDTH == 4) begin
); );
always @ (posedge txreset or posedge txusrclk) begin always @ (posedge txreset or posedge txusrclk) begin
if (txreset) txdata_resync_strobe <= 0; if (txreset) txdata_resync_strobe <= 0;
else if (txdata_resync_valid) txdata_resync_strobe <= ~txdata_resync_strobe[0]; else if (txdata_resync_valid) txdata_resync_strobe <= ~txdata_resync_strobe;
if (txreset) begin if (txreset) begin
txdata_enc_in_r <= 0; txdata_enc_in_r <= 0;
...@@ -169,18 +169,18 @@ if (DATA_BYTE_WIDTH == 4) begin ...@@ -169,18 +169,18 @@ if (DATA_BYTE_WIDTH == 4) begin
if (txreset) begin if (txreset) begin
txcomwake_gtx_f <= 0; txcomwake_gtx_f <= 0;
txcominit_gtx_f <= 0; txcominit_gtx_f <= 0;
txelecidle_gtx_f <= 0; txelecidle_gtx_f <= ~0;
end else begin end else begin
txcomwake_gtx_f <= txdata_resync_out[36]; txcomwake_gtx_f <= {txdata_resync_out[36],txcomwake_gtx_f[1]};
txcominit_gtx_f <= txdata_resync_out[37]; txcominit_gtx_f <= {txdata_resync_out[37],txcominit_gtx_f[1]};
txelecidle_gtx_f <= txdata_resync_out[38]; txelecidle_gtx_f <= {txdata_resync_out[38],txelecidle_gtx_f[1]};
end end
end end
assign txdata_enc_in = txdata_enc_in_r; assign txdata_enc_in = txdata_enc_in_r;
assign txcharisk_enc_in = txcharisk_enc_in_r; assign txcharisk_enc_in = txcharisk_enc_in_r;
assign txcominit_gtx = txcominit_gtx_f; assign txcominit_gtx = txcominit_gtx_f[0];
assign txcomwake_gtx = txcomwake_gtx_f; assign txcomwake_gtx = txcomwake_gtx_f[0];
assign txelecidle_gtx = txelecidle_gtx_f; assign txelecidle_gtx = txelecidle_gtx_f[0];
/*wire txdata_resync_nempty; /*wire txdata_resync_nempty;
......
host/link.v
View file @ 6efdc1f7
...@@ -100,16 +100,23 @@ module link #( ...@@ -100,16 +100,23 @@ module link #(
output wire [DATA_BYTE_WIDTH*8 - 1:0] phy_data_out, output wire [DATA_BYTE_WIDTH*8 - 1:0] phy_data_out,
output wire [DATA_BYTE_WIDTH - 1:0] phy_isk_out // charisk output wire [DATA_BYTE_WIDTH - 1:0] phy_isk_out // charisk
); );
`ifdef SIMULATION
reg [639:0] HOST_LINK_TITLE; // to show human-readable state in the GTKWave
reg [31:0] HOST_LINK_DATA;
`endif
// latching data-primitives stream from phy // latching data-primitives stream from phy
reg [DATA_BYTE_WIDTH*8 - 1:0] phy_data_in_r; reg [DATA_BYTE_WIDTH*8 - 1:0] phy_data_in_r;
reg [DATA_BYTE_WIDTH - 1:0] phy_isk_in_r; // charisk reg [DATA_BYTE_WIDTH - 1:0] phy_isk_in_r; // charisk
reg [DATA_BYTE_WIDTH - 1:0] phy_err_in_r; // disperr | notintable reg [DATA_BYTE_WIDTH - 1:0] phy_err_in_r; // disperr | notintable
always @ (posedge clk) //one extra layer to process CONTp
begin reg [DATA_BYTE_WIDTH*8 - 1:0] phy_data_in_r0;
phy_data_in_r <= phy_data_in; reg [DATA_BYTE_WIDTH - 1:0] phy_isk_in_r0; // charisk
phy_isk_in_r <= phy_isk_in; reg [DATA_BYTE_WIDTH - 1:0] phy_err_in_r0; // disperr | notintable
phy_err_in_r <= phy_err_in;
end reg [DATA_BYTE_WIDTH*8 - 1:0] last_not_cont_di; // last primitive dword, but not CONTp
reg rcv_junk; // receiving CONTp junk data
wire is_non_cont_p_w; // got primitive other than CONTp
wire is_cont_p_w; // got CONTp primitive
wire frame_done; wire frame_done;
// scrambled data // scrambled data
...@@ -122,25 +129,48 @@ wire crc_bad; ...@@ -122,25 +129,48 @@ wire crc_bad;
wire [31:0] crc_dword; wire [31:0] crc_dword;
// send primitives variety count, including CRC and DATA as primitives // send primitives variety count, including CRC and DATA as primitives
localparam PRIM_NUM = 15; localparam PRIM_NUM = 16; // 15;
wire [PRIM_NUM - 1:0] rcvd_dword; // shows current processing primitive (or just data dword) wire [PRIM_NUM - 1:0] rcvd_dword; // shows current processing primitive (or just data dword)
wire dword_val; wire dword_val;
// list of bits of rcvd_dword // list of bits of rcvd_dword
localparam CODE_DATA = 0; localparam CODE_DATA = 0; // DATA
localparam CODE_CRC = 1; localparam CODE_CRC = 1; // CRC
localparam CODE_SYNCP = 2; localparam CODE_SYNCP = 2; // SYNCp
localparam CODE_ALIGNP = 3; localparam CODE_ALIGNP = 3; // ALIGNp PHY layer control
localparam CODE_XRDYP = 4; localparam CODE_XRDYP = 4; // X_RDYp Transmission data ready
localparam CODE_SOFP = 5; localparam CODE_SOFP = 5; // SOFp Start of Frame
localparam CODE_HOLDAP = 6; localparam CODE_HOLDAP = 6; // HOLDAp HOLD acknowledge
localparam CODE_HOLDP = 7; localparam CODE_HOLDP = 7; // HOLDp Hold data transmission
localparam CODE_EOFP = 8; localparam CODE_EOFP = 8; // EOFp End Of Frame
localparam CODE_WTRMP = 9; localparam CODE_WTRMP = 9; // WTRMp Wait for frame termination
localparam CODE_RRDYP = 10; localparam CODE_RRDYP = 10; // R_RDYp Receiver ready
localparam CODE_IPP = 11; localparam CODE_IPP = 11; // R_IPp - Reception in progress
localparam CODE_DMATP = 12; localparam CODE_DMATP = 12; // DMATp - DMA terminate
localparam CODE_OKP = 13; localparam CODE_OKP = 13; // R_OKp - Reception with no error
localparam CODE_ERRP = 14; localparam CODE_ERRP = 14; // R_ERRp - Reception with Error
localparam CODE_CONTP = 15; // CONTp - Continue repeating
// processing CONTp/junk, delaying everything by 1 clock
always @ (posedge clk) begin
phy_data_in_r0 <= phy_data_in;
phy_isk_in_r0 <= phy_isk_in;
phy_err_in_r0 <= phy_err_in;
if (is_non_cont_p_w) last_not_cont_di <= phy_data_in_r0;
if (rst || is_non_cont_p_w) rcv_junk <= 0;
else if (is_cont_p_w) rcv_junk <= 1;
if (is_cont_p_w || (rcv_junk && !is_non_cont_p_w)) begin
phy_data_in_r <= last_not_cont_di;
phy_isk_in_r <= 1;
end else begin
phy_data_in_r <= phy_data_in_r0;
phy_isk_in_r <= phy_isk_in_r0;
end
phy_err_in_r <= phy_err_in_r0;
end
reg data_txing; // if there are still some data to transmit and the transaction wasn't cancelled reg data_txing; // if there are still some data to transmit and the transaction wasn't cancelled
always @ (posedge clk) always @ (posedge clk)
...@@ -393,6 +423,9 @@ localparam [15:0] PRIM_OKP_HI = {3'd1, 5'd21, 3'd1, 5'd21}; ...@@ -393,6 +423,9 @@ localparam [15:0] PRIM_OKP_HI = {3'd1, 5'd21, 3'd1, 5'd21};
localparam [15:0] PRIM_OKP_LO = {3'd5, 5'd21, 3'd3, 5'd28}; localparam [15:0] PRIM_OKP_LO = {3'd5, 5'd21, 3'd3, 5'd28};
localparam [15:0] PRIM_ERRP_HI = {3'd2, 5'd22, 3'd2, 5'd22}; localparam [15:0] PRIM_ERRP_HI = {3'd2, 5'd22, 3'd2, 5'd22};
localparam [15:0] PRIM_ERRP_LO = {3'd5, 5'd21, 3'd3, 5'd28}; localparam [15:0] PRIM_ERRP_LO = {3'd5, 5'd21, 3'd3, 5'd28};
//The transmission of CONTp is optional, but the ability to receive and properly process CONTp is required.
localparam [15:0] PRIM_CONTP_HI = {3'd4, 5'd25, 3'd4, 5'd25};
localparam [15:0] PRIM_CONTP_LO = {3'd2, 5'd10, 3'd3, 5'd28};
wire [DATA_BYTE_WIDTH*8 - 1:0] prim_data [PRIM_NUM - 1:0]; wire [DATA_BYTE_WIDTH*8 - 1:0] prim_data [PRIM_NUM - 1:0];
...@@ -417,6 +450,7 @@ begin ...@@ -417,6 +450,7 @@ begin
assign prim_data[CODE_DMATP] [15:0] = prim_word ? PRIM_DMATP_HI : PRIM_DMATP_LO; assign prim_data[CODE_DMATP] [15:0] = prim_word ? PRIM_DMATP_HI : PRIM_DMATP_LO;
assign prim_data[CODE_OKP] [15:0] = prim_word ? PRIM_OKP_HI : PRIM_OKP_LO; assign prim_data[CODE_OKP] [15:0] = prim_word ? PRIM_OKP_HI : PRIM_OKP_LO;
assign prim_data[CODE_ERRP] [15:0] = prim_word ? PRIM_ERRP_HI : PRIM_ERRP_LO; assign prim_data[CODE_ERRP] [15:0] = prim_word ? PRIM_ERRP_HI : PRIM_ERRP_LO;
assign prim_data[CODE_CONTP] [15:0] = prim_word ? PRIM_CONTP_HI : PRIM_CONTP_LO;
always @ (posedge clk) always @ (posedge clk)
begin begin
$display("%m: unsupported data width"); $display("%m: unsupported data width");
...@@ -441,6 +475,7 @@ begin ...@@ -441,6 +475,7 @@ begin
assign prim_data[CODE_DMATP] = {PRIM_DMATP_HI , PRIM_DMATP_LO}; assign prim_data[CODE_DMATP] = {PRIM_DMATP_HI , PRIM_DMATP_LO};
assign prim_data[CODE_OKP] = {PRIM_OKP_HI , PRIM_OKP_LO}; assign prim_data[CODE_OKP] = {PRIM_OKP_HI , PRIM_OKP_LO};
assign prim_data[CODE_ERRP] = {PRIM_ERRP_HI , PRIM_ERRP_LO}; assign prim_data[CODE_ERRP] = {PRIM_ERRP_HI , PRIM_ERRP_LO};
assign prim_data[CODE_CONTP] = {PRIM_CONTP_HI , PRIM_CONTP_LO};
end end
else else
begin begin
...@@ -469,6 +504,7 @@ assign select_prim[CODE_IPP] = ~alignes_pair & (state_rcvr_data & ~incom_ ...@@ -469,6 +504,7 @@ assign select_prim[CODE_IPP] = ~alignes_pair & (state_rcvr_data & ~incom_
assign select_prim[CODE_DMATP] = ~alignes_pair & (state_rcvr_data & incom_stop_f | state_rcvr_shold & incom_stop_f); assign select_prim[CODE_DMATP] = ~alignes_pair & (state_rcvr_data & incom_stop_f | state_rcvr_shold & incom_stop_f);
assign select_prim[CODE_OKP] = ~alignes_pair & (state_rcvr_goodend); assign select_prim[CODE_OKP] = ~alignes_pair & (state_rcvr_goodend);
assign select_prim[CODE_ERRP] = ~alignes_pair & (state_rcvr_badend); assign select_prim[CODE_ERRP] = ~alignes_pair & (state_rcvr_badend);
// No sending of CONTp
// primitive selector MUX // primitive selector MUX
always @ (posedge clk) always @ (posedge clk)
...@@ -584,6 +620,11 @@ assign rcvd_dword[CODE_DMATP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_B ...@@ -584,6 +620,11 @@ assign rcvd_dword[CODE_DMATP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_B
assign rcvd_dword[CODE_OKP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_OKP ] == phy_data_in_r; assign rcvd_dword[CODE_OKP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_OKP ] == phy_data_in_r;
assign rcvd_dword[CODE_ERRP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_ERRP ] == phy_data_in_r; assign rcvd_dword[CODE_ERRP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_ERRP ] == phy_data_in_r;
// CONTp (*_r0 is one cycle ahead of *_r)
assign is_cont_p_w = phy_isk_in_r0[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_CONTP ] == phy_data_in_r0;
assign is_non_cont_p_w = phy_isk_in_r0[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_CONTP ] != phy_data_in_r0;
// phy level errors handling TODO // phy level errors handling TODO
assign dec_err = |phy_err_in_r; assign dec_err = |phy_err_in_r;
...@@ -664,11 +705,16 @@ always @ (posedge clk) ...@@ -664,11 +705,16 @@ always @ (posedge clk)
always @ (posedge clk) always @ (posedge clk)
begin begin
if (data_val_out) begin if (data_val_out) begin
$display("[Host] LINK: From device - received data = %h", data_out); // $display("[Host] LINK: From device - received data = %h @%t", data_out, $time);
HOST_LINK_TITLE = "From device - received data";
HOST_LINK_DATA = data_out;
$display("[Host] LINK: %s = %h @%t", HOST_LINK_TITLE, HOST_LINK_DATA, $time);
`endif
end end
// if (inc_is_data) begin // if (inc_is_data) begin
// $display("[Host] LINK: From device - received raw data = %h", phy_data_in); // $display("[Host] LINK: From device - received raw data = %h", phy_data_in);
// end // end
end end
......
host/oob.v
View file @ 6efdc1f7
...@@ -106,6 +106,12 @@ module oob #( ...@@ -106,6 +106,12 @@ module oob #(
`endif //OOB_MULTISPEED `endif //OOB_MULTISPEED
); );
`ifdef SIMULATION
reg [639:0] HOST_OOB_TITLE; // to show human-readable state in the GTKWave
`endif
// 873.8 us error timer // 873.8 us error timer
// = 2621400 SATA2 serial ticks (period = 0.000333 us) // = 2621400 SATA2 serial ticks (period = 0.000333 us)
// = 131070 ticks @ 150Mhz // = 131070 ticks @ 150Mhz
...@@ -401,16 +407,20 @@ endgenerate ...@@ -401,16 +407,20 @@ endgenerate
always @ (posedge clk) always @ (posedge clk)
begin begin
if (txcominit) begin if (txcominit) begin
$display("[Host] OOB: Issued cominit"); HOST_OOB_TITLE = "Issued cominit";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end end
if (txcomwake) begin if (txcomwake) begin
$display("[Host] OOB: Issued comwake"); HOST_OOB_TITLE = "Issued comwake";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end end
if (state_wait_linkup) begin if (state_wait_linkup) begin
$display("[Host] OOB: Link is up"); HOST_OOB_TITLE = "Link is up";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end end
if (set_wait_synp) begin if (set_wait_synp) begin
$display("[Host] OOB: Started continious align sending"); HOST_OOB_TITLE = "Started continious align sending";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end end
end end
`endif `endif
......
system_defines.vh
View file @ 6efdc1f7
...@@ -6,11 +6,16 @@ ...@@ -6,11 +6,16 @@
`ifdef IVERILOG `ifdef IVERILOG
`define SIMULATION `define SIMULATION
`define OPEN_SOURCE_ONLY `define OPEN_SOURCE_ONLY
`define CHECKERS_ENABLED 1
`else `else
`ifdef CVC `ifdef CVC
`define SIMULATION `define SIMULATION
`define OPEN_SOURCE_ONLY `define OPEN_SOURCE_ONLY
`define CHECKERS_ENABLED 1
`else
`undef OPEN_SOURCE_ONLY
`endif // CVC `endif // CVC
`endif // IVERILOG `endif // IVERILOG
// will not use simultaneous reset in shift registers, just and input data with ~rst // will not use simultaneous reset in shift registers, just and input data with ~rst
......
tb/tb_top.v
View file @ 6efdc1f7
...@@ -19,6 +19,7 @@ ...@@ -19,6 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> . * along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/ *******************************************************************************/
// global defines // global defines
`define IVERILOG
`define SIMULATION `define SIMULATION
`define OPEN_SOURCE_ONLY `define OPEN_SOURCE_ONLY
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
...@@ -55,6 +56,9 @@ module tb #( ...@@ -55,6 +56,9 @@ module tb #(
`endif // CVC `endif // CVC
`endif // IVERILOG `endif // IVERILOG
reg [639:0] TESTBENCH_TITLE; // to show human-readable state in the GTKWave
reg [31:0] TESTBENCH_DATA;
reg [11:0] TESTBENCH_ID;
initial #1 $display("HI THERE"); initial #1 $display("HI THERE");
...@@ -618,12 +622,21 @@ task maxiMonitorPush; ...@@ -618,12 +622,21 @@ task maxiMonitorPush;
begin begin
if (maxi_monitor_raddr == (maxi_monitor_waddr + 1)) begin if (maxi_monitor_raddr == (maxi_monitor_waddr + 1)) begin
$display("[Testbench] maxiMonitorPush: trying to push to a full fifo"); $display("[Testbench] maxiMonitorPush: trying to push to a full fifo");
TESTBENCH_TITLE = "trying to push to a full fifo";
$display("[Testbench] maxiMonitorPush %s = %h, id = %h @%t", TESTBENCH_TITLE, $time);
$finish; $finish;
end end
maxi_monitor_fifo[maxi_monitor_waddr][31:0] = data; maxi_monitor_fifo[maxi_monitor_waddr][31:0] = data;
maxi_monitor_fifo[maxi_monitor_waddr][43:32] = id; maxi_monitor_fifo[maxi_monitor_waddr][43:32] = id;
maxi_monitor_fifo_empty = 1'b0; maxi_monitor_fifo_empty = 1'b0;
$display("[Testbench] MAXI: Got data = %h, id = %h", data, id); // $display("[Testbench] MAXI: Got data = %h, id = %h", data, id);
TESTBENCH_TITLE = "Got data";
TESTBENCH_DATA = data;
TESTBENCH_ID = id;
$display("[Testbench] MAXI %s = %h, id = %h @%t", TESTBENCH_TITLE, TESTBENCH_DATA, TESTBENCH_ID, $time);
//[Testbench] MAXI: %
maxi_monitor_waddr = (maxi_monitor_waddr + 1) % maxi_monitor_fifo_size; maxi_monitor_waddr = (maxi_monitor_waddr + 1) % maxi_monitor_fifo_size;
end end
endtask endtask
...@@ -637,6 +650,8 @@ initial forever @ (posedge CLK) begin ...@@ -637,6 +650,8 @@ initial forever @ (posedge CLK) begin
end end
// testing itself // testing itself
`include "test_top.v" // SuppressThisWarning VEditor - to avoid strange warnings `include "test_top.v" // S uppressThisWarning VEditor - to avoid strange warnings
endmodule endmodule
//`include "x393/glbl.v" // SuppressThisWarning VEditor - duplicate module
tb/test_top.v
View file @ 6efdc1f7
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
/* /*
* this file is included into tb_top.v due to the compatibility with x393 design testbench * this file is included into tb_top.v due to the compatibility with x393 design testbench
*/ */
reg [639:0] TEST_TITLE; // to show human-readable state in the GTKWave
// external clock to gtx // external clock to gtx
...@@ -81,7 +82,10 @@ begin ...@@ -81,7 +82,10 @@ begin
axi_write_single({30'h5, 2'b00}, 32'hEC); axi_write_single({30'h5, 2'b00}, 32'hEC);
// start! // start!
axi_write_single({30'hf, 2'b00}, 32'h0108); axi_write_single({30'hf, 2'b00}, 32'h0108);
$display("[Test] H2D Reg with pio cmd issued"); // $display("[Test]: H2D Reg with pio cmd issued");
TEST_TITLE = "H2D Reg with pio cmd issued";
$display("[Test]: %s @%t", TEST_TITLE, $time);
// wait until reception // wait until reception
while (dev.receive_id != 1) begin while (dev.receive_id != 1) begin
repeat (100) repeat (100)
...@@ -89,11 +93,15 @@ begin ...@@ -89,11 +93,15 @@ begin
end end
if (dev.receive_status != 0) begin if (dev.receive_status != 0) begin
$display("[Test] Failed"); // $display("[Test]: Failed 1");
TEST_TITLE = "Failed #1";
$display("[Test]: %s @%t", TEST_TITLE, $time);
$finish; $finish;
end end
$display("[Test] H2D Reg with pio cmd received by dev"); // $display("[Test]: H2D Reg with pio cmd received by dev");
TEST_TITLE = "H2D Reg with pio cmd received by dev";
$display("[Test]: %s @%t", TEST_TITLE, $time);
// send dev2host reg fis with BSY flag // send dev2host reg fis with BSY flag
repeat (100) repeat (100)
@ (posedge dev.clk); @ (posedge dev.clk);
...@@ -108,17 +116,23 @@ begin ...@@ -108,17 +116,23 @@ begin
dev.linkTransmitFIS(66, 5, 0, status); dev.linkTransmitFIS(66, 5, 0, status);
if (status != 0) begin if (status != 0) begin
$display("[Test] Failed"); // $display("[Test]: Failed 2");
TEST_TITLE = "Failed #2";
$display("[Test]: %s @%t", TEST_TITLE, $time);
$finish; $finish;
end end
$display("[Test] Dev sent BSY flag"); // $display("[Test]: Dev sent BSY flag");
TEST_TITLE = "Dev sent BSY flag";
$display("[Test]: %s @%t", TEST_TITLE, $time);
// checks if BSY is set up // only on waves TODO // checks if BSY is set up // only on waves TODO
axi_read_addr(12'h555, {30'h11, 2'b00}, 4'h3, 2'b01); axi_read_addr(12'h555, {30'h11, 2'b00}, 4'h3, 2'b01);
repeat (50) repeat (50)
@ (posedge dev.clk); @ (posedge dev.clk);
$display("[Test] Device sends PIO Setup"); // $display("[Test]: Device sends PIO Setup");
TEST_TITLE = "Device sends PIO Setup";
$display("[Test]: %s @%t", TEST_TITLE, $time);
dev.transmit_data[0] = 32'h0080205f; // direction d2h, type = 5f dev.transmit_data[0] = 32'h0080205f; // direction d2h, type = 5f
dev.transmit_data[1] = 32'hdeadbeef; // whatever dev.transmit_data[1] = 32'hdeadbeef; // whatever
dev.transmit_data[2] = 32'hdeadbeef; // whatever dev.transmit_data[2] = 32'hdeadbeef; // whatever
...@@ -126,11 +140,15 @@ begin ...@@ -126,11 +140,15 @@ begin
dev.transmit_data[4] = 32'h00000014; // let it be 20 bytes to be transfered dev.transmit_data[4] = 32'h00000014; // let it be 20 bytes to be transfered
dev.linkTransmitFIS(11, 5, 0, status); dev.linkTransmitFIS(11, 5, 0, status);
if (status != 0) begin if (status != 0) begin
$display("[Test] Failed"); // $display("[Test]: Failed 3");
TEST_TITLE = "Failed #3";
$display("[Test]: %s @%t", TEST_TITLE, $time);
$finish; $finish;
end end
$display("[Test] Device sends data FIS"); // $display("[Test]: Device sends data FIS");
TEST_TITLE = "Device sends data FIS";
$display("[Test]: %s @%t", TEST_TITLE, $time);
dev.transmit_data[0] = 32'h00000046; // type = 46 dev.transmit_data[0] = 32'h00000046; // type = 46
dev.transmit_data[1] = 32'hfeeddeaf; dev.transmit_data[1] = 32'hfeeddeaf;
dev.transmit_data[2] = 32'ha114bea7; dev.transmit_data[2] = 32'ha114bea7;
...@@ -139,7 +157,10 @@ begin ...@@ -139,7 +157,10 @@ begin
dev.transmit_data[5] = 32'hdeadbeef; dev.transmit_data[5] = 32'hdeadbeef;
dev.linkTransmitFIS(22, 6, 0, status); dev.linkTransmitFIS(22, 6, 0, status);
if (status != 0) begin if (status != 0) begin
$display("[Test] Failed"); // $display("[Test]: Failed 4");
TEST_TITLE = "Failed #4";
$display("[Test]: %s @%t", TEST_TITLE, $time);
$finish; $finish;
end end
...@@ -152,19 +173,30 @@ begin ...@@ -152,19 +173,30 @@ begin
end end
// imitating PIO reads // imitating PIO reads
$display("[Test] Read data word 0"); // $display("[Test]: Read data word 0");
TEST_TITLE = "Read data word 0";
$display("[Test]: %s @%t", TEST_TITLE, $time);
axi_read_addr(12'h660, {30'h00, 2'b00}, 4'h0, 2'b01); axi_read_addr(12'h660, {30'h00, 2'b00}, 4'h0, 2'b01);
$display("[Test] Read data word 1"); // $display("[Test]: Read data word 1");
TEST_TITLE = "Read data word 1";
$display("[Test]: %s @%t", TEST_TITLE, $time);
axi_read_addr(12'h661, {30'h00, 2'b00}, 4'h0, 2'b01); axi_read_addr(12'h661, {30'h00, 2'b00}, 4'h0, 2'b01);
$display("[Test] Read data word 2"); // $display("[Test]: Read data word 2");
TEST_TITLE = "Read data word 2";
$display("[Test]: %s @%t", TEST_TITLE, $time);
axi_read_addr(12'h662, {30'h00, 2'b00}, 4'h0, 2'b01); axi_read_addr(12'h662, {30'h00, 2'b00}, 4'h0, 2'b01);
$display("[Test] Read data word 3"); // $display("[Test]: Read data word 3");
TEST_TITLE = "Read data word 3";
$display("[Test]: %s @%t", TEST_TITLE, $time);
axi_read_addr(12'h663, {30'h00, 2'b00}, 4'h0, 2'b01); axi_read_addr(12'h663, {30'h00, 2'b00}, 4'h0, 2'b01);
$display("[Test] Read data word 4"); // $display("[Test]: Read data word 4");
TEST_TITLE = "Read data word 4";
$display("[Test]: %s @%t", TEST_TITLE, $time);
axi_read_addr(12'h664, {30'h00, 2'b00}, 4'h0, 2'b01); axi_read_addr(12'h664, {30'h00, 2'b00}, 4'h0, 2'b01);
// check if all ok // check if all ok
...@@ -172,12 +204,18 @@ begin ...@@ -172,12 +204,18 @@ begin
while (~maxiMonitorIsEmpty(0)) begin while (~maxiMonitorIsEmpty(0)) begin
maxiMonitorPop(data, id); maxiMonitorPop(data, id);
if (dev.transmit_data[i] != data) begin if (dev.transmit_data[i] != data) begin
$display("[Test] Data check failed"); // $display("[Test]: Data check failed");
TEST_TITLE = "Data check failed";
$display("[Test]: %s @%t", TEST_TITLE, $time);
$finish; $finish;
end end
i = i + 1; i = i + 1;
end end
$display("[Test] Data check OK"); // $display("[Test]: Data check OK");
TEST_TITLE = "Data check OK";
$display("[Test]: %s @%t", TEST_TITLE, $time);
...@@ -188,6 +226,7 @@ begin ...@@ -188,6 +226,7 @@ begin
$display("data received : %h", dev.receive_data[i]); $display("data received : %h", dev.receive_data[i]);
end*/ end*/
$display("============= DONE ============="); $display("============= DONE =============");
TEST_TITLE = "DONE";
$finish; $finish;
// test SAXI3 iface // test SAXI3 iface
...@@ -241,7 +280,10 @@ end ...@@ -241,7 +280,10 @@ end
*/ */
initial begin initial begin
#150000; #150000;
$display("[Test] Failed"); // $display("[Test]: Failed");
TEST_TITLE = "Failed (timelimit)";
$display("[Test]: %s @%t", TEST_TITLE, $time);
$display("============= TIMELIMIT ============="); $display("============= TIMELIMIT =============");
$finish; $finish;
end end
wrapper/gtxe2_channel_wrapper.v
View file @ 6efdc1f7
...@@ -18,6 +18,7 @@ ...@@ -18,6 +18,7 @@
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> . * along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/ *******************************************************************************/
`include "system_defines.vh"
module gtxe2_channel_wrapper( module gtxe2_channel_wrapper(
// clocking ports, UG476 p.37 // clocking ports, UG476 p.37
input [2:0] CPLLREFCLKSEL, input [2:0] CPLLREFCLKSEL,
......
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