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x393_sata
Commit 6a13fd70 authored by Alexey Grebenkin's avatar Alexey Grebenkin
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intermediate changes

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axi_regs.v
View file @ 6a13fd70
...@@ -43,7 +43,12 @@ ...@@ -43,7 +43,12 @@
*/ */
`include "axibram_read.v" `include "axibram_read.v"
`include "axibram_write.v" `include "axibram_write.v"
module axi_regs( `include "membridge.v"
`include "send_dma.v"
module axi_regs #(
parameter REGISTERS_CNT = 20
)
(
input wire ACLK, // AXI PS Master GP1 Clock , input input wire ACLK, // AXI PS Master GP1 Clock , input
input wire ARESETN, // AXI PS Master GP1 Reset, output input wire ARESETN, // AXI PS Master GP1 Reset, output
// AXI PS Master GP1: Read Address // AXI PS Master GP1: Read Address
...@@ -88,12 +93,25 @@ module axi_regs( ...@@ -88,12 +93,25 @@ module axi_regs(
output wire BVALID, // AXI PS Master GP1 BVALID, input output wire BVALID, // AXI PS Master GP1 BVALID, input
input wire BREADY, // AXI PS Master GP1 BREADY, output input wire BREADY, // AXI PS Master GP1 BREADY, output
output wire [11:0] BID, // AXI PS Master GP1 BID[11:0], input output wire [11:0] BID, // AXI PS Master GP1 BID[11:0], input
output wire [1:0] BRESP // AXI PS Master GP1 BRESP[1:0], input output wire [1:0] BRESP, // AXI PS Master GP1 BRESP[1:0], input
// temporary registers output
output wire [32*REGISTERS_CNT - 1:0] outmem,
output wire clrstart
); );
// register set // register set
//reg [31:0] mem [3:0]; //reg [31:0] mem [3:0];
reg [32*16 - 1:0] mem; /*
* DMA write:
* 0x10: addr of the buffer
* 0x14: size
* 0x18: burst len
* 0x1c:
* 0x20-0x3c - data
*/
reg [32*REGISTERS_CNT - 1:0] mem;
assign outmem = mem;
`ifndef MAXI_NEW_IFACE `ifndef MAXI_NEW_IFACE
/* /*
* Converntional MAXI interface from x393 project, uses fifos, writes to/reads from memory * Converntional MAXI interface from x393 project, uses fifos, writes to/reads from memory
...@@ -112,8 +130,17 @@ wire bram_regen; ...@@ -112,8 +130,17 @@ wire bram_regen;
// later on will try to use them as an application level registers // later on will try to use them as an application level registers
genvar ii; genvar ii;
generate generate
for (ii = 0; ii < 16; ii = ii + 1) for (ii = 0; ii < REGISTERS_CNT; ii = ii + 1)
begin: write_to_mem begin: write_to_mem
if (ii == 7) // for some reason expression (clrstart & (ii == 7)) ? is not working
always @ (posedge ACLK)
begin
mem[32*ii + 31-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[31-:8] & {8{bram_wstb[3]}}: clrstart ? 8'h0 : mem[32*ii + 31-:8];
mem[32*ii + 23-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[23-:8] & {8{bram_wstb[2]}}: clrstart ? 8'h0 : mem[32*ii + 23-:8];
mem[32*ii + 15-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[15-:8] & {8{bram_wstb[1]}}: clrstart ? 8'h0 : mem[32*ii + 15-:8];
mem[32*ii + 7-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[ 7-:8] & {8{bram_wstb[0]}}: clrstart ? 8'h0 : mem[32*ii + 7-:8];
end
else
always @ (posedge ACLK) always @ (posedge ACLK)
begin begin
mem[32*ii + 31-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[31-:8] & {8{bram_wstb[3]}}: mem[32*ii + 31-:8]; mem[32*ii + 31-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[31-:8] & {8{bram_wstb[3]}}: mem[32*ii + 31-:8];
...@@ -161,7 +188,7 @@ axibram_write( ...@@ -161,7 +188,7 @@ axibram_write(
.start_burst (), .start_burst (),
.dev_ready (1'b1), .dev_ready (1'b1),
.bram_wclk (), .bram_wclk (),
.bram_waddr (bram_waddr), .bram_waddr (bram_waddr[15:0]),
.bram_wen (bram_wen), .bram_wen (bram_wen),
.bram_wstb (bram_wstb), .bram_wstb (bram_wstb),
.bram_wdata (bram_wdata) .bram_wdata (bram_wdata)
...@@ -189,7 +216,7 @@ axibram_read( ...@@ -189,7 +216,7 @@ axibram_read(
.start_burst (), .start_burst (),
.dev_ready (1'b1), .dev_ready (1'b1),
.bram_rclk (), .bram_rclk (),
.bram_raddr (bram_raddr), .bram_raddr (bram_raddr[15:0]),
.bram_ren (bram_ren), .bram_ren (bram_ren),
.bram_regen (bram_regen), .bram_regen (bram_regen),
.bram_rdata (bram_rdata) .bram_rdata (bram_rdata)
......
dma_adapter.v 0 → 100644
View file @ 6a13fd70
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simul/build
View file @ 6a13fd70
...@@ -9,7 +9,7 @@ if [ "$UNISIMS_PATH" == '' ] ...@@ -9,7 +9,7 @@ if [ "$UNISIMS_PATH" == '' ]
then then
export UNISIMS_PATH="../../../../eddr3-src/eddr3/unisims" export UNISIMS_PATH="../../../../eddr3-src/eddr3/unisims"
fi fi
iverilog $SATA_PATH/tb/tb_top.v -f opts -stb $1 2>&1| tee $LOGFILE_PATH iverilog $SATA_PATH/tb/tb_top.v $SATA_PATH/x393/glbl.v -f opts -stb -sglbl $1 2>&1| tee $LOGFILE_PATH
#-y$SATA_PATH/x393/util_modules -I$SATA_PATH/x393/ -I$SATA_PATH/x393/axi/ $SATA_PATH/tb/tb_axiregs.v -I$SATA_PATH/ -I$SATA_PATH/tb/ #-y$SATA_PATH/x393/util_modules -I$SATA_PATH/x393/ -I$SATA_PATH/x393/axi/ $SATA_PATH/tb/tb_axiregs.v -I$SATA_PATH/ -I$SATA_PATH/tb/
simul/opts
View file @ 6a13fd70
-v ${SATA_PATH}/x393/simulation_modules/simul_axi_fifo_out.v -v ${SATA_PATH}/x393/simulation_modules/simul_axi_fifo_out.v
-y ${SATA_PATH}/x393/simulation_modules -y ${SATA_PATH}/x393/simulation_modules
-y ${SATA_PATH}/x393/memctrl
-y ${SATA_PATH}/x393/wrap
-y ${UNISIMS_PATH}/ -y ${UNISIMS_PATH}/
-y ${SATA_PATH}/x393/util_modules -y ${SATA_PATH}/x393/util_modules
-v ${SATA_PATH}/x393/axi_hp_clk.v
+incdir+${SATA_PATH}/tb/ +incdir+${SATA_PATH}/tb/
+incdir+${SATA_PATH}/x393/ +incdir+${SATA_PATH}/x393/
+incdir+${SATA_PATH}/x393/axi/ +incdir+${SATA_PATH}/x393/axi/
......
tb/tb_top.v
View file @ 6a13fd70
...@@ -330,12 +330,186 @@ simul_axi_read #( ...@@ -330,12 +330,186 @@ simul_axi_read #(
.burst(), // burst in progress - just debug .burst(), // burst in progress - just debug
.err_out()); // data last does not match predicted or FIFO over/under run - just debug .err_out()); // data last does not match predicted or FIFO over/under run - just debug
`include "includes/x393_tasks01.vh"
// device-under-test instance // device-under-test instance
top dut( top dut(
); );
// SAXI HP interface
// axi_hp simulation signals
wire HCLK;
wire [31:0] afi_sim_rd_address; // output[31:0]
wire [ 5:0] afi_sim_rid; // output[5:0] SuppressThisWarning VEditor - not used - just view
// reg afi_sim_rd_valid; // input
wire afi_sim_rd_valid; // input
wire afi_sim_rd_ready; // output
// reg [63:0] afi_sim_rd_data; // input[63:0]
wire [63:0] afi_sim_rd_data; // input[63:0]
wire [ 2:0] afi_sim_rd_cap; // output[2:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] afi_sim_rd_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view
wire [ 1:0] afi_sim_rd_resp; // input[1:0]
// reg [ 1:0] afi_sim_rd_resp; // input[1:0]
wire [31:0] afi_sim_wr_address; // output[31:0] SuppressThisWarning VEditor - not used - just view
wire [ 5:0] afi_sim_wid; // output[5:0] SuppressThisWarning VEditor - not used - just view
wire afi_sim_wr_valid; // output
wire afi_sim_wr_ready; // input
// reg afi_sim_wr_ready; // input
wire [63:0] afi_sim_wr_data; // output[63:0] SuppressThisWarning VEditor - not used - just view
wire [ 7:0] afi_sim_wr_stb; // output[7:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] afi_sim_bresp_latency; // input[3:0]
// reg [ 3:0] afi_sim_bresp_latency; // input[3:0]
wire [ 2:0] afi_sim_wr_cap; // output[2:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] afi_sim_wr_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view
assign HCLK = dut.ps7_i.SAXIHP3ACLK; // shortcut name
// afi loopback
assign #1 afi_sim_rd_data= afi_sim_rd_ready?{2'h0,afi_sim_rd_address[31:3],1'h1, 2'h0,afi_sim_rd_address[31:3],1'h0}:64'bx;
assign #1 afi_sim_rd_valid = afi_sim_rd_ready;
assign #1 afi_sim_rd_resp = afi_sim_rd_ready?2'b0:2'bx;
assign #1 afi_sim_wr_ready = afi_sim_wr_valid;
assign #1 afi_sim_bresp_latency=4'h5;
// axi_hp register access
// PS memory mapped registers to read/write over a separate simulation bus running at HCLK, no waits
reg [31:0] PS_REG_ADDR;
reg PS_REG_WR;
reg PS_REG_RD;
reg [31:0] PS_REG_DIN;
wire [31:0] PS_REG_DOUT;
reg [31:0] PS_RDATA; // SuppressThisWarning VEditor - not used - just view
/*
reg [31:0] afi_reg_addr;
reg afi_reg_wr;
reg afi_reg_rd;
reg [31:0] afi_reg_din;
wire [31:0] afi_reg_dout;
reg [31:0] AFI_REG_RD; // SuppressThisWarning VEditor - not used - just view
*/
initial begin
PS_REG_ADDR <= 'bx;
PS_REG_WR <= 0;
PS_REG_RD <= 0;
PS_REG_DIN <= 'bx;
PS_RDATA <= 'bx;
end
always @ (posedge HCLK) if (PS_REG_RD) PS_RDATA <= PS_REG_DOUT;
simul_axi_hp_rd #(
.HP_PORT(3)
) simul_axi_hp_rd_i (
.rst (RST), // input
.aclk (dut.ps7_i.SAXIHP3ACLK), // input
.aresetn (), // output
.araddr (dut.ps7_i.SAXIHP3ARADDR[31:0]), // input[31:0]
.arvalid (dut.ps7_i.SAXIHP3ARVALID), // input
.arready (dut.ps7_i.SAXIHP3ARREADY), // output
.arid (dut.ps7_i.SAXIHP3ARID), // input[5:0]
.arlock (dut.ps7_i.SAXIHP3ARLOCK), // input[1:0]
.arcache (dut.ps7_i.SAXIHP3ARCACHE), // input[3:0]
.arprot (dut.ps7_i.SAXIHP3ARPROT), // input[2:0]
.arlen (dut.ps7_i.SAXIHP3ARLEN), // input[3:0]
.arsize (dut.ps7_i.SAXIHP3ARSIZE), // input[2:0]
.arburst (dut.ps7_i.SAXIHP3ARBURST), // input[1:0]
.arqos (dut.ps7_i.SAXIHP3ARQOS), // input[3:0]
.rdata (dut.ps7_i.SAXIHP3RDATA), // output[63:0]
.rvalid (dut.ps7_i.SAXIHP3RVALID), // output
.rready (dut.ps7_i.SAXIHP3RREADY), // input
.rid (dut.ps7_i.SAXIHP3RID), // output[5:0]
.rlast (dut.ps7_i.SAXIHP3RLAST), // output
.rresp (dut.ps7_i.SAXIHP3RRESP), // output[1:0]
.rcount (dut.ps7_i.SAXIHP3RCOUNT), // output[7:0]
.racount (dut.ps7_i.SAXIHP3RACOUNT), // output[2:0]
.rdissuecap1en (dut.ps7_i.SAXIHP3RDISSUECAP1EN), // input
.sim_rd_address (afi_sim_rd_address), // output[31:0]
.sim_rid (afi_sim_rid), // output[5:0]
.sim_rd_valid (afi_sim_rd_valid), // input
.sim_rd_ready (afi_sim_rd_ready), // output
.sim_rd_data (afi_sim_rd_data), // input[63:0]
.sim_rd_cap (afi_sim_rd_cap), // output[2:0]
.sim_rd_qos (afi_sim_rd_qos), // output[3:0]
.sim_rd_resp (afi_sim_rd_resp), // input[1:0]
.reg_addr (PS_REG_ADDR), // input[31:0]
.reg_wr (PS_REG_WR), // input
.reg_rd (PS_REG_RD), // input
.reg_din (PS_REG_DIN), // input[31:0]
.reg_dout (PS_REG_DOUT) // output[31:0]
);
simul_axi_hp_wr #(
.HP_PORT(3)
) simul_axi_hp_wr_i (
.rst (RST), // input
.aclk (dut.ps7_i.SAXIHP3ACLK), // input
.aresetn (), // output
.awaddr (dut.ps7_i.SAXIHP3AWADDR), // input[31:0]
.awvalid (dut.ps7_i.SAXIHP3AWVALID), // input
.awready (dut.ps7_i.SAXIHP3AWREADY), // output
.awid (dut.ps7_i.SAXIHP3AWID), // input[5:0]
.awlock (dut.ps7_i.SAXIHP3AWLOCK), // input[1:0]
.awcache (dut.ps7_i.SAXIHP3AWCACHE), // input[3:0]
.awprot (dut.ps7_i.SAXIHP3AWPROT), // input[2:0]
.awlen (dut.ps7_i.SAXIHP3AWLEN), // input[3:0]
.awsize (dut.ps7_i.SAXIHP3AWSIZE), // input[2:0]
.awburst (dut.ps7_i.SAXIHP3AWBURST), // input[1:0]
.awqos (dut.ps7_i.SAXIHP3AWQOS), // input[3:0]
.wdata (dut.ps7_i.SAXIHP3WDATA), // input[63:0]
.wvalid (dut.ps7_i.SAXIHP3WVALID), // input
.wready (dut.ps7_i.SAXIHP3WREADY), // output
.wid (dut.ps7_i.SAXIHP3WID), // input[5:0]
.wlast (dut.ps7_i.SAXIHP3WLAST), // input
.wstrb (dut.ps7_i.SAXIHP3WSTRB), // input[7:0]
.bvalid (dut.ps7_i.SAXIHP3BVALID), // output
.bready (dut.ps7_i.SAXIHP3BREADY), // input
.bid (dut.ps7_i.SAXIHP3BID), // output[5:0]
.bresp (dut.ps7_i.SAXIHP3BRESP), // output[1:0]
.wcount (dut.ps7_i.SAXIHP3WCOUNT), // output[7:0]
.wacount (dut.ps7_i.SAXIHP3WACOUNT), // output[5:0]
.wrissuecap1en (dut.ps7_i.SAXIHP3WRISSUECAP1EN), // input
.sim_wr_address (afi_sim_wr_address), // output[31:0]
.sim_wid (afi_sim_wid), // output[5:0]
.sim_wr_valid (afi_sim_wr_valid), // output
.sim_wr_ready (afi_sim_wr_ready), // input
.sim_wr_data (afi_sim_wr_data), // output[63:0]
.sim_wr_stb (afi_sim_wr_stb), // output[7:0]
.sim_bresp_latency(afi_sim_bresp_latency), // input[3:0]
.sim_wr_cap (afi_sim_wr_cap), // output[2:0]
.sim_wr_qos (afi_sim_wr_qos), // output[3:0]
.reg_addr (PS_REG_ADDR), // input[31:0]
.reg_wr (PS_REG_WR), // input
.reg_rd (PS_REG_RD), // input
.reg_din (PS_REG_DIN), // input[31:0]
.reg_dout (PS_REG_DOUT) // output[31:0]
);
// wire [ 3:0] SIMUL_ADD_ADDR;
always @ (posedge CLK) begin
if (RST) SIMUL_AXI_FULL <=0;
else if (rstb) SIMUL_AXI_FULL <=1;
if (RST) begin
NUM_WORDS_READ <= 0;
end else if (rstb) begin
NUM_WORDS_READ <= NUM_WORDS_READ + 1;
end
if (rstb) begin
SIMUL_AXI_ADDR <= SIMUL_AXI_ADDR_W;
SIMUL_AXI_READ <= rdata;
`ifdef DEBUG_RD_DATA
$display (" Read data (addr:data): 0x%x:0x%x @%t",SIMUL_AXI_ADDR_W,rdata,$time);
`endif
end
end
//tasks
`include "includes/x393_tasks01.vh"
`include "includes/x393_tasks_afi.vh"
// testing itself // testing itself
`include "test_top.v" `include "test_top.v"
......
tb/test_top.v
View file @ 6a13fd70
...@@ -41,14 +41,25 @@ begin ...@@ -41,14 +41,25 @@ begin
repeat (20) repeat (20)
@ (posedge CLK); @ (posedge CLK);
// test MAXI1 inface
axi_set_rd_lag(0); axi_set_rd_lag(0);
axi_write_single(32'h4, 32'hdeadbeef); axi_write_single(32'h4, 32'hdeadbeef);
axi_read_addr(12'h777, 32'h4, 4'h3, 2'b01); axi_read_addr(12'h777, 32'h4, 4'h3, 2'b01);
repeat (7) repeat (7)
@ (posedge CLK); @ (posedge CLK);
axi_write_single(32'h8, 32'hd34db33f); axi_write_single(32'h8, 32'hd34db33f);
axi_read_addr(12'h555, 32'h0, 4'h3, 2'b01); axi_read_addr(12'h555, 32'h0, 4'h3, 2'b01);
// test SAXI3 iface
afi_setup(3);
axi_write_single(32'h10, 32'h0add9e55 >> 3); // addr
axi_write_single(32'h14, 32'h00000010); // size
axi_write_single(32'h18, 32'h00000010); // burst_len
axi_write_single(32'h20, 32'hdeadbee0); // data
axi_write_single(32'h24, 32'hdeadbee1); // data
axi_write_single(32'h28, 32'hdeadbee2); // data
axi_write_single(32'h2c, 32'hdeadbee3); // data
axi_write_single(32'h1c, 32'hffffffff); // start
end end
initial initial
......
top.v
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top_axi_regs.v 0 → 100644
View file @ 6a13fd70
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