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x393_sata
Commit 6a13fd70 authored by Alexey Grebenkin's avatar Alexey Grebenkin
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intermediate changes

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axi_regs.v
View file @ 6a13fd70
...@@ -43,7 +43,12 @@ ...@@ -43,7 +43,12 @@
*/ */
`include "axibram_read.v" `include "axibram_read.v"
`include "axibram_write.v" `include "axibram_write.v"
module axi_regs( `include "membridge.v"
`include "send_dma.v"
module axi_regs #(
parameter REGISTERS_CNT = 20
)
(
input wire ACLK, // AXI PS Master GP1 Clock , input input wire ACLK, // AXI PS Master GP1 Clock , input
input wire ARESETN, // AXI PS Master GP1 Reset, output input wire ARESETN, // AXI PS Master GP1 Reset, output
// AXI PS Master GP1: Read Address // AXI PS Master GP1: Read Address
...@@ -88,12 +93,25 @@ module axi_regs( ...@@ -88,12 +93,25 @@ module axi_regs(
output wire BVALID, // AXI PS Master GP1 BVALID, input output wire BVALID, // AXI PS Master GP1 BVALID, input
input wire BREADY, // AXI PS Master GP1 BREADY, output input wire BREADY, // AXI PS Master GP1 BREADY, output
output wire [11:0] BID, // AXI PS Master GP1 BID[11:0], input output wire [11:0] BID, // AXI PS Master GP1 BID[11:0], input
output wire [1:0] BRESP // AXI PS Master GP1 BRESP[1:0], input output wire [1:0] BRESP, // AXI PS Master GP1 BRESP[1:0], input
// temporary registers output
output wire [32*REGISTERS_CNT - 1:0] outmem,
output wire clrstart
); );
// register set // register set
//reg [31:0] mem [3:0]; //reg [31:0] mem [3:0];
reg [32*16 - 1:0] mem; /*
* DMA write:
* 0x10: addr of the buffer
* 0x14: size
* 0x18: burst len
* 0x1c:
* 0x20-0x3c - data
*/
reg [32*REGISTERS_CNT - 1:0] mem;
assign outmem = mem;
`ifndef MAXI_NEW_IFACE `ifndef MAXI_NEW_IFACE
/* /*
* Converntional MAXI interface from x393 project, uses fifos, writes to/reads from memory * Converntional MAXI interface from x393 project, uses fifos, writes to/reads from memory
...@@ -112,15 +130,24 @@ wire bram_regen; ...@@ -112,15 +130,24 @@ wire bram_regen;
// later on will try to use them as an application level registers // later on will try to use them as an application level registers
genvar ii; genvar ii;
generate generate
for (ii = 0; ii < 16; ii = ii + 1) for (ii = 0; ii < REGISTERS_CNT; ii = ii + 1)
begin: write_to_mem begin: write_to_mem
always @ (posedge ACLK) if (ii == 7) // for some reason expression (clrstart & (ii == 7)) ? is not working
begin always @ (posedge ACLK)
mem[32*ii + 31-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[31-:8] & {8{bram_wstb[3]}}: mem[32*ii + 31-:8]; begin
mem[32*ii + 23-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[23-:8] & {8{bram_wstb[2]}}: mem[32*ii + 23-:8]; mem[32*ii + 31-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[31-:8] & {8{bram_wstb[3]}}: clrstart ? 8'h0 : mem[32*ii + 31-:8];
mem[32*ii + 15-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[15-:8] & {8{bram_wstb[1]}}: mem[32*ii + 15-:8]; mem[32*ii + 23-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[23-:8] & {8{bram_wstb[2]}}: clrstart ? 8'h0 : mem[32*ii + 23-:8];
mem[32*ii + 7-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[ 7-:8] & {8{bram_wstb[0]}}: mem[32*ii + 7-:8]; mem[32*ii + 15-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[15-:8] & {8{bram_wstb[1]}}: clrstart ? 8'h0 : mem[32*ii + 15-:8];
end mem[32*ii + 7-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[ 7-:8] & {8{bram_wstb[0]}}: clrstart ? 8'h0 : mem[32*ii + 7-:8];
end
else
always @ (posedge ACLK)
begin
mem[32*ii + 31-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[31-:8] & {8{bram_wstb[3]}}: mem[32*ii + 31-:8];
mem[32*ii + 23-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[23-:8] & {8{bram_wstb[2]}}: mem[32*ii + 23-:8];
mem[32*ii + 15-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[15-:8] & {8{bram_wstb[1]}}: mem[32*ii + 15-:8];
mem[32*ii + 7-:8] <= bram_wen & (bram_waddr[3:0] == ii) ? bram_wdata[ 7-:8] & {8{bram_wstb[0]}}: mem[32*ii + 7-:8];
end
end end
endgenerate endgenerate
...@@ -161,7 +188,7 @@ axibram_write( ...@@ -161,7 +188,7 @@ axibram_write(
.start_burst (), .start_burst (),
.dev_ready (1'b1), .dev_ready (1'b1),
.bram_wclk (), .bram_wclk (),
.bram_waddr (bram_waddr), .bram_waddr (bram_waddr[15:0]),
.bram_wen (bram_wen), .bram_wen (bram_wen),
.bram_wstb (bram_wstb), .bram_wstb (bram_wstb),
.bram_wdata (bram_wdata) .bram_wdata (bram_wdata)
...@@ -189,7 +216,7 @@ axibram_read( ...@@ -189,7 +216,7 @@ axibram_read(
.start_burst (), .start_burst (),
.dev_ready (1'b1), .dev_ready (1'b1),
.bram_rclk (), .bram_rclk (),
.bram_raddr (bram_raddr), .bram_raddr (bram_raddr[15:0]),
.bram_ren (bram_ren), .bram_ren (bram_ren),
.bram_regen (bram_regen), .bram_regen (bram_regen),
.bram_rdata (bram_rdata) .bram_rdata (bram_rdata)
......
dma_adapter.v 0 → 100644
View file @ 6a13fd70
/*******************************************************************************
* Module: dma_adapter
* Date: 2015-07-11
* Author: Alexey
* Description: temporary interconnect to membridge testing purposes only
*
* Copyright (c) 2015 Elphel, Inc.
* dma_adapter.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dma_adapter.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
/*
* The module is temporary
* It could make transactions from DMA data buffer to membridge and vice versa.
* Processes 1 transaction of 16 x 64bit-words at a time.
* Waits until 1 read or 1 write is completely done.
* After that it deasserts busy and is ready to process a new transaction.
*
* The whole purpose of a module as a system block is to be a buffer between
* a big dma data storage and axi interface. So it shall recieve data and control
* for 1 burst and pass it to axi.
*/
/*
* For debug only:
* DMA write:
* 0x0c: |mem[:] => use dbg registers as a source of dma data
* 0x10: addr of the buffer
* 0x14: size
* 0x18: burst len
* 0x1c: start dma
* 0x20-0x3c - data
*/
module send_dma #(
parameter REGISTERS_CNT = 20
)
(
input wire clk,
input wire rst,
// dbg iface
input wire [32*REGISTERS_CNT - 1:0] mem,
input wire dbg_mode,
output wire clrstart,
// cmd iface
input wire cmd_type, // 1 = wr, 0 = rd
input wire cmd_val, // issue a cmd
input wire [31:7] cmd_addr, // [2:0] - 64-bit (8-bytes) word offset, [6:3] - 16-words transfer offset
output wire cmd_busy, // no-pipelined cmd execution, 1 cmd at a time
// data iface
input wire [63:0] wr_data_in,
output wire wr_val_out,
output wire [63:0] rd_data_out,
input wire rd_val_in,
// membridge iface
output wire [7:0] cmd_ad,
output wire cmd_stb,
input wire [7:0] status_ad,
input wire status_rq,
output wire status_start,
input wire frame_start_chn,
input wire next_page_chn,
output wire cmd_wrmem,
output wire page_ready_chn,
output wire frame_done_chn,
output wire [15:0] line_unfinished_chn1,
input wire suspend_chn1,
output wire xfer_reset_page_rd,
output wire buf_wpage_nxt,
output wire buf_wr,
output wire [63:0] buf_wdata,
output wire xfer_reset_page_wr,
output wire buf_rpage_nxt,
output wire buf_rd,
input wire [63:0] buf_rdata,
// additinal wire to indicate if membridge recieved a packet
input wire rdata_done // = membridge.is_last_in_page & membridge.afi_rready;
);
// cmd handling
// if not busy and got cmd with val => cmd recieved, assert busy, start a respective algorithm
wire wr_start;
wire rd_start;
reg wr_done;
reg rd_done;
reg cmd_type_r;
reg cmd_addr_r;
reg cmd_val_r;
reg cmd_busy_r;
wire set_busy;
wire clr_busy;
assign set_busy = ~cmd_busy_r & cmd_val;
assign clr_busy = cmd_busy_r & (wr_done | rd_done)
always @ (posedge clk)
begin
cmd_type_r <= rst ? 1'b0 :
cmd_addr_r <= rst ? 1'b0 :
cmd_val_r <= rst ? 1'b0 :
cmd_busy_r <= rst ? 1'b0 : ~cmd_busy_r & cmd_val_r
end
/*
* Read/write state machine
* For better readability the state machine is splitted to two pieces:
* the first one is responsible only for the CMD WRITE case handling,
* the second one, respectively, for CMD READ
*
* Each fsm starts a membridge fsm, which, if being 1st time launched, sets up
* membridge's registers, or, if have been launched before, just programs read/write
* address.
*
* Current implementation is extremely slow, but simple and reliable
* After all other parts are implemented and this place occurs to be a bottleneck
* then replace it (and may be membridge too) with something more ... pipelined
*/
reg [1:0] rdwr_state;
// Get data from buffer
localparam READ_IDLE = 0;
localparam READ_ON = 2;
localparam READ_DATA = 3;
reg rd_reset_page;
reg rd_next_page;
reg rd_data
always @ (posedge clk)
if (rst)
begin
rd_state <= READ_IDLE;
rd_done <=
end
else
case (rst)
READ_IDLE:
begin
end
READ_ON:
begin
end
// Put data into buffer
localparam WRITE_IDLE = 0;
localparam WRITE_ON = 1;
reg wr_en;
reg wr_reset_page;
reg wr_next_page;
reg [63:0] wr_data;
reg [6:0] wr_page_offset;
reg wr_page_ready;
reg wr_val;
wire [31:0] dw0 = mem[32*9-1:32*8];
wire [31:0] dw1 = mem[32*10-1:32*9];
wire [31:0] dw2 = mem[32*11-1:32*10];
wire [31:0] dw3 = mem[32*12-1:32*11];
wire [6:0] wr_cnt_to_push;
wire wr_stop;
assign wr_cnt_to_push = 7'hf;
assign wr_stop = wr_page_offset == wr_cnt_to_push;
assign wr_val_in = wr_val;
assign wr_data_in = wr_data;
// assuming for now we write only pre-defined 16 64-bit words
always @ (posedge clk)
if (rst)
begin
wr_done <= 1'b0;
wr_page_offset <= 7'd0;
wr_val <= 1'b0;
wr_data <= 64'h0;
wr_next_page <= 1'b0;
wr_reset_page <= 1'b0;
wr_en <= 1'b0;
wr_page_ready <= 1'b0;
rdwr_state <= WRITE_IDLE;
end
else
case (wr_state)
WRITE_IDLE:
begin
wr_page_offset <= 7'd0;
wr_done <= 1'b0;
wr_val <= 1'b0;
wr_data <= 64'h0;
wr_next_page <= 1'b0;
wr_reset_page <= wr_start ? 1'b1 : 1'b0;
wr_en <= 1'b0;
wr_page_ready <= 1'b0;
rdwr_state <= wr_start ? WRITE_ON : WRITE_IDLE;
end
WRITE_ON:
begin
wr_done <= wr_stop ? 1'b1 : 1'b0;
wr_page_offset <= wr_page_offset + 1'b1;
wr_val <= 1'b1;
wr_data <= ~dbg_mode ? in_data :
wr_page_offset[1:0] == 2'b00 ? {dw0, 25'h0, wr_page_offset} :
wr_page_offset[1:0] == 2'b01 ? {dw1, 25'h0, wr_page_offset} :
wr_page_offset[1:0] == 2'b10 ? {dw2, 25'h0, wr_page_offset} :
{dw3, 25'h0, wr_page_offset};
wr_next_page <= wr_stop ? 1'b1 : 1'b0;
wr_reset_page <= 1'b0;
wr_en <= 1'b1;
wr_page_ready <= wr_stop ? 1'b1 : 1'b0;
rdwr_state <= wr_stop ? WRITE_IDLE : WRITE_ON;
end
default: // read is executed
begin
wr_done <= 1'b0;
wr_page_offset <= 7'd0;
wr_val <= 1'b0;
wr_data <= 64'h0;
wr_next_page <= 1'b0;
wr_reset_page <= 1'b0;
wr_en <= 1'b0;
wr_page_ready <= 1'b0;
rdwr_state <= rdwr_state;
end
endcase
// temporary assigments
assign status_start = 1'b0; // no need until status is used
assign cmd_wrmem = 1'b0; // for now only writing
assign xfer_reset_page_wr = 1'b0; // for now only writing
assign buf_rpage_nxt = 1'b0; // for now only writing
assign buf_rd = 1'b0; // for now only writing
assign xfer_reset_page_wr = 1'b0;
assign buf_wdata = wr_data;
assign buf_wr = wr_en;
assign buf_wpage_nxt = wr_next_page;
assign xfer_reset_page_rd = wr_reset_page;
assign page_ready_chn = cmd_wrmem ? 1'b0 : wr_page_ready;
assign frame_done_chn = 1'b1;
// compute membridge parameters to corresponding mem register
// dma fsm
// mode = 0
// width = 4
// size = 0x14
// start = 0
// lo_address = 0x10
// ctrl = 0x1c
// len = 0x18
localparam MEMBR_IDLE = 0;
localparam MEMBR_MODE = 1;
localparam MEMBR_WIDTH = 2;
localparam MEMBR_LEN = 3;
localparam MEMBR_START = 4;
localparam MEMBR_SIZE = 5;
localparam MEMBR_LOADDR = 6;
localparam MEMBR_CTRL = 7;
reg [32:0] membr_data;
reg [15:0] membr_addr;
reg membr_start;
reg membr_done;
reg [2:0] membr_state;
reg membr_setup; // indicates the first tick of the state
wire membr_inprocess;
wire dma_start;
assign dma_start = |mem[32*8-1:32*7];
assign clrstart = dma_start & membr_state == MEMBR_IDLE;
//assign wr_start = membr_state == MEMBR_CTRL;
always @ (posedge clk)
if (rst)
begin
membr_data <= 32'h0;
membr_addr <= 16'h0;
membr_start <= 1'b0;
membr_setup <= 1'b0;
membr_state <= MEMBR_IDLE;
end
else
case (membr_state)
MEMBR_IDLE:
begin
membr_data <= 32'h0;
membr_addr <= 16'h200;
membr_start <= dma_start ? 1'b1 : 1'b0;
membr_setup <= dma_start ? 1'b1 : 1'b0;
membr_state <= dma_start ? MEMBR_MODE : MEMBR_IDLE;
end
MEMBR_MODE:
begin
membr_data <= 32'h3;
membr_addr <= 16'h207;
membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1;
membr_state <= membr_inprocess | membr_setup ? MEMBR_MODE : MEMBR_WIDTH;
end
MEMBR_WIDTH:
begin
membr_data <= 32'h10;
membr_addr <= 16'h206;
membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1;
membr_state <= membr_inprocess | membr_setup ? MEMBR_WIDTH : MEMBR_LEN;
end
MEMBR_LEN:
begin
membr_data <= 32'h10;
membr_addr <= 16'h205;
membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1;
membr_state <= membr_inprocess | membr_setup ? MEMBR_LEN : MEMBR_START;
end
MEMBR_START:
begin
membr_data <= 32'h0;
membr_addr <= 16'h204;
membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1;
membr_state <= membr_inprocess | membr_setup ? MEMBR_START : MEMBR_SIZE;
end
MEMBR_SIZE:
begin
membr_data <= 32'h10;
membr_addr <= 16'h203;
membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1;
membr_state <= membr_inprocess | membr_setup ? MEMBR_SIZE : MEMBR_LOADDR;
end
MEMBR_LOADDR:
begin
membr_data <= mem[32*5-1:32*4];
membr_addr <= 16'h202;
membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1;
membr_state <= membr_inprocess | membr_setup ? MEMBR_LOADDR : MEMBR_CTRL;
end
MEMBR_CTRL:
begin
membr_data <= {28'h0000000, 4'b0011};
membr_addr <= 16'h200;
membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= 1'b0;
membr_state <= membr_inprocess | membr_setup ? MEMBR_CTRL : MEMBR_IDLE;
end
default:
begin
membr_data <= 32'h0;
membr_addr <= 16'h0;
membr_start <= 1'b0;
membr_setup <= 1'b0;
membr_state <= MEMBR_IDLE;
end
endcase
// write to memridge registers fsm
localparam STATE_IDLE = 3'h0;
localparam STATE_CMD_0 = 3'h1;
localparam STATE_CMD_1 = 3'h2;
localparam STATE_DATA_0 = 3'h3;
localparam STATE_DATA_1 = 3'h4;
localparam STATE_DATA_2 = 3'h5;
localparam STATE_DATA_3 = 3'h6;
reg [2:0] state;
reg [7:0] out_ad;
reg out_stb;
assign membr_inprocess = state != STATE_IDLE;
assign cmd_ad = out_ad;
assign cmd_stb = out_stb;
always @ (posedge clk)
if (rst)
begin
membr_done <= 1'b0;
state <= STATE_IDLE;
out_ad <= 8'h0;
out_stb <= 1'b0;
end
else
case (state)
STATE_IDLE:
begin
membr_done <= 1'b0;
out_ad <= 8'h0;
out_stb <= 1'b0;
state <= membr_setup ? STATE_CMD_0 : STATE_IDLE;
end
STATE_CMD_0:
begin
membr_done <= 1'b0;
out_ad <= membr_addr[7:0];
out_stb <= 1'b1;
state <= STATE_CMD_1;
end
STATE_CMD_1:
begin
membr_done <= 1'b0;
out_ad <= membr_addr[15:8];
out_stb <= 1'b0;
state <= STATE_DATA_0;
end
STATE_DATA_0:
begin
membr_done <= 1'b0;
out_ad <= membr_data[7:0];
out_stb <= 1'b0;
state <= STATE_DATA_1;
end
STATE_DATA_1:
begin
membr_done <= 1'b0;
out_ad <= membr_data[15:8];
out_stb <= 1'b0;
state <= STATE_DATA_2;
end
STATE_DATA_2:
begin
membr_done <= 1'b0;
out_ad <= membr_data[23:16];
out_stb <= 1'b0;
state <= STATE_DATA_3;
end
STATE_DATA_3:
begin
membr_done <= 1'b0;
out_ad <= membr_data[31:24];
out_stb <= 1'b0;
state <= STATE_IDLE;
end
default:
begin
membr_done <= 1'b1;
out_ad <= 8'hff;
out_stb <= 1'b0;
state <= STATE_IDLE;
end
endcase
endmodule
simul/build
View file @ 6a13fd70
...@@ -9,7 +9,7 @@ if [ "$UNISIMS_PATH" == '' ] ...@@ -9,7 +9,7 @@ if [ "$UNISIMS_PATH" == '' ]
then then
export UNISIMS_PATH="../../../../eddr3-src/eddr3/unisims" export UNISIMS_PATH="../../../../eddr3-src/eddr3/unisims"
fi fi
iverilog $SATA_PATH/tb/tb_top.v -f opts -stb $1 2>&1| tee $LOGFILE_PATH iverilog $SATA_PATH/tb/tb_top.v $SATA_PATH/x393/glbl.v -f opts -stb -sglbl $1 2>&1| tee $LOGFILE_PATH
#-y$SATA_PATH/x393/util_modules -I$SATA_PATH/x393/ -I$SATA_PATH/x393/axi/ $SATA_PATH/tb/tb_axiregs.v -I$SATA_PATH/ -I$SATA_PATH/tb/ #-y$SATA_PATH/x393/util_modules -I$SATA_PATH/x393/ -I$SATA_PATH/x393/axi/ $SATA_PATH/tb/tb_axiregs.v -I$SATA_PATH/ -I$SATA_PATH/tb/
simul/opts
View file @ 6a13fd70
-v ${SATA_PATH}/x393/simulation_modules/simul_axi_fifo_out.v -v ${SATA_PATH}/x393/simulation_modules/simul_axi_fifo_out.v
-y ${SATA_PATH}/x393/simulation_modules -y ${SATA_PATH}/x393/simulation_modules
-y ${SATA_PATH}/x393/memctrl
-y ${SATA_PATH}/x393/wrap
-y ${UNISIMS_PATH}/ -y ${UNISIMS_PATH}/
-y ${SATA_PATH}/x393/util_modules -y ${SATA_PATH}/x393/util_modules
-v ${SATA_PATH}/x393/axi_hp_clk.v
+incdir+${SATA_PATH}/tb/ +incdir+${SATA_PATH}/tb/
+incdir+${SATA_PATH}/x393/ +incdir+${SATA_PATH}/x393/
+incdir+${SATA_PATH}/x393/axi/ +incdir+${SATA_PATH}/x393/axi/
......
tb/tb_top.v
View file @ 6a13fd70
...@@ -330,12 +330,186 @@ simul_axi_read #( ...@@ -330,12 +330,186 @@ simul_axi_read #(
.burst(), // burst in progress - just debug .burst(), // burst in progress - just debug
.err_out()); // data last does not match predicted or FIFO over/under run - just debug .err_out()); // data last does not match predicted or FIFO over/under run - just debug
`include "includes/x393_tasks01.vh"
// device-under-test instance // device-under-test instance
top dut( top dut(
); );
// SAXI HP interface
// axi_hp simulation signals
wire HCLK;
wire [31:0] afi_sim_rd_address; // output[31:0]
wire [ 5:0] afi_sim_rid; // output[5:0] SuppressThisWarning VEditor - not used - just view
// reg afi_sim_rd_valid; // input
wire afi_sim_rd_valid; // input
wire afi_sim_rd_ready; // output
// reg [63:0] afi_sim_rd_data; // input[63:0]
wire [63:0] afi_sim_rd_data; // input[63:0]
wire [ 2:0] afi_sim_rd_cap; // output[2:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] afi_sim_rd_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view
wire [ 1:0] afi_sim_rd_resp; // input[1:0]
// reg [ 1:0] afi_sim_rd_resp; // input[1:0]
wire [31:0] afi_sim_wr_address; // output[31:0] SuppressThisWarning VEditor - not used - just view
wire [ 5:0] afi_sim_wid; // output[5:0] SuppressThisWarning VEditor - not used - just view
wire afi_sim_wr_valid; // output
wire afi_sim_wr_ready; // input
// reg afi_sim_wr_ready; // input
wire [63:0] afi_sim_wr_data; // output[63:0] SuppressThisWarning VEditor - not used - just view
wire [ 7:0] afi_sim_wr_stb; // output[7:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] afi_sim_bresp_latency; // input[3:0]
// reg [ 3:0] afi_sim_bresp_latency; // input[3:0]
wire [ 2:0] afi_sim_wr_cap; // output[2:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] afi_sim_wr_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view
assign HCLK = dut.ps7_i.SAXIHP3ACLK; // shortcut name
// afi loopback
assign #1 afi_sim_rd_data= afi_sim_rd_ready?{2'h0,afi_sim_rd_address[31:3],1'h1, 2'h0,afi_sim_rd_address[31:3],1'h0}:64'bx;
assign #1 afi_sim_rd_valid = afi_sim_rd_ready;
assign #1 afi_sim_rd_resp = afi_sim_rd_ready?2'b0:2'bx;
assign #1 afi_sim_wr_ready = afi_sim_wr_valid;
assign #1 afi_sim_bresp_latency=4'h5;
// axi_hp register access
// PS memory mapped registers to read/write over a separate simulation bus running at HCLK, no waits
reg [31:0] PS_REG_ADDR;
reg PS_REG_WR;
reg PS_REG_RD;
reg [31:0] PS_REG_DIN;
wire [31:0] PS_REG_DOUT;
reg [31:0] PS_RDATA; // SuppressThisWarning VEditor - not used - just view
/*
reg [31:0] afi_reg_addr;
reg afi_reg_wr;
reg afi_reg_rd;
reg [31:0] afi_reg_din;
wire [31:0] afi_reg_dout;
reg [31:0] AFI_REG_RD; // SuppressThisWarning VEditor - not used - just view
*/
initial begin
PS_REG_ADDR <= 'bx;
PS_REG_WR <= 0;
PS_REG_RD <= 0;
PS_REG_DIN <= 'bx;
PS_RDATA <= 'bx;
end
always @ (posedge HCLK) if (PS_REG_RD) PS_RDATA <= PS_REG_DOUT;
simul_axi_hp_rd #(
.HP_PORT(3)
) simul_axi_hp_rd_i (
.rst (RST), // input
.aclk (dut.ps7_i.SAXIHP3ACLK), // input
.aresetn (), // output
.araddr (dut.ps7_i.SAXIHP3ARADDR[31:0]), // input[31:0]
.arvalid (dut.ps7_i.SAXIHP3ARVALID), // input
.arready (dut.ps7_i.SAXIHP3ARREADY), // output
.arid (dut.ps7_i.SAXIHP3ARID), // input[5:0]
.arlock (dut.ps7_i.SAXIHP3ARLOCK), // input[1:0]
.arcache (dut.ps7_i.SAXIHP3ARCACHE), // input[3:0]
.arprot (dut.ps7_i.SAXIHP3ARPROT), // input[2:0]
.arlen (dut.ps7_i.SAXIHP3ARLEN), // input[3:0]
.arsize (dut.ps7_i.SAXIHP3ARSIZE), // input[2:0]
.arburst (dut.ps7_i.SAXIHP3ARBURST), // input[1:0]
.arqos (dut.ps7_i.SAXIHP3ARQOS), // input[3:0]
.rdata (dut.ps7_i.SAXIHP3RDATA), // output[63:0]
.rvalid (dut.ps7_i.SAXIHP3RVALID), // output
.rready (dut.ps7_i.SAXIHP3RREADY), // input
.rid (dut.ps7_i.SAXIHP3RID), // output[5:0]
.rlast (dut.ps7_i.SAXIHP3RLAST), // output
.rresp (dut.ps7_i.SAXIHP3RRESP), // output[1:0]
.rcount (dut.ps7_i.SAXIHP3RCOUNT), // output[7:0]
.racount (dut.ps7_i.SAXIHP3RACOUNT), // output[2:0]
.rdissuecap1en (dut.ps7_i.SAXIHP3RDISSUECAP1EN), // input
.sim_rd_address (afi_sim_rd_address), // output[31:0]
.sim_rid (afi_sim_rid), // output[5:0]
.sim_rd_valid (afi_sim_rd_valid), // input
.sim_rd_ready (afi_sim_rd_ready), // output
.sim_rd_data (afi_sim_rd_data), // input[63:0]
.sim_rd_cap (afi_sim_rd_cap), // output[2:0]
.sim_rd_qos (afi_sim_rd_qos), // output[3:0]
.sim_rd_resp (afi_sim_rd_resp), // input[1:0]
.reg_addr (PS_REG_ADDR), // input[31:0]
.reg_wr (PS_REG_WR), // input
.reg_rd (PS_REG_RD), // input
.reg_din (PS_REG_DIN), // input[31:0]
.reg_dout (PS_REG_DOUT) // output[31:0]
);
simul_axi_hp_wr #(
.HP_PORT(3)
) simul_axi_hp_wr_i (
.rst (RST), // input
.aclk (dut.ps7_i.SAXIHP3ACLK), // input
.aresetn (), // output
.awaddr (dut.ps7_i.SAXIHP3AWADDR), // input[31:0]
.awvalid (dut.ps7_i.SAXIHP3AWVALID), // input
.awready (dut.ps7_i.SAXIHP3AWREADY), // output
.awid (dut.ps7_i.SAXIHP3AWID), // input[5:0]
.awlock (dut.ps7_i.SAXIHP3AWLOCK), // input[1:0]
.awcache (dut.ps7_i.SAXIHP3AWCACHE), // input[3:0]
.awprot (dut.ps7_i.SAXIHP3AWPROT), // input[2:0]
.awlen (dut.ps7_i.SAXIHP3AWLEN), // input[3:0]
.awsize (dut.ps7_i.SAXIHP3AWSIZE), // input[2:0]
.awburst (dut.ps7_i.SAXIHP3AWBURST), // input[1:0]
.awqos (dut.ps7_i.SAXIHP3AWQOS), // input[3:0]
.wdata (dut.ps7_i.SAXIHP3WDATA), // input[63:0]
.wvalid (dut.ps7_i.SAXIHP3WVALID), // input
.wready (dut.ps7_i.SAXIHP3WREADY), // output
.wid (dut.ps7_i.SAXIHP3WID), // input[5:0]
.wlast (dut.ps7_i.SAXIHP3WLAST), // input
.wstrb (dut.ps7_i.SAXIHP3WSTRB), // input[7:0]
.bvalid (dut.ps7_i.SAXIHP3BVALID), // output
.bready (dut.ps7_i.SAXIHP3BREADY), // input
.bid (dut.ps7_i.SAXIHP3BID), // output[5:0]
.bresp (dut.ps7_i.SAXIHP3BRESP), // output[1:0]
.wcount (dut.ps7_i.SAXIHP3WCOUNT), // output[7:0]
.wacount (dut.ps7_i.SAXIHP3WACOUNT), // output[5:0]
.wrissuecap1en (dut.ps7_i.SAXIHP3WRISSUECAP1EN), // input
.sim_wr_address (afi_sim_wr_address), // output[31:0]
.sim_wid (afi_sim_wid), // output[5:0]
.sim_wr_valid (afi_sim_wr_valid), // output
.sim_wr_ready (afi_sim_wr_ready), // input
.sim_wr_data (afi_sim_wr_data), // output[63:0]
.sim_wr_stb (afi_sim_wr_stb), // output[7:0]
.sim_bresp_latency(afi_sim_bresp_latency), // input[3:0]
.sim_wr_cap (afi_sim_wr_cap), // output[2:0]
.sim_wr_qos (afi_sim_wr_qos), // output[3:0]
.reg_addr (PS_REG_ADDR), // input[31:0]
.reg_wr (PS_REG_WR), // input
.reg_rd (PS_REG_RD), // input
.reg_din (PS_REG_DIN), // input[31:0]
.reg_dout (PS_REG_DOUT) // output[31:0]
);
// wire [ 3:0] SIMUL_ADD_ADDR;
always @ (posedge CLK) begin
if (RST) SIMUL_AXI_FULL <=0;
else if (rstb) SIMUL_AXI_FULL <=1;
if (RST) begin
NUM_WORDS_READ <= 0;
end else if (rstb) begin
NUM_WORDS_READ <= NUM_WORDS_READ + 1;
end
if (rstb) begin
SIMUL_AXI_ADDR <= SIMUL_AXI_ADDR_W;
SIMUL_AXI_READ <= rdata;
`ifdef DEBUG_RD_DATA
$display (" Read data (addr:data): 0x%x:0x%x @%t",SIMUL_AXI_ADDR_W,rdata,$time);
`endif
end
end
//tasks
`include "includes/x393_tasks01.vh"
`include "includes/x393_tasks_afi.vh"
// testing itself // testing itself
`include "test_top.v" `include "test_top.v"
......
tb/test_top.v
View file @ 6a13fd70
...@@ -41,14 +41,25 @@ begin ...@@ -41,14 +41,25 @@ begin
repeat (20) repeat (20)
@ (posedge CLK); @ (posedge CLK);
// test MAXI1 inface
axi_set_rd_lag(0); axi_set_rd_lag(0);
axi_write_single(32'h4, 32'hdeadbeef); axi_write_single(32'h4, 32'hdeadbeef);
axi_read_addr(12'h777, 32'h4, 4'h3, 2'b01); axi_read_addr(12'h777, 32'h4, 4'h3, 2'b01);
repeat (7) repeat (7)
@ (posedge CLK); @ (posedge CLK);
axi_write_single(32'h8, 32'hd34db33f); axi_write_single(32'h8, 32'hd34db33f);
axi_read_addr(12'h555, 32'h0, 4'h3, 2'b01); axi_read_addr(12'h555, 32'h0, 4'h3, 2'b01);
// test SAXI3 iface
afi_setup(3);
axi_write_single(32'h10, 32'h0add9e55 >> 3); // addr
axi_write_single(32'h14, 32'h00000010); // size
axi_write_single(32'h18, 32'h00000010); // burst_len
axi_write_single(32'h20, 32'hdeadbee0); // data
axi_write_single(32'h24, 32'hdeadbee1); // data
axi_write_single(32'h28, 32'hdeadbee2); // data
axi_write_single(32'h2c, 32'hdeadbee3); // data
axi_write_single(32'h1c, 32'hffffffff); // start
end end
initial initial
......
top.v
View file @ 6a13fd70
...@@ -30,10 +30,15 @@ module top #( ...@@ -30,10 +30,15 @@ module top #(
) )
( (
); );
parameter REGISTERS_CNT = 20;
wire [32*REGISTERS_CNT - 1:0] outmem;
wire clrstart;
wire [3:0] fclk; wire [3:0] fclk;
wire [3:0] frst; wire [3:0] frst;
wire axi_aclk; wire axi_aclk;
wire axi_rst; wire axi_rst;
wire hclk;
wire comb_rst; wire comb_rst;
wire [31:0] ARADDR; wire [31:0] ARADDR;
wire ARVALID; wire ARVALID;
...@@ -75,6 +80,74 @@ wire [11:0] BID; ...@@ -75,6 +80,74 @@ wire [11:0] BID;
wire [1:0] BRESP; wire [1:0] BRESP;
reg axi_rst_pre; reg axi_rst_pre;
// membridge
wire [31:0] afi0_awaddr; // output[31:0]
wire afi0_awvalid; // output
wire afi0_awready; // input
wire [ 5:0] afi0_awid; // output[5:0]
wire [ 1:0] afi0_awlock; // output[1:0]
wire [ 3:0] afi0_awcache; // output[3:0]
wire [ 2:0] afi0_awprot; // output[2:0]
wire [ 3:0] afi0_awlen; // output[3:0]
wire [ 2:0] afi0_awsize; // output[2:0]
wire [ 1:0] afi0_awburst; // output[1:0]
wire [ 3:0] afi0_awqos; // output[3:0]
wire [63:0] afi0_wdata; // output[63:0]
wire afi0_wvalid; // output
wire afi0_wready; // input
wire [ 5:0] afi0_wid; // output[5:0]
wire afi0_wlast; // output
wire [ 7:0] afi0_wstrb; // output[7:0]
wire afi0_bvalid; // input
wire afi0_bready; // output
wire [ 5:0] afi0_bid; // input[5:0]
wire [ 1:0] afi0_bresp; // input[1:0]
wire [ 7:0] afi0_wcount; // input[7:0]
wire [ 5:0] afi0_wacount; // input[5:0]
wire afi0_wrissuecap1en; // output
wire [31:0] afi0_araddr; // output[31:0]
wire afi0_arvalid; // output
wire afi0_arready; // input
wire [ 5:0] afi0_arid; // output[5:0]
wire [ 1:0] afi0_arlock; // output[1:0]
wire [ 3:0] afi0_arcache; // output[3:0]
wire [ 2:0] afi0_arprot; // output[2:0]
wire [ 3:0] afi0_arlen; // output[3:0]
wire [ 2:0] afi0_arsize; // output[2:0]
wire [ 1:0] afi0_arburst; // output[1:0]
wire [ 3:0] afi0_arqos; // output[3:0]
wire [63:0] afi0_rdata; // input[63:0]
wire afi0_rvalid; // input
wire afi0_rready; // output
wire [ 5:0] afi0_rid; // input[5:0]
wire afi0_rlast; // input
wire [ 1:0] afi0_rresp; // input[2:0]
wire [ 7:0] afi0_rcount; // input[7:0]
wire [ 2:0] afi0_racount; // input[2:0]
wire afi0_rdissuecap1en; // output
// send_dma
wire [7:0] cmd_ad;
wire cmd_stb;
wire [7:0] status_ad;
wire status_rq;
wire status_start;
wire frame_start_chn;
wire next_page_chn;
wire cmd_wrmem;
wire page_ready_chn;
wire frame_done_chn;
wire [15:0] line_unfinished_chn1;
wire suspend_chn1;
wire xfer_reset_page_rd;
wire buf_wpage_nxt;
wire buf_wr;
wire [63:0] buf_wdata;
wire xfer_reset_page_wr;
wire buf_rpage_nxt;
wire buf_rd;
wire [63:0] buf_rdata;
assign comb_rst=~frst[0] | frst[1]; assign comb_rst=~frst[0] | frst[1];
always @(posedge comb_rst or posedge axi_aclk) begin always @(posedge comb_rst or posedge axi_aclk) begin
if (comb_rst) axi_rst_pre <= 1'b1; if (comb_rst) axi_rst_pre <= 1'b1;
...@@ -83,8 +156,21 @@ end ...@@ -83,8 +156,21 @@ end
BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre)); BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
axi_hp_clk #(
.CLKIN_PERIOD(20),
.CLKFBOUT_MULT_AXIHP(18),
.CLKFBOUT_DIV_AXIHP(6)
) axi_hp_clk_i (
.rst (axi_rst), // input
.clk_in (axi_aclk), // input
.clk_axihp (hclk), // output
.locked_axihp () // output // not controlled?
);
axi_regs axi_regs( axi_regs #(
.REGISTERS_CNT (REGISTERS_CNT)
)
axi_regs(
.ACLK (axi_aclk), .ACLK (axi_aclk),
.ARESETN (axi_rst), .ARESETN (axi_rst),
.ARADDR (ARADDR), .ARADDR (ARADDR),
...@@ -124,7 +210,39 @@ axi_regs axi_regs( ...@@ -124,7 +210,39 @@ axi_regs axi_regs(
.BVALID (BVALID), .BVALID (BVALID),
.BREADY (BREADY), .BREADY (BREADY),
.BID (BID), .BID (BID),
.BRESP (BRESP) .BRESP (BRESP),
.outmem (outmem),
.clrstart (clrstart)
);
dma_adapter #(
.REGISTERS_CNT (REGISTERS_CNT)
)
dma_adapter(
.clk (axi_aclk),
.rst (axi_rst),
.mem (outmem),
.clrstart (clrstart),
.cmd_ad (cmd_ad),
.cmd_stb (cmd_stb),
.status_ad (status_ad),
.status_rq (status_rq),
.status_start (status_start),
.frame_start_chn (frame_start_chn),
.next_page_chn (next_page_chn),
.cmd_wrmem (cmd_wrmem),
.page_ready_chn (page_ready_chn),
.frame_done_chn (frame_done_chn),
.line_unfinished_chn1 (line_unfinished_chn1),
.suspend_chn1 (suspend_chn1),
.xfer_reset_page_rd (xfer_reset_page_rd),
.buf_wpage_nxt (buf_wpage_nxt),
.buf_wr (buf_wr),
.buf_wdata (buf_wdata),
.xfer_reset_page_wr (xfer_reset_page_wr),
.buf_rpage_nxt (buf_rpage_nxt),
.buf_rd (buf_rd),
.buf_rdata (buf_rdata)
); );
PS7 ps7_i ( PS7 ps7_i (
...@@ -744,57 +862,57 @@ PS7 ps7_i ( ...@@ -744,57 +862,57 @@ PS7 ps7_i (
// AXI PS Slave HP3 // AXI PS Slave HP3
// AXI PS Slave HP3: Clock, Reset // AXI PS Slave HP3: Clock, Reset
.SAXIHP3ACLK(), // AXI PS Slave HP3 Clock , input .SAXIHP3ACLK (hclk), // AXI PS Slave HP3 Clock , input
.SAXIHP3ARESETN(), // AXI PS Slave HP3 Reset, output .SAXIHP3ARESETN(), // AXI PS Slave HP3 Reset, output
// AXI PS Slave HP3: Read Address // AXI PS Slave HP3: Read Address
.SAXIHP3ARADDR(), // AXI PS Slave HP3 ARADDR[31:0], input .SAXIHP3ARADDR (afi0_araddr), // AXI PS Slave HP3 ARADDR[31:0], input
.SAXIHP3ARVALID(), // AXI PS Slave HP3 ARVALID, input .SAXIHP3ARVALID (afi0_arvalid), // AXI PS Slave HP3 ARVALID, input
.SAXIHP3ARREADY(), // AXI PS Slave HP3 ARREADY, output .SAXIHP3ARREADY (afi0_arready), // AXI PS Slave HP3 ARREADY, output
.SAXIHP3ARID(), // AXI PS Slave HP3 ARID[5:0], input .SAXIHP3ARID (afi0_arid), // AXI PS Slave HP3 ARID[5:0], input
.SAXIHP3ARLOCK(), // AXI PS Slave HP3 ARLOCK[1:0], input .SAXIHP3ARLOCK (afi0_arlock), // AXI PS Slave HP3 ARLOCK[1:0], input
.SAXIHP3ARCACHE(), // AXI PS Slave HP3 ARCACHE[3:0], input .SAXIHP3ARCACHE (afi0_arcache), // AXI PS Slave HP3 ARCACHE[3:0], input
.SAXIHP3ARPROT(), // AXI PS Slave HP3 ARPROT[2:0], input .SAXIHP3ARPROT (afi0_arprot), // AXI PS Slave HP3 ARPROT[2:0], input
.SAXIHP3ARLEN(), // AXI PS Slave HP3 ARLEN[3:0], input .SAXIHP3ARLEN (afi0_arlen), // AXI PS Slave HP3 ARLEN[3:0], input
.SAXIHP3ARSIZE(), // AXI PS Slave HP3 ARSIZE[2:0], input .SAXIHP3ARSIZE (afi0_arsize), // AXI PS Slave HP3 ARSIZE[2:0], input
.SAXIHP3ARBURST(), // AXI PS Slave HP3 ARBURST[1:0], input .SAXIHP3ARBURST (afi0_arburst), // AXI PS Slave HP3 ARBURST[1:0], input
.SAXIHP3ARQOS(), // AXI PS Slave HP3 ARQOS[3:0], input .SAXIHP3ARQOS (afi0_arqos), // AXI PS Slave HP3 ARQOS[3:0], input
// AXI PS Slave HP3: Read Data // AXI PS Slave HP3: Read Data
.SAXIHP3RDATA(), // AXI PS Slave HP3 RDATA[63:0], output .SAXIHP3RDATA (afi0_rdata), // AXI PS Slave HP3 RDATA[63:0], output
.SAXIHP3RVALID(), // AXI PS Slave HP3 RVALID, output .SAXIHP3RVALID (afi0_rvalid), // AXI PS Slave HP3 RVALID, output
.SAXIHP3RREADY(), // AXI PS Slave HP3 RREADY, input .SAXIHP3RREADY (afi0_rready), // AXI PS Slave HP3 RREADY, input
.SAXIHP3RID(), // AXI PS Slave HP3 RID[5:0], output .SAXIHP3RID (afi0_rid), // AXI PS Slave HP3 RID[5:0], output
.SAXIHP3RLAST(), // AXI PS Slave HP3 RLAST, output .SAXIHP3RLAST (afi0_rlast), // AXI PS Slave HP3 RLAST, output
.SAXIHP3RRESP(), // AXI PS Slave HP3 RRESP[1:0], output .SAXIHP3RRESP (afi0_rresp), // AXI PS Slave HP3 RRESP[1:0], output
.SAXIHP3RCOUNT(), // AXI PS Slave HP3 RCOUNT[7:0], output .SAXIHP3RCOUNT (afi0_rcount), // AXI PS Slave HP3 RCOUNT[7:0], output
.SAXIHP3RACOUNT(), // AXI PS Slave HP3 RACOUNT[2:0], output .SAXIHP3RACOUNT (afi0_racount), // AXI PS Slave HP3 RACOUNT[2:0], output
.SAXIHP3RDISSUECAP1EN(), // AXI PS Slave HP3 RDISSUECAP1EN, input .SAXIHP3RDISSUECAP1EN (afi0_rdissuecap1en), // AXI PS Slave HP3 RDISSUECAP1EN, input
// AXI PS Slave HP3: Write Address // AXI PS Slave HP3: Write Address
.SAXIHP3AWADDR(), // AXI PS Slave HP3 AWADDR[31:0], input .SAXIHP3AWADDR (afi0_awaddr), // AXI PS Slave HP3 AWADDR[31:0], input
.SAXIHP3AWVALID(), // AXI PS Slave HP3 AWVALID, input .SAXIHP3AWVALID (afi0_awvalid), // AXI PS Slave HP3 AWVALID, input
.SAXIHP3AWREADY(), // AXI PS Slave HP3 AWREADY, output .SAXIHP3AWREADY (afi0_awready), // AXI PS Slave HP3 AWREADY, output
.SAXIHP3AWID(), // AXI PS Slave HP3 AWID[5:0], input .SAXIHP3AWID (afi0_awid), // AXI PS Slave HP3 AWID[5:0], input
.SAXIHP3AWLOCK(), // AXI PS Slave HP3 AWLOCK[1:0], input .SAXIHP3AWLOCK (afi0_awlock), // AXI PS Slave HP3 AWLOCK[1:0], input
.SAXIHP3AWCACHE(), // AXI PS Slave HP3 AWCACHE[3:0], input .SAXIHP3AWCACHE (afi0_awcache), // AXI PS Slave HP3 AWCACHE[3:0], input
.SAXIHP3AWPROT(), // AXI PS Slave HP3 AWPROT[2:0], input .SAXIHP3AWPROT (afi0_awprot), // AXI PS Slave HP3 AWPROT[2:0], input
.SAXIHP3AWLEN(), // AXI PS Slave HP3 AWLEN[3:0], input .SAXIHP3AWLEN (afi0_awlen), // AXI PS Slave HP3 AWLEN[3:0], input
.SAXIHP3AWSIZE(), // AXI PS Slave HP3 AWSIZE[1:0], input .SAXIHP3AWSIZE (afi0_awsize), // AXI PS Slave HP3 AWSIZE[1:0], input
.SAXIHP3AWBURST(), // AXI PS Slave HP3 AWBURST[1:0], input .SAXIHP3AWBURST (afi0_awburst), // AXI PS Slave HP3 AWBURST[1:0], input
.SAXIHP3AWQOS(), // AXI PS Slave HP3 AWQOS[3:0], input .SAXIHP3AWQOS (afi0_awqos), // AXI PS Slave HP3 AWQOS[3:0], input
// AXI PS Slave HP3: Write Data // AXI PS Slave HP3: Write Data
.SAXIHP3WDATA(), // AXI PS Slave HP3 WDATA[63:0], input .SAXIHP3WDATA (afi0_wdata), // AXI PS Slave HP3 WDATA[63:0], input
.SAXIHP3WVALID(), // AXI PS Slave HP3 WVALID, input .SAXIHP3WVALID (afi0_wvalid), // AXI PS Slave HP3 WVALID, input
.SAXIHP3WREADY(), // AXI PS Slave HP3 WREADY, output .SAXIHP3WREADY (afi0_wready), // AXI PS Slave HP3 WREADY, output
.SAXIHP3WID(), // AXI PS Slave HP3 WID[5:0], input .SAXIHP3WID (afi0_wid), // AXI PS Slave HP3 WID[5:0], input
.SAXIHP3WLAST(), // AXI PS Slave HP3 WLAST, input .SAXIHP3WLAST (afi0_wlast), // AXI PS Slave HP3 WLAST, input
.SAXIHP3WSTRB(), // AXI PS Slave HP3 WSTRB[7:0], input .SAXIHP3WSTRB (afi0_wstrb), // AXI PS Slave HP3 WSTRB[7:0], input
.SAXIHP3WCOUNT(), // AXI PS Slave HP3 WCOUNT[7:0], output .SAXIHP3WCOUNT (afi0_wcount), // AXI PS Slave HP3 WCOUNT[7:0], output
.SAXIHP3WACOUNT(), // AXI PS Slave HP3 WACOUNT[5:0], output .SAXIHP3WACOUNT (afi0_wacount), // AXI PS Slave HP3 WACOUNT[5:0], output
.SAXIHP3WRISSUECAP1EN(), // AXI PS Slave HP3 WRISSUECAP1EN, input .SAXIHP3WRISSUECAP1EN (afi0_wrissuecap1en), // AXI PS Slave HP3 WRISSUECAP1EN, input
// AXI PS Slave HP3: Write Responce // AXI PS Slave HP3: Write Responce
.SAXIHP3BVALID(), // AXI PS Slave HP3 BVALID, output .SAXIHP3BVALID (afi0_bvalid), // AXI PS Slave HP3 BVALID, output
.SAXIHP3BREADY(), // AXI PS Slave HP3 BREADY, input .SAXIHP3BREADY (afi0_bready), // AXI PS Slave HP3 BREADY, input
.SAXIHP3BID(), // AXI PS Slave HP3 BID[5:0], output .SAXIHP3BID (afi0_bid), // AXI PS Slave HP3 BID[5:0], output
.SAXIHP3BRESP(), // AXI PS Slave HP3 BRESP[1:0], output .SAXIHP3BRESP (afi0_bresp), // AXI PS Slave HP3 BRESP[1:0], output
// AXI PS Slave ACP // AXI PS Slave ACP
// AXI PS Slave ACP: Clock, Reset // AXI PS Slave ACP: Clock, Reset
...@@ -870,4 +988,88 @@ PS7 ps7_i ( ...@@ -870,4 +988,88 @@ PS7 ps7_i (
.PSSRSTB() // PS PSSRSTB, inout .PSSRSTB() // PS PSSRSTB, inout
); );
membridge /*#(
.MEMBRIDGE_ADDR (),
.MEMBRIDGE_MASK (),
.MEMBRIDGE_CTRL (),
.MEMBRIDGE_STATUS_CNTRL (),
.MEMBRIDGE_LO_ADDR64 (),
.MEMBRIDGE_SIZE64 (),
.MEMBRIDGE_START64 (),
.MEMBRIDGE_LEN64 (),
.MEMBRIDGE_WIDTH64 (),
.MEMBRIDGE_MODE (),
.MEMBRIDGE_STATUS_REG (),
.FRAME_HEIGHT_BITS (),
.FRAME_WIDTH_BITS ()
)*/ membridge_i (
.rst (axi_rst), // input
.mclk (axi_aclk), // input
.hclk (hclk), // input
.cmd_ad (cmd_ad),
.cmd_stb (cmd_stb),
.status_ad (status_ad),
.status_rq (status_rq),
.status_start (status_start),
.frame_start_chn (frame_start_chn),
.next_page_chn (next_page_chn),
.cmd_wrmem (cmd_wrmem),
.page_ready_chn (page_ready_chn),
.frame_done_chn (frame_done_chn),
.line_unfinished_chn1 (line_unfinished_chn1),
.suspend_chn1 (suspend_chn1),
.xfer_reset_page_rd (xfer_reset_page_rd),
.buf_wpage_nxt (buf_wpage_nxt),
.buf_wr (buf_wr),
.buf_wdata (buf_wdata),
.xfer_reset_page_wr (xfer_reset_page_wr),
.buf_rpage_nxt (buf_rpage_nxt),
.buf_rd (buf_rd),
.buf_rdata (buf_rdata),
.afi_awaddr (afi0_awaddr), // output[31:0]
.afi_awvalid (afi0_awvalid), // output
.afi_awready (afi0_awready), // input
.afi_awid (afi0_awid), // output[5:0]
.afi_awlock (afi0_awlock), // output[1:0]
.afi_awcache (afi0_awcache), // output[3:0]
.afi_awprot (afi0_awprot), // output[2:0]
.afi_awlen (afi0_awlen), // output[3:0]
.afi_awsize (afi0_awsize), // output[2:0]
.afi_awburst (afi0_awburst), // output[1:0]
.afi_awqos (afi0_awqos), // output[3:0]
.afi_wdata (afi0_wdata), // output[63:0]
.afi_wvalid (afi0_wvalid), // output
.afi_wready (afi0_wready), // input
.afi_wid (afi0_wid), // output[5:0]
.afi_wlast (afi0_wlast), // output
.afi_wstrb (afi0_wstrb), // output[7:0]
.afi_bvalid (afi0_bvalid), // input
.afi_bready (afi0_bready), // output
.afi_bid (afi0_bid), // input[5:0]
.afi_bresp (afi0_bresp), // input[1:0]
.afi_wcount (afi0_wcount), // input[7:0]
.afi_wacount (afi0_wacount), // input[5:0]
.afi_wrissuecap1en (afi0_wrissuecap1en), // output
.afi_araddr (afi0_araddr), // output[31:0]
.afi_arvalid (afi0_arvalid), // output
.afi_arready (afi0_arready), // input
.afi_arid (afi0_arid), // output[5:0]
.afi_arlock (afi0_arlock), // output[1:0]
.afi_arcache (afi0_arcache), // output[3:0]
.afi_arprot (afi0_arprot), // output[2:0]
.afi_arlen (afi0_arlen), // output[3:0]
.afi_arsize (afi0_arsize), // output[2:0]
.afi_arburst (afi0_arburst), // output[1:0]
.afi_arqos (afi0_arqos), // output[3:0]
.afi_rdata (afi0_rdata), // input[63:0]
.afi_rvalid (afi0_rvalid), // input
.afi_rready (afi0_rready), // output
.afi_rid (afi0_rid), // input[5:0]
.afi_rlast (afi0_rlast), // input
.afi_rresp (afi0_rresp), // input[2:0]
.afi_rcount (afi0_rcount), // input[7:0]
.afi_racount (afi0_racount), // input[2:0]
.afi_rdissuecap1en (afi0_rdissuecap1en) // output
);
endmodule endmodule
top_axi_regs.v 0 → 100644
View file @ 6a13fd70
/*******************************************************************************
* Module: top
* Date: 2015-07-11
* Author: Alexey
* Description: top-level module, instantiates PS7 + sata host controller
*
* Copyright (c) 2015 Elphel, Inc.
* top.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* top.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
/*
* all signals' and modules' names and interconnections are taken from x393.v
* to make the final integration easier - just to make an instance of
* what is called now 'axi_regs' and connect it
*/
`include "system_defines.vh"
`include "axi_regs.v"
module top #(
`include "includes/x393_parameters.vh"
)
(
);
wire [3:0] fclk;
wire [3:0] frst;
wire axi_aclk;
wire axi_rst;
wire comb_rst;
wire [31:0] ARADDR;
wire ARVALID;
wire ARREADY;
wire [11:0] ARID;
wire [1:0] ARLOCK;
wire [3:0] ARCACHE;
wire [2:0] ARPROT;
wire [3:0] ARLEN;
wire [1:0] ARSIZE;
wire [1:0] ARBURST;
wire [3:0] ARQOS;
wire [31:0] RDATA;
wire RVALID;
wire RREADY;
wire [11:0] RID;
wire RLAST;
wire [1:0] RRESP;
wire [31:0] AWADDR;
wire AWVALID;
wire AWREADY;
wire [11:0] AWID;
wire [1:0] AWLOCK;
wire [3:0] AWCACHE;
wire [2:0] AWPROT;
wire [3:0] AWLEN;
wire [1:0] AWSIZE;
wire [1:0] AWBURST;
wire [3:0] AWQOS;
wire [31:0] WDATA;
wire WVALID;
wire WREADY;
wire [11:0] WID;
wire WLAST;
wire [3:0] WSTRB;
wire BVALID;
wire BREADY;
wire [11:0] BID;
wire [1:0] BRESP;
reg axi_rst_pre;
assign comb_rst=~frst[0] | frst[1];
always @(posedge comb_rst or posedge axi_aclk) begin
if (comb_rst) axi_rst_pre <= 1'b1;
else axi_rst_pre <= 1'b0;
end
BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
axi_regs axi_regs(
.ACLK (axi_aclk),
.ARESETN (axi_rst),
.ARADDR (ARADDR),
.ARVALID (ARVALID),
.ARREADY (ARREADY),
.ARID (ARID),
.ARLOCK (ARLOCK),
.ARCACHE (ARCACHE),
.ARPROT (ARPROT),
.ARLEN (ARLEN),
.ARSIZE (ARSIZE),
.ARBURST (ARBURST),
.ARQOS (ARQOS),
.RDATA (RDATA),
.RVALID (RVALID),
.RREADY (RREADY),
.RID (RID),
.RLAST (RLAST),
.RRESP (RRESP),
.AWADDR (AWADDR),
.AWVALID (AWVALID),
.AWREADY (AWREADY),
.AWID (AWID),
.AWLOCK (AWLOCK),
.AWCACHE (AWCACHE),
.AWPROT (AWPROT),
.AWLEN (AWLEN),
.AWSIZE (AWSIZE),
.AWBURST (AWBURST),
.AWQOS (AWQOS),
.WDATA (WDATA),
.WVALID (WVALID),
.WREADY (WREADY),
.WID (WID),
.WLAST (WLAST),
.WSTRB (WSTRB),
.BVALID (BVALID),
.BREADY (BREADY),
.BID (BID),
.BRESP (BRESP)
);
PS7 ps7_i (
// EMIO interface
// CAN interface
.EMIOCAN0PHYTX(), // CAN 0 TX, output
.EMIOCAN0PHYRX(), // CAN 0 RX, input
.EMIOCAN1PHYTX(), // Can 1 TX, output
.EMIOCAN1PHYRX(), // CAN 1 RX, input
// GMII 0
.EMIOENET0GMIICRS(), // GMII 0 Carrier sense, input
.EMIOENET0GMIICOL(), // GMII 0 Collision detect, input
.EMIOENET0EXTINTIN(), // GMII 0 Controller Interrupt input, input
// GMII 0 TX signals
.EMIOENET0GMIITXCLK(), // GMII 0 TX clock, input
.EMIOENET0GMIITXD(), // GMII 0 Tx Data[7:0], output
.EMIOENET0GMIITXEN(), // GMII 0 Tx En, output
.EMIOENET0GMIITXER(), // GMII 0 Tx Err, output
// GMII 0 TX timestamp signals
.EMIOENET0SOFTX(), // GMII 0 Tx Tx Start-of-Frame, output
.EMIOENET0PTPDELAYREQTX(), // GMII 0 Tx PTP delay req frame detected, output
.EMIOENET0PTPPDELAYREQTX(), // GMII 0 Tx PTP peer delay frame detect, output
.EMIOENET0PTPPDELAYRESPTX(), // GMII 0 Tx PTP pear delay response frame detected, output
.EMIOENET0PTPSYNCFRAMETX(), // GMII 0 Tx PTP sync frame detected, output
// GMII 0 RX signals
.EMIOENET0GMIIRXCLK(), // GMII 0 Rx Clock, input
.EMIOENET0GMIIRXD(), // GMII 0 Rx Data (7:0), input
.EMIOENET0GMIIRXDV(), // GMII 0 Rx Data valid, input
.EMIOENET0GMIIRXER(), // GMII 0 Rx Error, input
// GMII 0 RX timestamp signals
.EMIOENET0SOFRX(), // GMII 0 Rx Start of Frame, output
.EMIOENET0PTPDELAYREQRX(), // GMII 0 Rx PTP delay req frame detected
.EMIOENET0PTPPDELAYREQRX(), // GMII 0 Rx PTP peer delay frame detected, output
.EMIOENET0PTPPDELAYRESPRX(), // GMII 0 Rx PTP peer delay responce frame detected, output
.EMIOENET0PTPSYNCFRAMERX(), // GMII 0 Rx PTP sync frame detected, output
// MDIO 0
.EMIOENET0MDIOMDC(), // MDIO 0 MD clock output, output
.EMIOENET0MDIOO(), // MDIO 0 MD data output, output
.EMIOENET0MDIOTN(), // MDIO 0 MD data 3-state, output
.EMIOENET0MDIOI(), // MDIO 0 MD data input, input
// GMII 1
.EMIOENET1GMIICRS(), // GMII 1 Carrier sense, input
.EMIOENET1GMIICOL(), // GMII 1 Collision detect, input
.EMIOENET1EXTINTIN(), // GMII 1 Controller Interrupt input, input
// GMII 1 TX signals
.EMIOENET1GMIITXCLK(), // GMII 1 TX clock, input
.EMIOENET1GMIITXD(), // GMII 1 Tx Data[7:0], output
.EMIOENET1GMIITXEN(), // GMII 1 Tx En, output
.EMIOENET1GMIITXER(), // GMII 1 Tx Err, output
// GMII 1 TX timestamp signals
.EMIOENET1SOFTX(), // GMII 1 Tx Tx Start-of-Frame, output
.EMIOENET1PTPDELAYREQTX(), // GMII 1 Tx PTP delay req frame detected, output
.EMIOENET1PTPPDELAYREQTX(), // GMII 1 Tx PTP peer delay frame detect, output
.EMIOENET1PTPPDELAYRESPTX(), // GMII 1 Tx PTP pear delay response frame detected, output
.EMIOENET1PTPSYNCFRAMETX(), // GMII 1 Tx PTP sync frame detected, output
// GMII 1 RX signals
.EMIOENET1GMIIRXCLK(), // GMII 1 Rx Clock, input
.EMIOENET1GMIIRXD(), // GMII 1 Rx Data (7:0), input
.EMIOENET1GMIIRXDV(), // GMII 1 Rx Data valid, input
.EMIOENET1GMIIRXER(), // GMII 1 Rx Error, input
// GMII 1 RX timestamp signals
.EMIOENET1SOFRX(), // GMII 1 Rx Start of Frame, output
.EMIOENET1PTPDELAYREQRX(), // GMII 1 Rx PTP delay req frame detected
.EMIOENET1PTPPDELAYREQRX(), // GMII 1 Rx PTP peer delay frame detected, output
.EMIOENET1PTPPDELAYRESPRX(), // GMII 1 Rx PTP peer delay responce frame detected, output
.EMIOENET1PTPSYNCFRAMERX(), // GMII 1 Rx PTP sync frame detected, output
// MDIO 1
.EMIOENET1MDIOMDC(), // MDIO 1 MD clock output, output
.EMIOENET1MDIOO(), // MDIO 1 MD data output, output
.EMIOENET1MDIOTN(), // MDIO 1 MD data 3-state, output
.EMIOENET1MDIOI(), // MDIO 1 MD data input, input
// EMIO GPIO
.EMIOGPIOO(), // EMIO GPIO Data out[63:0], output
.EMIOGPIOI(/*gpio_in[63:0]*/), // EMIO GPIO Data in[63:0], input
.EMIOGPIOTN(), // EMIO GPIO OutputEnable[63:0], output
// EMIO I2C 0
.EMIOI2C0SCLO(), // I2C 0 SCL OUT, output // manual says input
.EMIOI2C0SCLI(), // I2C 0 SCL IN, input // manual says output
.EMIOI2C0SCLTN(), // I2C 0 SCL EN, output // manual says input
.EMIOI2C0SDAO(), // I2C 0 SDA OUT, output // manual says input
.EMIOI2C0SDAI(), // I2C 0 SDA IN, input // manual says output
.EMIOI2C0SDATN(), // I2C 0 SDA EN, output // manual says input
// EMIO I2C 1
.EMIOI2C1SCLO(), // I2C 1 SCL OUT, output // manual says input
.EMIOI2C1SCLI(), // I2C 1 SCL IN, input // manual says output
.EMIOI2C1SCLTN(), // I2C 1 SCL EN, output // manual says input
.EMIOI2C1SDAO(), // I2C 1 SDA OUT, output // manual says input
.EMIOI2C1SDAI(), // I2C 1 SDA IN, input // manual says output
.EMIOI2C1SDATN(), // I2C 1 SDA EN, output // manual says input
// JTAG
.EMIOPJTAGTCK(), // JTAG TCK, input
.EMIOPJTAGTMS(), // JTAG TMS, input
.EMIOPJTAGTDI(), // JTAG TDI, input
.EMIOPJTAGTDO(), // JTAG TDO, output
.EMIOPJTAGTDTN(), // JTAG TDO OE, output
// SDIO 0
.EMIOSDIO0CLKFB(), // SDIO 0 Clock feedback, input
.EMIOSDIO0CLK(), // SDIO 0 Clock, output
.EMIOSDIO0CMDI(), // SDIO 0 Command in, input
.EMIOSDIO0CMDO(), // SDIO 0 Command out, output
.EMIOSDIO0CMDTN(), // SDIO 0 command OE, output
.EMIOSDIO0DATAI(), // SDIO 0 Data in [3:0], input
.EMIOSDIO0DATAO(), // SDIO 0 Data out [3:0], output
.EMIOSDIO0DATATN(), // SDIO 0 Data OE [3:0], output
.EMIOSDIO0CDN(), // SDIO 0 Card detect, input
.EMIOSDIO0WP(), // SDIO 0 Write protect, input
.EMIOSDIO0BUSPOW(), // SDIO 0 Power control, output
.EMIOSDIO0LED(), // SDIO 0 LED control, output
.EMIOSDIO0BUSVOLT(), // SDIO 0 Bus voltage [2:0], output
// SDIO 1
.EMIOSDIO1CLKFB(), // SDIO 1 Clock feedback, input
.EMIOSDIO1CLK(), // SDIO 1 Clock, output
.EMIOSDIO1CMDI(), // SDIO 1 Command in, input
.EMIOSDIO1CMDO(), // SDIO 1 Command out, output
.EMIOSDIO1CMDTN(), // SDIO 1 command OE, output
.EMIOSDIO1DATAI(), // SDIO 1 Data in [3:0], input
.EMIOSDIO1DATAO(), // SDIO 1 Data out [3:0], output
.EMIOSDIO1DATATN(), // SDIO 1 Data OE [3:0], output
.EMIOSDIO1CDN(), // SDIO 1 Card detect, input
.EMIOSDIO1WP(), // SDIO 1 Write protect, input
.EMIOSDIO1BUSPOW(), // SDIO 1 Power control, output
.EMIOSDIO1LED(), // SDIO 1 LED control, output
.EMIOSDIO1BUSVOLT(), // SDIO 1 Bus voltage [2:0], output
// SPI 0
.EMIOSPI0SCLKI(), // SPI 0 CLK in , input
.EMIOSPI0SCLKO(), // SPI 0 CLK out, output
.EMIOSPI0SCLKTN(), // SPI 0 CLK OE, output
.EMIOSPI0SI(), // SPI 0 MOSI in , input
.EMIOSPI0MO(), // SPI 0 MOSI out , output
.EMIOSPI0MOTN(), // SPI 0 MOSI OE, output
.EMIOSPI0MI(), // SPI 0 MISO in, input
.EMIOSPI0SO(), // SPI 0 MISO out, output
.EMIOSPI0STN(), // SPI 0 MISO OE, output
.EMIOSPI0SSIN(), // SPI 0 Slave select 0 in, input
.EMIOSPI0SSON(), // SPI 0 Slave select [2:0] out, output
.EMIOSPI0SSNTN(), // SPI 0 Slave select OE, output
// SPI 1
.EMIOSPI1SCLKI(), // SPI 1 CLK in , input
.EMIOSPI1SCLKO(), // SPI 1 CLK out, output
.EMIOSPI1SCLKTN(), // SPI 1 CLK OE, output
.EMIOSPI1SI(), // SPI 1 MOSI in , input
.EMIOSPI1MO(), // SPI 1 MOSI out , output
.EMIOSPI1MOTN(), // SPI 1 MOSI OE, output
.EMIOSPI1MI(), // SPI 1 MISO in, input
.EMIOSPI1SO(), // SPI 1 MISO out, output
.EMIOSPI1STN(), // SPI 1 MISO OE, output
.EMIOSPI1SSIN(), // SPI 1 Slave select 0 in, input
.EMIOSPI1SSON(), // SPI 1 Slave select [2:0] out, output
.EMIOSPI1SSNTN(), // SPI 1 Slave select OE, output
// TPIU signals (Trace)
.EMIOTRACECTL(), // Trace CTL, output
.EMIOTRACEDATA(), // Trace Data[31:0], output
.EMIOTRACECLK(), // Trace CLK, input
// Timers/counters
.EMIOTTC0CLKI(), // Counter/Timer 0 clock in [2:0], input
.EMIOTTC0WAVEO(), // Counter/Timer 0 wave out[2:0], output
.EMIOTTC1CLKI(), // Counter/Timer 1 clock in [2:0], input
.EMIOTTC1WAVEO(), // Counter/Timer 1 wave out[2:0], output
//UART 0
.EMIOUART0TX(), // UART 0 Transmit, output
.EMIOUART0RX(), // UART 0 Receive, input
.EMIOUART0CTSN(), // UART 0 Clear To Send, input
.EMIOUART0RTSN(), // UART 0 Ready to Send, output
.EMIOUART0DSRN(), // UART 0 Data Set Ready , input
.EMIOUART0DCDN(), // UART 0 Data Carrier Detect, input
.EMIOUART0RIN(), // UART 0 Ring Indicator, input
.EMIOUART0DTRN(), // UART 0 Data Terminal Ready, output
//UART 1
.EMIOUART1TX(), // UART 1 Transmit, output
.EMIOUART1RX(), // UART 1 Receive, input
.EMIOUART1CTSN(), // UART 1 Clear To Send, input
.EMIOUART1RTSN(), // UART 1 Ready to Send, output
.EMIOUART1DSRN(), // UART 1 Data Set Ready , input
.EMIOUART1DCDN(), // UART 1 Data Carrier Detect, input
.EMIOUART1RIN(), // UART 1 Ring Indicator, input
.EMIOUART1DTRN(), // UART 1 Data Terminal Ready, output
// USB 0
.EMIOUSB0PORTINDCTL(), // USB 0 Port Indicator [1:0], output
.EMIOUSB0VBUSPWRFAULT(), // USB 0 Power Fault, input
.EMIOUSB0VBUSPWRSELECT(), // USB 0 Power Select, output
// USB 1
.EMIOUSB1PORTINDCTL(), // USB 1 Port Indicator [1:0], output
.EMIOUSB1VBUSPWRFAULT(), // USB 1 Power Fault, input
.EMIOUSB1VBUSPWRSELECT(), // USB 1 Power Select, output
// Watchdog Timer
.EMIOWDTCLKI(), // Watchdog Timer Clock in, input
.EMIOWDTRSTO(), // Watchdog Timer Reset out, output
// DMAC 0
.DMA0ACLK(), // DMAC 0 Clock, input
.DMA0DRVALID(), // DMAC 0 DMA Request Valid, input
.DMA0DRLAST(), // DMAC 0 DMA Request Last, input
.DMA0DRTYPE(), // DMAC 0 DMA Request Type [1:0] ()single/burst/ackn flush/reserved), input
.DMA0DRREADY(), // DMAC 0 DMA Request Ready, output
.DMA0DAVALID(), // DMAC 0 DMA Acknowledge Valid (DA_TYPE[1:0] valid), output
.DMA0DAREADY(), // DMAC 0 DMA Acknowledge (peripheral can accept DA_TYPE[1:0]), input
.DMA0DATYPE(), // DMAC 0 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA0RSTN(), // DMAC 0 RESET output (reserved, do not use), output
// DMAC 1
.DMA1ACLK(), // DMAC 1 Clock, input
.DMA1DRVALID(), // DMAC 1 DMA Request Valid, input
.DMA1DRLAST(), // DMAC 1 DMA Request Last, input
.DMA1DRTYPE(), // DMAC 1 DMA Request Type [1:0] ()single/burst/ackn flush/reserved), input
.DMA1DRREADY(), // DMAC 1 DMA Request Ready, output
.DMA1DAVALID(), // DMAC 1 DMA Acknowledge Valid (DA_TYPE[1:0] valid), output
.DMA1DAREADY(), // DMAC 1 DMA Acknowledge (peripheral can accept DA_TYPE[1:0]), input
.DMA1DATYPE(), // DMAC 1 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA1RSTN(), // DMAC 1 RESET output (reserved, do not use), output
// DMAC 2
.DMA2ACLK(), // DMAC 2 Clock, input
.DMA2DRVALID(), // DMAC 2 DMA Request Valid, input
.DMA2DRLAST(), // DMAC 2 DMA Request Last, input
.DMA2DRTYPE(), // DMAC 2 DMA Request Type [1:0] ()single/burst/ackn flush/reserved), input
.DMA2DRREADY(), // DMAC 2 DMA Request Ready, output
.DMA2DAVALID(), // DMAC 2 DMA Acknowledge Valid (DA_TYPE[1:0] valid), output
.DMA2DAREADY(), // DMAC 2 DMA Acknowledge (peripheral can accept DA_TYPE[1:0]), input
.DMA2DATYPE(), // DMAC 2 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA2RSTN(), // DMAC 2 RESET output (reserved, do not use), output
// DMAC 3
.DMA3ACLK(), // DMAC 3 Clock, input
.DMA3DRVALID(), // DMAC 3 DMA Request Valid, input
.DMA3DRLAST(), // DMAC 3 DMA Request Last, input
.DMA3DRTYPE(), // DMAC 3 DMA Request Type [1:0] ()single/burst/ackn flush/reserved), input
.DMA3DRREADY(), // DMAC 3 DMA Request Ready, output
.DMA3DAVALID(), // DMAC 3 DMA Acknowledge Valid (DA_TYPE[1:0] valid), output
.DMA3DAREADY(), // DMAC 3 DMA Acknowledge (peripheral can accept DA_TYPE[1:0]), input
.DMA3DATYPE(), // DMAC 3 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA3RSTN(), // DMAC 3 RESET output (reserved, do not use), output
// Interrupt signals
.IRQF2P(), // Interrupts, OL to PS [19:0], input
.IRQP2F(), // Interrupts, OL to PS [28:0], output
// Event Signals
.EVENTEVENTI(), // EVENT Wake up one or both CPU from WFE state, input
.EVENTEVENTO(), // EVENT Asserted when one of the COUs executed SEV instruction, output
.EVENTSTANDBYWFE(), // EVENT CPU standby mode [1:0], asserted when CPU is waiting for an event, output
.EVENTSTANDBYWFI(), // EVENT CPU standby mode [1:0], asserted when CPU is waiting for an interrupt, output
// PL Resets and clocks
.FCLKCLK(fclk[3:0]), // PL Clocks [3:0], output
.FCLKCLKTRIGN(), // PL Clock Throttle Control [3:0], input
.FCLKRESETN(frst[3:0]), // PL General purpose user reset [3:0], output (active low)
// Debug signals
.FTMTP2FDEBUG(), // Debug General purpose debug output [31:0], output
.FTMTF2PDEBUG(), // Debug General purpose debug input [31:0], input
.FTMTP2FTRIG(), // Debug Trigger PS to PL [3:0], output
.FTMTP2FTRIGACK(), // Debug Trigger PS to PL acknowledge[3:0], input
.FTMTF2PTRIG(), // Debug Trigger PL to PS [3:0], input
.FTMTF2PTRIGACK(), // Debug Trigger PL to PS acknowledge[3:0], output
.FTMDTRACEINCLOCK(), // Debug Trace PL to PS Clock, input
.FTMDTRACEINVALID(), // Debug Trace PL to PS Clock, data&id valid, input
.FTMDTRACEINDATA(), // Debug Trace PL to PS data [31:0], input
.FTMDTRACEINATID(), // Debug Trace PL to PS ID [3:0], input
// DDR Urgent
.DDRARB(), // DDR Urgent[3:0], input
// SRAM interrupt (on rising edge)
.EMIOSRAMINTIN(), // SRAM interrupt #50 shared with NAND busy, input
// AXI interfaces
.FPGAIDLEN(1'b1), //Idle PL AXI interfaces (active low), input
// AXI PS Master GP0
// AXI PS Master GP0: Clock, Reset
.MAXIGP0ACLK(/*axi_aclk*/), // AXI PS Master GP0 Clock , input
// .MAXIGP0ACLK(/*fclk[0]*/), // AXI PS Master GP0 Clock , input
// .MAXIGP0ACLK(/*~fclk[0]*/), // AXI PS Master GP0 Clock , input
// .MAXIGP0ACLK(/*axi_naclk*/), // AXI PS Master GP0 Clock , input
//
.MAXIGP0ARESETN(), // AXI PS Master GP0 Reset, output
// AXI PS Master GP0: Read Address
.MAXIGP0ARADDR (/*axi_araddr[31:0]*/), // AXI PS Master GP0 ARADDR[31:0], output
.MAXIGP0ARVALID (/*axi_arvalid*/), // AXI PS Master GP0 ARVALID, output
.MAXIGP0ARREADY (/*axi_arready*/), // AXI PS Master GP0 ARREADY, input
.MAXIGP0ARID (/*axi_arid[11:0]*/), // AXI PS Master GP0 ARID[11:0], output
.MAXIGP0ARLOCK (), // AXI PS Master GP0 ARLOCK[1:0], output
.MAXIGP0ARCACHE (),// AXI PS Master GP0 ARCACHE[3:0], output
.MAXIGP0ARPROT(), // AXI PS Master GP0 ARPROT[2:0], output
.MAXIGP0ARLEN (/*axi_arlen[3:0]*/), // AXI PS Master GP0 ARLEN[3:0], output
.MAXIGP0ARSIZE (/*axi_arsize[1:0]*/), // AXI PS Master GP0 ARSIZE[1:0], output
.MAXIGP0ARBURST (/*axi_arburst[1:0]*/),// AXI PS Master GP0 ARBURST[1:0], output
.MAXIGP0ARQOS (), // AXI PS Master GP0 ARQOS[3:0], output
// AXI PS Master GP0: Read Data
.MAXIGP0RDATA (/*axi_rdata[31:0]*/), // AXI PS Master GP0 RDATA[31:0], input
.MAXIGP0RVALID (/*axi_rvalid*/), // AXI PS Master GP0 RVALID, input
.MAXIGP0RREADY (/*axi_rready*/), // AXI PS Master GP0 RREADY, output
.MAXIGP0RID (/*axi_rid[11:0]*/), // AXI PS Master GP0 RID[11:0], input
.MAXIGP0RLAST (/*axi_rlast*/), // AXI PS Master GP0 RLAST, input
.MAXIGP0RRESP (/*axi_rresp[1:0]*/), // AXI PS Master GP0 RRESP[1:0], input
// AXI PS Master GP0: Write Address
.MAXIGP0AWADDR (/*axi_awaddr[31:0]*/), // AXI PS Master GP0 AWADDR[31:0], output
.MAXIGP0AWVALID (/*axi_awvalid*/), // AXI PS Master GP0 AWVALID, output
.MAXIGP0AWREADY (/*axi_awready*/), // AXI PS Master GP0 AWREADY, input
.MAXIGP0AWID (/*axi_awid[11:0]*/), // AXI PS Master GP0 AWID[11:0], output
.MAXIGP0AWLOCK (), // AXI PS Master GP0 AWLOCK[1:0], output
.MAXIGP0AWCACHE (),// AXI PS Master GP0 AWCACHE[3:0], output
.MAXIGP0AWPROT (), // AXI PS Master GP0 AWPROT[2:0], output
.MAXIGP0AWLEN (/*axi_awlen[3:0]*/), // AXI PS Master GP0 AWLEN[3:0], output
.MAXIGP0AWSIZE (/*axi_awsize[1:0]*/), // AXI PS Master GP0 AWSIZE[1:0], output
.MAXIGP0AWBURST (/*axi_awburst[1:0]*/),// AXI PS Master GP0 AWBURST[1:0], output
.MAXIGP0AWQOS (), // AXI PS Master GP0 AWQOS[3:0], output
// AXI PS Master GP0: Write Data
.MAXIGP0WDATA (/*axi_wdata[31:0]*/), // AXI PS Master GP0 WDATA[31:0], output
.MAXIGP0WVALID (/*axi_wvalid*/), // AXI PS Master GP0 WVALID, output
.MAXIGP0WREADY (/*axi_wready*/), // AXI PS Master GP0 WREADY, input
.MAXIGP0WID (/*axi_wid[11:0]*/), // AXI PS Master GP0 WID[11:0], output
.MAXIGP0WLAST (/*axi_wlast*/), // AXI PS Master GP0 WLAST, output
.MAXIGP0WSTRB (/*axi_wstb[3:0]*/), // AXI PS Master GP0 WSTRB[3:0], output
// AXI PS Master GP0: Write Responce
.MAXIGP0BVALID (/*axi_bvalid*/), // AXI PS Master GP0 BVALID, input
.MAXIGP0BREADY (/*axi_bready*/), // AXI PS Master GP0 BREADY, output
.MAXIGP0BID (/*axi_bid[11:0]*/), // AXI PS Master GP0 BID[11:0], input
.MAXIGP0BRESP (/*axi_bresp[1:0]*/), // AXI PS Master GP0 BRESP[1:0], input
// AXI PS Master GP1
// AXI PS Master GP1: Clock, Reset
.MAXIGP1ACLK (axi_aclk), // AXI PS Master GP1 Clock , input
.MAXIGP1ARESETN (), // AXI PS Master GP1 Reset, output
// AXI PS Master GP1: Read Address
.MAXIGP1ARADDR (ARADDR), // AXI PS Master GP1 ARADDR[31:0], output
.MAXIGP1ARVALID (ARVALID), // AXI PS Master GP1 ARVALID, output
.MAXIGP1ARREADY (ARREADY), // AXI PS Master GP1 ARREADY, input
.MAXIGP1ARID (ARID), // AXI PS Master GP1 ARID[11:0], output
.MAXIGP1ARLOCK (ARLOCK), // AXI PS Master GP1 ARLOCK[1:0], output
.MAXIGP1ARCACHE (ARCACHE), // AXI PS Master GP1 ARCACHE[3:0], output
.MAXIGP1ARPROT (ARPROT), // AXI PS Master GP1 ARPROT[2:0], output
.MAXIGP1ARLEN (ARLEN), // AXI PS Master GP1 ARLEN[3:0], output
.MAXIGP1ARSIZE (ARSIZE), // AXI PS Master GP1 ARSIZE[1:0], output
.MAXIGP1ARBURST (ARBURST), // AXI PS Master GP1 ARBURST[1:0], output
.MAXIGP1ARQOS (ARQOS), // AXI PS Master GP1 ARQOS[3:0], output
// AXI PS Master GP1: Read Data
.MAXIGP1RDATA (RDATA), // AXI PS Master GP1 RDATA[31:0], input
.MAXIGP1RVALID (RVALID), // AXI PS Master GP1 RVALID, input
.MAXIGP1RREADY (RREADY), // AXI PS Master GP1 RREADY, output
.MAXIGP1RID (RID), // AXI PS Master GP1 RID[11:0], input
.MAXIGP1RLAST (RLAST), // AXI PS Master GP1 RLAST, input
.MAXIGP1RRESP (RRESP), // AXI PS Master GP1 RRESP[1:0], input
// AXI PS Master GP1: Write Address
.MAXIGP1AWADDR (AWADDR), // AXI PS Master GP1 AWADDR[31:0], output
.MAXIGP1AWVALID (AWVALID), // AXI PS Master GP1 AWVALID, output
.MAXIGP1AWREADY (AWREADY), // AXI PS Master GP1 AWREADY, input
.MAXIGP1AWID (AWID), // AXI PS Master GP1 AWID[11:0], output
.MAXIGP1AWLOCK (AWLOCK), // AXI PS Master GP1 AWLOCK[1:0], output
.MAXIGP1AWCACHE (AWCACHE), // AXI PS Master GP1 AWCACHE[3:0], output
.MAXIGP1AWPROT (AWPROT), // AXI PS Master GP1 AWPROT[2:0], output
.MAXIGP1AWLEN (AWLEN), // AXI PS Master GP1 AWLEN[3:0], output
.MAXIGP1AWSIZE (AWSIZE), // AXI PS Master GP1 AWSIZE[1:0], output
.MAXIGP1AWBURST (AWBURST), // AXI PS Master GP1 AWBURST[1:0], output
.MAXIGP1AWQOS (AWQOS), // AXI PS Master GP1 AWQOS[3:0], output
// AXI PS Master GP1: Write Data
.MAXIGP1WDATA (WDATA), // AXI PS Master GP1 WDATA[31:0], output
.MAXIGP1WVALID (WVALID), // AXI PS Master GP1 WVALID, output
.MAXIGP1WREADY (WREADY), // AXI PS Master GP1 WREADY, input
.MAXIGP1WID (WID), // AXI PS Master GP1 WID[11:0], output
.MAXIGP1WLAST (WLAST), // AXI PS Master GP1 WLAST, output
.MAXIGP1WSTRB (WSTRB), // AXI PS Master GP1 WSTRB[3:0], output
// AXI PS Master GP1: Write Responce
.MAXIGP1BVALID (BVALID), // AXI PS Master GP1 BVALID, input
.MAXIGP1BREADY (BREADY), // AXI PS Master GP1 BREADY, output
.MAXIGP1BID (BID), // AXI PS Master GP1 BID[11:0], input
.MAXIGP1BRESP (BRESP), // AXI PS Master GP1 BRESP[1:0], input
// AXI PS Slave GP0
// AXI PS Slave GP0: Clock, Reset
.SAXIGP0ACLK(), // AXI PS Slave GP0 Clock , input
.SAXIGP0ARESETN(), // AXI PS Slave GP0 Reset, output
// AXI PS Slave GP0: Read Address
.SAXIGP0ARADDR(), // AXI PS Slave GP0 ARADDR[31:0], input
.SAXIGP0ARVALID(), // AXI PS Slave GP0 ARVALID, input
.SAXIGP0ARREADY(), // AXI PS Slave GP0 ARREADY, output
.SAXIGP0ARID(), // AXI PS Slave GP0 ARID[5:0], input
.SAXIGP0ARLOCK(), // AXI PS Slave GP0 ARLOCK[1:0], input
.SAXIGP0ARCACHE(), // AXI PS Slave GP0 ARCACHE[3:0], input
.SAXIGP0ARPROT(), // AXI PS Slave GP0 ARPROT[2:0], input
.SAXIGP0ARLEN(), // AXI PS Slave GP0 ARLEN[3:0], input
.SAXIGP0ARSIZE(), // AXI PS Slave GP0 ARSIZE[1:0], input
.SAXIGP0ARBURST(), // AXI PS Slave GP0 ARBURST[1:0], input
.SAXIGP0ARQOS(), // AXI PS Slave GP0 ARQOS[3:0], input
// AXI PS Slave GP0: Read Data
.SAXIGP0RDATA(), // AXI PS Slave GP0 RDATA[31:0], output
.SAXIGP0RVALID(), // AXI PS Slave GP0 RVALID, output
.SAXIGP0RREADY(), // AXI PS Slave GP0 RREADY, input
.SAXIGP0RID(), // AXI PS Slave GP0 RID[5:0], output
.SAXIGP0RLAST(), // AXI PS Slave GP0 RLAST, output
.SAXIGP0RRESP(), // AXI PS Slave GP0 RRESP[1:0], output
// AXI PS Slave GP0: Write Address
.SAXIGP0AWADDR(), // AXI PS Slave GP0 AWADDR[31:0], input
.SAXIGP0AWVALID(), // AXI PS Slave GP0 AWVALID, input
.SAXIGP0AWREADY(), // AXI PS Slave GP0 AWREADY, output
.SAXIGP0AWID(), // AXI PS Slave GP0 AWID[5:0], input
.SAXIGP0AWLOCK(), // AXI PS Slave GP0 AWLOCK[1:0], input
.SAXIGP0AWCACHE(), // AXI PS Slave GP0 AWCACHE[3:0], input
.SAXIGP0AWPROT(), // AXI PS Slave GP0 AWPROT[2:0], input
.SAXIGP0AWLEN(), // AXI PS Slave GP0 AWLEN[3:0], input
.SAXIGP0AWSIZE(), // AXI PS Slave GP0 AWSIZE[1:0], input
.SAXIGP0AWBURST(), // AXI PS Slave GP0 AWBURST[1:0], input
.SAXIGP0AWQOS(), // AXI PS Slave GP0 AWQOS[3:0], input
// AXI PS Slave GP0: Write Data
.SAXIGP0WDATA(), // AXI PS Slave GP0 WDATA[31:0], input
.SAXIGP0WVALID(), // AXI PS Slave GP0 WVALID, input
.SAXIGP0WREADY(), // AXI PS Slave GP0 WREADY, output
.SAXIGP0WID(), // AXI PS Slave GP0 WID[5:0], input
.SAXIGP0WLAST(), // AXI PS Slave GP0 WLAST, input
.SAXIGP0WSTRB(), // AXI PS Slave GP0 WSTRB[3:0], input
// AXI PS Slave GP0: Write Responce
.SAXIGP0BVALID(), // AXI PS Slave GP0 BVALID, output
.SAXIGP0BREADY(), // AXI PS Slave GP0 BREADY, input
.SAXIGP0BID(), // AXI PS Slave GP0 BID[5:0], output //TODO: Update range !!!
.SAXIGP0BRESP(), // AXI PS Slave GP0 BRESP[1:0], output
// AXI PS Slave GP1
// AXI PS Slave GP1: Clock, Reset
.SAXIGP1ACLK(), // AXI PS Slave GP1 Clock , input
.SAXIGP1ARESETN(), // AXI PS Slave GP1 Reset, output
// AXI PS Slave GP1: Read Address
.SAXIGP1ARADDR(), // AXI PS Slave GP1 ARADDR[31:0], input
.SAXIGP1ARVALID(), // AXI PS Slave GP1 ARVALID, input
.SAXIGP1ARREADY(), // AXI PS Slave GP1 ARREADY, output
.SAXIGP1ARID(), // AXI PS Slave GP1 ARID[5:0], input
.SAXIGP1ARLOCK(), // AXI PS Slave GP1 ARLOCK[1:0], input
.SAXIGP1ARCACHE(), // AXI PS Slave GP1 ARCACHE[3:0], input
.SAXIGP1ARPROT(), // AXI PS Slave GP1 ARPROT[2:0], input
.SAXIGP1ARLEN(), // AXI PS Slave GP1 ARLEN[3:0], input
.SAXIGP1ARSIZE(), // AXI PS Slave GP1 ARSIZE[1:0], input
.SAXIGP1ARBURST(), // AXI PS Slave GP1 ARBURST[1:0], input
.SAXIGP1ARQOS(), // AXI PS Slave GP1 ARQOS[3:0], input
// AXI PS Slave GP1: Read Data
.SAXIGP1RDATA(), // AXI PS Slave GP1 RDATA[31:0], output
.SAXIGP1RVALID(), // AXI PS Slave GP1 RVALID, output
.SAXIGP1RREADY(), // AXI PS Slave GP1 RREADY, input
.SAXIGP1RID(), // AXI PS Slave GP1 RID[5:0], output
.SAXIGP1RLAST(), // AXI PS Slave GP1 RLAST, output
.SAXIGP1RRESP(), // AXI PS Slave GP1 RRESP[1:0], output
// AXI PS Slave GP1: Write Address
.SAXIGP1AWADDR(), // AXI PS Slave GP1 AWADDR[31:0], input
.SAXIGP1AWVALID(), // AXI PS Slave GP1 AWVALID, input
.SAXIGP1AWREADY(), // AXI PS Slave GP1 AWREADY, output
.SAXIGP1AWID(), // AXI PS Slave GP1 AWID[5:0], input
.SAXIGP1AWLOCK(), // AXI PS Slave GP1 AWLOCK[1:0], input
.SAXIGP1AWCACHE(), // AXI PS Slave GP1 AWCACHE[3:0], input
.SAXIGP1AWPROT(), // AXI PS Slave GP1 AWPROT[2:0], input
.SAXIGP1AWLEN(), // AXI PS Slave GP1 AWLEN[3:0], input
.SAXIGP1AWSIZE(), // AXI PS Slave GP1 AWSIZE[1:0], input
.SAXIGP1AWBURST(), // AXI PS Slave GP1 AWBURST[1:0], input
.SAXIGP1AWQOS(), // AXI PS Slave GP1 AWQOS[3:0], input
// AXI PS Slave GP1: Write Data
.SAXIGP1WDATA(), // AXI PS Slave GP1 WDATA[31:0], input
.SAXIGP1WVALID(), // AXI PS Slave GP1 WVALID, input
.SAXIGP1WREADY(), // AXI PS Slave GP1 WREADY, output
.SAXIGP1WID(), // AXI PS Slave GP1 WID[5:0], input
.SAXIGP1WLAST(), // AXI PS Slave GP1 WLAST, input
.SAXIGP1WSTRB(), // AXI PS Slave GP1 WSTRB[3:0], input
// AXI PS Slave GP1: Write Responce
.SAXIGP1BVALID(), // AXI PS Slave GP1 BVALID, output
.SAXIGP1BREADY(), // AXI PS Slave GP1 BREADY, input
.SAXIGP1BID(), // AXI PS Slave GP1 BID[5:0], output
.SAXIGP1BRESP(), // AXI PS Slave GP1 BRESP[1:0], output
// AXI PS Slave HP0
// AXI PS Slave HP0: Clock, Reset
.SAXIHP0ACLK(), // AXI PS Slave HP0 Clock , input
.SAXIHP0ARESETN(), // AXI PS Slave HP0 Reset, output
// AXI PS Slave HP0: Read Address
.SAXIHP0ARADDR(), // AXI PS Slave HP0 ARADDR[31:0], input
.SAXIHP0ARVALID(), // AXI PS Slave HP0 ARVALID, input
.SAXIHP0ARREADY(), // AXI PS Slave HP0 ARREADY, output
.SAXIHP0ARID(), // AXI PS Slave HP0 ARID[5:0], input
.SAXIHP0ARLOCK(), // AXI PS Slave HP0 ARLOCK[1:0], input
.SAXIHP0ARCACHE(), // AXI PS Slave HP0 ARCACHE[3:0], input
.SAXIHP0ARPROT(), // AXI PS Slave HP0 ARPROT[2:0], input
.SAXIHP0ARLEN(), // AXI PS Slave HP0 ARLEN[3:0], input
.SAXIHP0ARSIZE(), // AXI PS Slave HP0 ARSIZE[2:0], input
.SAXIHP0ARBURST(), // AXI PS Slave HP0 ARBURST[1:0], input
.SAXIHP0ARQOS(), // AXI PS Slave HP0 ARQOS[3:0], input
// AXI PS Slave HP0: Read Data
.SAXIHP0RDATA(), // AXI PS Slave HP0 RDATA[63:0], output
.SAXIHP0RVALID(), // AXI PS Slave HP0 RVALID, output
.SAXIHP0RREADY(), // AXI PS Slave HP0 RREADY, input
.SAXIHP0RID(), // AXI PS Slave HP0 RID[5:0], output
.SAXIHP0RLAST(), // AXI PS Slave HP0 RLAST, output
.SAXIHP0RRESP(), // AXI PS Slave HP0 RRESP[1:0], output
.SAXIHP0RCOUNT(), // AXI PS Slave HP0 RCOUNT[7:0], output
.SAXIHP0RACOUNT(), // AXI PS Slave HP0 RACOUNT[2:0], output
.SAXIHP0RDISSUECAP1EN(), // AXI PS Slave HP0 RDISSUECAP1EN, input
// AXI PS Slave HP0: Write Address
.SAXIHP0AWADDR(), // AXI PS Slave HP0 AWADDR[31:0], input
.SAXIHP0AWVALID(), // AXI PS Slave HP0 AWVALID, input
.SAXIHP0AWREADY(), // AXI PS Slave HP0 AWREADY, output
.SAXIHP0AWID(), // AXI PS Slave HP0 AWID[5:0], input
.SAXIHP0AWLOCK(), // AXI PS Slave HP0 AWLOCK[1:0], input
.SAXIHP0AWCACHE(), // AXI PS Slave HP0 AWCACHE[3:0], input
.SAXIHP0AWPROT(), // AXI PS Slave HP0 AWPROT[2:0], input
.SAXIHP0AWLEN(), // AXI PS Slave HP0 AWLEN[3:0], input
.SAXIHP0AWSIZE(), // AXI PS Slave HP0 AWSIZE[1:0], input
.SAXIHP0AWBURST(), // AXI PS Slave HP0 AWBURST[1:0], input
.SAXIHP0AWQOS(), // AXI PS Slave HP0 AWQOS[3:0], input
// AXI PS Slave HP0: Write Data
.SAXIHP0WDATA(), // AXI PS Slave HP0 WDATA[63:0], input
.SAXIHP0WVALID(), // AXI PS Slave HP0 WVALID, input
.SAXIHP0WREADY(), // AXI PS Slave HP0 WREADY, output
.SAXIHP0WID(), // AXI PS Slave HP0 WID[5:0], input
.SAXIHP0WLAST(), // AXI PS Slave HP0 WLAST, input
.SAXIHP0WSTRB(), // AXI PS Slave HP0 WSTRB[7:0], input
.SAXIHP0WCOUNT(), // AXI PS Slave HP0 WCOUNT[7:0], output
.SAXIHP0WACOUNT(), // AXI PS Slave HP0 WACOUNT[5:0], output
.SAXIHP0WRISSUECAP1EN(), // AXI PS Slave HP0 WRISSUECAP1EN, input
// AXI PS Slave HP0: Write Responce
.SAXIHP0BVALID(), // AXI PS Slave HP0 BVALID, output
.SAXIHP0BREADY(), // AXI PS Slave HP0 BREADY, input
.SAXIHP0BID(), // AXI PS Slave HP0 BID[5:0], output
.SAXIHP0BRESP(), // AXI PS Slave HP0 BRESP[1:0], output
// AXI PS Slave HP1
// AXI PS Slave 1: Clock, Reset
.SAXIHP1ACLK(), // AXI PS Slave HP1 Clock , input
.SAXIHP1ARESETN(), // AXI PS Slave HP1 Reset, output
// AXI PS Slave HP1: Read Address
.SAXIHP1ARADDR(), // AXI PS Slave HP1 ARADDR[31:0], input
.SAXIHP1ARVALID(), // AXI PS Slave HP1 ARVALID, input
.SAXIHP1ARREADY(), // AXI PS Slave HP1 ARREADY, output
.SAXIHP1ARID(), // AXI PS Slave HP1 ARID[5:0], input
.SAXIHP1ARLOCK(), // AXI PS Slave HP1 ARLOCK[1:0], input
.SAXIHP1ARCACHE(), // AXI PS Slave HP1 ARCACHE[3:0], input
.SAXIHP1ARPROT(), // AXI PS Slave HP1 ARPROT[2:0], input
.SAXIHP1ARLEN(), // AXI PS Slave HP1 ARLEN[3:0], input
.SAXIHP1ARSIZE(), // AXI PS Slave HP1 ARSIZE[2:0], input
.SAXIHP1ARBURST(), // AXI PS Slave HP1 ARBURST[1:0], input
.SAXIHP1ARQOS(), // AXI PS Slave HP1 ARQOS[3:0], input
// AXI PS Slave HP1: Read Data
.SAXIHP1RDATA(), // AXI PS Slave HP1 RDATA[63:0], output
.SAXIHP1RVALID(), // AXI PS Slave HP1 RVALID, output
.SAXIHP1RREADY(), // AXI PS Slave HP1 RREADY, input
.SAXIHP1RID(), // AXI PS Slave HP1 RID[5:0], output
.SAXIHP1RLAST(), // AXI PS Slave HP1 RLAST, output
.SAXIHP1RRESP(), // AXI PS Slave HP1 RRESP[1:0], output
.SAXIHP1RCOUNT(), // AXI PS Slave HP1 RCOUNT[7:0], output
.SAXIHP1RACOUNT(), // AXI PS Slave HP1 RACOUNT[2:0], output
.SAXIHP1RDISSUECAP1EN(), // AXI PS Slave HP1 RDISSUECAP1EN, input
// AXI PS Slave HP1: Write Address
.SAXIHP1AWADDR(), // AXI PS Slave HP1 AWADDR[31:0], input
.SAXIHP1AWVALID(), // AXI PS Slave HP1 AWVALID, input
.SAXIHP1AWREADY(), // AXI PS Slave HP1 AWREADY, output
.SAXIHP1AWID(), // AXI PS Slave HP1 AWID[5:0], input
.SAXIHP1AWLOCK(), // AXI PS Slave HP1 AWLOCK[1:0], input
.SAXIHP1AWCACHE(), // AXI PS Slave HP1 AWCACHE[3:0], input
.SAXIHP1AWPROT(), // AXI PS Slave HP1 AWPROT[2:0], input
.SAXIHP1AWLEN(), // AXI PS Slave HP1 AWLEN[3:0], input
.SAXIHP1AWSIZE(), // AXI PS Slave HP1 AWSIZE[1:0], input
.SAXIHP1AWBURST(), // AXI PS Slave HP1 AWBURST[1:0], input
.SAXIHP1AWQOS(), // AXI PS Slave HP1 AWQOS[3:0], input
// AXI PS Slave HP1: Write Data
.SAXIHP1WDATA(), // AXI PS Slave HP1 WDATA[63:0], input
.SAXIHP1WVALID(), // AXI PS Slave HP1 WVALID, input
.SAXIHP1WREADY(), // AXI PS Slave HP1 WREADY, output
.SAXIHP1WID(), // AXI PS Slave HP1 WID[5:0], input
.SAXIHP1WLAST(), // AXI PS Slave HP1 WLAST, input
.SAXIHP1WSTRB(), // AXI PS Slave HP1 WSTRB[7:0], input
.SAXIHP1WCOUNT(), // AXI PS Slave HP1 WCOUNT[7:0], output
.SAXIHP1WACOUNT(), // AXI PS Slave HP1 WACOUNT[5:0], output
.SAXIHP1WRISSUECAP1EN(), // AXI PS Slave HP1 WRISSUECAP1EN, input
// AXI PS Slave HP1: Write Responce
.SAXIHP1BVALID(), // AXI PS Slave HP1 BVALID, output
.SAXIHP1BREADY(), // AXI PS Slave HP1 BREADY, input
.SAXIHP1BID(), // AXI PS Slave HP1 BID[5:0], output
.SAXIHP1BRESP(), // AXI PS Slave HP1 BRESP[1:0], output
// AXI PS Slave HP2
// AXI PS Slave HP2: Clock, Reset
.SAXIHP2ACLK(), // AXI PS Slave HP2 Clock , input
.SAXIHP2ARESETN(), // AXI PS Slave HP2 Reset, output
// AXI PS Slave HP2: Read Address
.SAXIHP2ARADDR(), // AXI PS Slave HP2 ARADDR[31:0], input
.SAXIHP2ARVALID(), // AXI PS Slave HP2 ARVALID, input
.SAXIHP2ARREADY(), // AXI PS Slave HP2 ARREADY, output
.SAXIHP2ARID(), // AXI PS Slave HP2 ARID[5:0], input
.SAXIHP2ARLOCK(), // AXI PS Slave HP2 ARLOCK[1:0], input
.SAXIHP2ARCACHE(), // AXI PS Slave HP2 ARCACHE[3:0], input
.SAXIHP2ARPROT(), // AXI PS Slave HP2 ARPROT[2:0], input
.SAXIHP2ARLEN(), // AXI PS Slave HP2 ARLEN[3:0], input
.SAXIHP2ARSIZE(), // AXI PS Slave HP2 ARSIZE[2:0], input
.SAXIHP2ARBURST(), // AXI PS Slave HP2 ARBURST[1:0], input
.SAXIHP2ARQOS(), // AXI PS Slave HP2 ARQOS[3:0], input
// AXI PS Slave HP2: Read Data
.SAXIHP2RDATA(), // AXI PS Slave HP2 RDATA[63:0], output
.SAXIHP2RVALID(), // AXI PS Slave HP2 RVALID, output
.SAXIHP2RREADY(), // AXI PS Slave HP2 RREADY, input
.SAXIHP2RID(), // AXI PS Slave HP2 RID[5:0], output
.SAXIHP2RLAST(), // AXI PS Slave HP2 RLAST, output
.SAXIHP2RRESP(), // AXI PS Slave HP2 RRESP[1:0], output
.SAXIHP2RCOUNT(), // AXI PS Slave HP2 RCOUNT[7:0], output
.SAXIHP2RACOUNT(), // AXI PS Slave HP2 RACOUNT[2:0], output
.SAXIHP2RDISSUECAP1EN(), // AXI PS Slave HP2 RDISSUECAP1EN, input
// AXI PS Slave HP2: Write Address
.SAXIHP2AWADDR(), // AXI PS Slave HP2 AWADDR[31:0], input
.SAXIHP2AWVALID(), // AXI PS Slave HP2 AWVALID, input
.SAXIHP2AWREADY(), // AXI PS Slave HP2 AWREADY, output
.SAXIHP2AWID(), // AXI PS Slave HP2 AWID[5:0], input
.SAXIHP2AWLOCK(), // AXI PS Slave HP2 AWLOCK[1:0], input
.SAXIHP2AWCACHE(), // AXI PS Slave HP2 AWCACHE[3:0], input
.SAXIHP2AWPROT(), // AXI PS Slave HP2 AWPROT[2:0], input
.SAXIHP2AWLEN(), // AXI PS Slave HP2 AWLEN[3:0], input
.SAXIHP2AWSIZE(), // AXI PS Slave HP2 AWSIZE[1:0], input
.SAXIHP2AWBURST(), // AXI PS Slave HP2 AWBURST[1:0], input
.SAXIHP2AWQOS(), // AXI PS Slave HP2 AWQOS[3:0], input
// AXI PS Slave HP2: Write Data
.SAXIHP2WDATA(), // AXI PS Slave HP2 WDATA[63:0], input
.SAXIHP2WVALID(), // AXI PS Slave HP2 WVALID, input
.SAXIHP2WREADY(), // AXI PS Slave HP2 WREADY, output
.SAXIHP2WID(), // AXI PS Slave HP2 WID[5:0], input
.SAXIHP2WLAST(), // AXI PS Slave HP2 WLAST, input
.SAXIHP2WSTRB(), // AXI PS Slave HP2 WSTRB[7:0], input
.SAXIHP2WCOUNT(), // AXI PS Slave HP2 WCOUNT[7:0], output
.SAXIHP2WACOUNT(), // AXI PS Slave HP2 WACOUNT[5:0], output
.SAXIHP2WRISSUECAP1EN(), // AXI PS Slave HP2 WRISSUECAP1EN, input
// AXI PS Slave HP2: Write Responce
.SAXIHP2BVALID(), // AXI PS Slave HP2 BVALID, output
.SAXIHP2BREADY(), // AXI PS Slave HP2 BREADY, input
.SAXIHP2BID(), // AXI PS Slave HP2 BID[5:0], output
.SAXIHP2BRESP(), // AXI PS Slave HP2 BRESP[1:0], output
// AXI PS Slave HP3
// AXI PS Slave HP3: Clock, Reset
.SAXIHP3ACLK(), // AXI PS Slave HP3 Clock , input
.SAXIHP3ARESETN(), // AXI PS Slave HP3 Reset, output
// AXI PS Slave HP3: Read Address
.SAXIHP3ARADDR(), // AXI PS Slave HP3 ARADDR[31:0], input
.SAXIHP3ARVALID(), // AXI PS Slave HP3 ARVALID, input
.SAXIHP3ARREADY(), // AXI PS Slave HP3 ARREADY, output
.SAXIHP3ARID(), // AXI PS Slave HP3 ARID[5:0], input
.SAXIHP3ARLOCK(), // AXI PS Slave HP3 ARLOCK[1:0], input
.SAXIHP3ARCACHE(), // AXI PS Slave HP3 ARCACHE[3:0], input
.SAXIHP3ARPROT(), // AXI PS Slave HP3 ARPROT[2:0], input
.SAXIHP3ARLEN(), // AXI PS Slave HP3 ARLEN[3:0], input
.SAXIHP3ARSIZE(), // AXI PS Slave HP3 ARSIZE[2:0], input
.SAXIHP3ARBURST(), // AXI PS Slave HP3 ARBURST[1:0], input
.SAXIHP3ARQOS(), // AXI PS Slave HP3 ARQOS[3:0], input
// AXI PS Slave HP3: Read Data
.SAXIHP3RDATA(), // AXI PS Slave HP3 RDATA[63:0], output
.SAXIHP3RVALID(), // AXI PS Slave HP3 RVALID, output
.SAXIHP3RREADY(), // AXI PS Slave HP3 RREADY, input
.SAXIHP3RID(), // AXI PS Slave HP3 RID[5:0], output
.SAXIHP3RLAST(), // AXI PS Slave HP3 RLAST, output
.SAXIHP3RRESP(), // AXI PS Slave HP3 RRESP[1:0], output
.SAXIHP3RCOUNT(), // AXI PS Slave HP3 RCOUNT[7:0], output
.SAXIHP3RACOUNT(), // AXI PS Slave HP3 RACOUNT[2:0], output
.SAXIHP3RDISSUECAP1EN(), // AXI PS Slave HP3 RDISSUECAP1EN, input
// AXI PS Slave HP3: Write Address
.SAXIHP3AWADDR(), // AXI PS Slave HP3 AWADDR[31:0], input
.SAXIHP3AWVALID(), // AXI PS Slave HP3 AWVALID, input
.SAXIHP3AWREADY(), // AXI PS Slave HP3 AWREADY, output
.SAXIHP3AWID(), // AXI PS Slave HP3 AWID[5:0], input
.SAXIHP3AWLOCK(), // AXI PS Slave HP3 AWLOCK[1:0], input
.SAXIHP3AWCACHE(), // AXI PS Slave HP3 AWCACHE[3:0], input
.SAXIHP3AWPROT(), // AXI PS Slave HP3 AWPROT[2:0], input
.SAXIHP3AWLEN(), // AXI PS Slave HP3 AWLEN[3:0], input
.SAXIHP3AWSIZE(), // AXI PS Slave HP3 AWSIZE[1:0], input
.SAXIHP3AWBURST(), // AXI PS Slave HP3 AWBURST[1:0], input
.SAXIHP3AWQOS(), // AXI PS Slave HP3 AWQOS[3:0], input
// AXI PS Slave HP3: Write Data
.SAXIHP3WDATA(), // AXI PS Slave HP3 WDATA[63:0], input
.SAXIHP3WVALID(), // AXI PS Slave HP3 WVALID, input
.SAXIHP3WREADY(), // AXI PS Slave HP3 WREADY, output
.SAXIHP3WID(), // AXI PS Slave HP3 WID[5:0], input
.SAXIHP3WLAST(), // AXI PS Slave HP3 WLAST, input
.SAXIHP3WSTRB(), // AXI PS Slave HP3 WSTRB[7:0], input
.SAXIHP3WCOUNT(), // AXI PS Slave HP3 WCOUNT[7:0], output
.SAXIHP3WACOUNT(), // AXI PS Slave HP3 WACOUNT[5:0], output
.SAXIHP3WRISSUECAP1EN(), // AXI PS Slave HP3 WRISSUECAP1EN, input
// AXI PS Slave HP3: Write Responce
.SAXIHP3BVALID(), // AXI PS Slave HP3 BVALID, output
.SAXIHP3BREADY(), // AXI PS Slave HP3 BREADY, input
.SAXIHP3BID(), // AXI PS Slave HP3 BID[5:0], output
.SAXIHP3BRESP(), // AXI PS Slave HP3 BRESP[1:0], output
// AXI PS Slave ACP
// AXI PS Slave ACP: Clock, Reset
.SAXIACPACLK(), // AXI PS Slave ACP Clock, input
.SAXIACPARESETN(), // AXI PS Slave ACP Reset, output
// AXI PS Slave ACP: Read Address
.SAXIACPARADDR(), // AXI PS Slave ACP ARADDR[31:0], input
.SAXIACPARVALID(), // AXI PS Slave ACP ARVALID, input
.SAXIACPARREADY(), // AXI PS Slave ACP ARREADY, output
.SAXIACPARID(), // AXI PS Slave ACP ARID[2:0], input
.SAXIACPARLOCK(), // AXI PS Slave ACP ARLOCK[1:0], input
.SAXIACPARCACHE(), // AXI PS Slave ACP ARCACHE[3:0], input
.SAXIACPARPROT(), // AXI PS Slave ACP ARPROT[2:0], input
.SAXIACPARLEN(), // AXI PS Slave ACP ARLEN[3:0], input
.SAXIACPARSIZE(), // AXI PS Slave ACP ARSIZE[2:0], input
.SAXIACPARBURST(), // AXI PS Slave ACP ARBURST[1:0], input
.SAXIACPARQOS(), // AXI PS Slave ACP ARQOS[3:0], input
.SAXIACPARUSER(), // AXI PS Slave ACP ARUSER[4:0], input
// AXI PS Slave ACP: Read Data
.SAXIACPRDATA(), // AXI PS Slave ACP RDATA[63:0], output
.SAXIACPRVALID(), // AXI PS Slave ACP RVALID, output
.SAXIACPRREADY(), // AXI PS Slave ACP RREADY, input
.SAXIACPRID(), // AXI PS Slave ACP RID[2:0], output
.SAXIACPRLAST(), // AXI PS Slave ACP RLAST, output
.SAXIACPRRESP(), // AXI PS Slave ACP RRESP[1:0], output
// AXI PS Slave ACP: Write Address
.SAXIACPAWADDR(), // AXI PS Slave ACP AWADDR[31:0], input
.SAXIACPAWVALID(), // AXI PS Slave ACP AWVALID, input
.SAXIACPAWREADY(), // AXI PS Slave ACP AWREADY, output
.SAXIACPAWID(), // AXI PS Slave ACP AWID[2:0], input
.SAXIACPAWLOCK(), // AXI PS Slave ACP AWLOCK[1:0], input
.SAXIACPAWCACHE(), // AXI PS Slave ACP AWCACHE[3:0], input
.SAXIACPAWPROT(), // AXI PS Slave ACP AWPROT[2:0], input
.SAXIACPAWLEN(), // AXI PS Slave ACP AWLEN[3:0], input
.SAXIACPAWSIZE(), // AXI PS Slave ACP AWSIZE[1:0], input
.SAXIACPAWBURST(), // AXI PS Slave ACP AWBURST[1:0], input
.SAXIACPAWQOS(), // AXI PS Slave ACP AWQOS[3:0], input
.SAXIACPAWUSER(), // AXI PS Slave ACP AWUSER[4:0], input
// AXI PS Slave ACP: Write Data
.SAXIACPWDATA(), // AXI PS Slave ACP WDATA[63:0], input
.SAXIACPWVALID(), // AXI PS Slave ACP WVALID, input
.SAXIACPWREADY(), // AXI PS Slave ACP WREADY, output
.SAXIACPWID(), // AXI PS Slave ACP WID[2:0], input
.SAXIACPWLAST(), // AXI PS Slave ACP WLAST, input
.SAXIACPWSTRB(), // AXI PS Slave ACP WSTRB[7:0], input
// AXI PS Slave ACP: Write Responce
.SAXIACPBVALID(), // AXI PS Slave ACP BVALID, output
.SAXIACPBREADY(), // AXI PS Slave ACP BREADY, input
.SAXIACPBID(), // AXI PS Slave ACP BID[2:0], output
.SAXIACPBRESP(), // AXI PS Slave ACP BRESP[1:0], output
// Direct connection to PS package pads
.DDRA(), // PS DDRA[14:0], inout
.DDRBA(), // PS DDRBA[2:0], inout
.DDRCASB(), // PS DDRCASB, inout
.DDRCKE(), // PS DDRCKE, inout
.DDRCKP(), // PS DDRCKP, inout
.DDRCKN(), // PS DDRCKN, inout
.DDRCSB(), // PS DDRCSB, inout
.DDRDM(), // PS DDRDM[3:0], inout
.DDRDQ(), // PS DDRDQ[31:0], inout
.DDRDQSP(), // PS DDRDQSP[3:0], inout
.DDRDQSN(), // PS DDRDQSN[3:0], inout
.DDRDRSTB(), // PS DDRDRSTB, inout
.DDRODT(), // PS DDRODT, inout
.DDRRASB(), // PS DDRRASB, inout
.DDRVRN(), // PS DDRVRN, inout
.DDRVRP(), // PS DDRVRP, inout
.DDRWEB(), // PS DDRWEB, inout
.MIO(), // PS MIO[53:0], inout // clg225 has less
.PSCLK(), // PS PSCLK, inout
.PSPORB(), // PS PSPORB, inout
.PSSRSTB() // PS PSSRSTB, inout
);
endmodule
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