From 5f8fee87b69690cf2f69b4557527f7e256530089 Mon Sep 17 00:00:00 2001 From: Andrey Filippov Date: Tue, 26 Jan 2016 00:44:27 -0700 Subject: [PATCH] simulating/debugging --- ahci/ahci_fis_transmit.v | 8 +-- ahci/ahci_top.v | 3 +- device/sata_device.v | 2 +- tb/tb_ahci.tf | 3 +- tb_ahci_01.sav | 105 +++++++++++++++++++++++++++++++++++---- 5 files changed, 105 insertions(+), 16 deletions(-) diff --git a/ahci/ahci_fis_transmit.v b/ahci/ahci_fis_transmit.v index 9dd7d9d..9b001b8 100644 --- a/ahci/ahci_fis_transmit.v +++ b/ahci/ahci_fis_transmit.v @@ -23,7 +23,8 @@ module ahci_fis_transmit #( parameter PREFETCH_ALWAYS = 0, parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen - parameter READ_CT_LATENCY = 1, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen +// parameter READ_CT_LATENCY = 1, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen + parameter READ_CT_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen parameter ADDRESS_BITS = 10 // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle) )( @@ -281,8 +282,9 @@ module ahci_fis_transmit #( if (cfis_xmit) ct_addr <= 0; else if (atapi_xmit) ct_addr <= 'h10; // start of ATAPI area - else if (cfis_acmd_left_r[0]) ct_addr <= ct_addr + 1; - +// else if (cfis_acmd_left_r[0]) ct_addr <= ct_addr + 1; + else if (ct_re_r[0]) ct_addr <= ct_addr + 1; +// // first/last dword in FIS if (!acfis_xmit_busy_r) fis_dw_first <= 1; else if (ct_stb) fis_dw_first <= 0; diff --git a/ahci/ahci_top.v b/ahci/ahci_top.v index fa37c3f..0763135 100644 --- a/ahci/ahci_top.v +++ b/ahci/ahci_top.v @@ -23,7 +23,8 @@ module ahci_top#( parameter PREFETCH_ALWAYS = 0, parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen - parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen +// parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen + parameter READ_CT_LATENCY = 2, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle) parameter HBA_RESET_BITS = 9, // duration of HBA reset in aclk periods (9: ~10usec) parameter RESET_TO_FIRST_ACCESS = 1 // keep port reset until first R/W any register by software diff --git a/device/sata_device.v b/device/sata_device.v index a17a9b3..7329ab7 100644 --- a/device/sata_device.v +++ b/device/sata_device.v @@ -501,7 +501,7 @@ task linkMonitorFIS; // $display("[Device] LINK: Got data = %h", receive_data[cnt]); DEV_TITLE = "Got data"; DEV_DATA = receive_data[cnt]; - $display("[Device] LINK: %s = %d @%t", DEV_TITLE, DEV_DATA, $time); + $display("[Device] LINK: %s = %h @%t", DEV_TITLE, DEV_DATA, $time); pause = pause + receive_data_pause[cnt]; crc = calculateCRC(crc, receive_data[cnt]); // running crc. shall be 0 diff --git a/tb/tb_ahci.tf b/tb/tb_ahci.tf index fd37a66..38f4603 100644 --- a/tb/tb_ahci.tf +++ b/tb/tb_ahci.tf @@ -720,7 +720,8 @@ localparam ATA_IDFY = 'hec; // Identify command (1 << 7) | // 'P' Prefetchable = 1 (0 << 8) | // 'R' Not a Reset (0 << 9) | // 'B' Not a BIST - (0 << 10) | // 'C' Do not clear BSY/CI after transmitting this command +// (0 << 10) | // 'C' Do not clear BSY/CI after transmitting this command + (1 << 10) | // 'C' Do clear BSY/CI after transmitting this command (1 << 16)); // 'PRDTL' - number of PRDT entries (just one) maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address // Set Command Issued diff --git a/tb_ahci_01.sav b/tb_ahci_01.sav index 177cc13..930f132 100644 --- a/tb_ahci_01.sav +++ b/tb_ahci_01.sav @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI -[*] Tue Jan 26 02:29:04 2016 +[*] Tue Jan 26 07:42:26 2016 [*] -[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160125190408414.fst" -[dumpfile_mtime] "Tue Jan 26 02:05:07 2016" -[dumpfile_size] 6202198 +[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160126002016009.fst" +[dumpfile_mtime] "Tue Jan 26 07:20:39 2016" +[dumpfile_size] 3075666 [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav" -[timestart] 0 +[timestart] 20289400 [size] 1823 1180 -[pos] 1951 0 -*-23.114683 19004242 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[pos] 1994 0 +*-15.994723 20457430 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] tb_ahci. [treeopen] tb_ahci.dev. [treeopen] tb_ahci.dev.phy. @@ -17,6 +17,7 @@ [treeopen] tb_ahci.dut.axi_hp_clk_i. [treeopen] tb_ahci.dut.sata_top. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i. +[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl. [treeopen] tb_ahci.dut.sata_top.ahci_top_i. @@ -31,9 +32,9 @@ [treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i. [treeopen] tb_ahci.simul_axi_hp_rd_i. [sst_width] 420 -[signals_width] 254 +[signals_width] 330 [sst_expanded] 1 -[sst_vpaned_height] 625 +[sst_vpaned_height] 618 @820 tb_ahci.TESTBENCH_TITLE[639:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0] @@ -795,7 +796,9 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0] @28 (0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0] (1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0] +@29 (2)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0] +@28 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_pre_act_w @1001200 -group_end @@ -1031,6 +1034,27 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.todev_ready tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_w tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_stb tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.acfis_xmit_end +@22 +tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_addr[4:0] +@800028 +tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re[1:0] +@28 +(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re[1:0] +(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re[1:0] +@22 +tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_data[31:0] +tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.cfis_acmd_left_r[4:0] +@1001200 +-group_end +@200 +- +@28 +tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.fis_data_valid +tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.write_or_w +tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.todev_valid +@22 +tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.todev_type[1:0] +tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.todev_data[31:0] @1001200 -group_end -group_end @@ -1040,10 +1064,38 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.acfis_xmit_end -ahci_sata_layers @28 tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_ready -@23 +@22 tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_fill[9:0] +@28 +tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_fifo_wr +tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_fifo_rd +@22 +tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_type[1:0] +tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_mask[1:0] +tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_data[31:0] +tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_h2d_mask_in[1:0] +tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_h2d_data_in[31:0] +tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_type_out[1:0] +@c00200 +-fifo_h2d_control +@28 +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.clk +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.wr +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.rd +@22 +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.mem_wa[8:0] +@28 +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.mem_re +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.mem_regen +@22 +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.fill_ram[9:0] +@28 +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.ramo_full +tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.rreg_full @200 - +@1401200 +-fifo_h2d_control @1000200 -ahci_sata_layers @800200 @@ -1082,11 +1134,14 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_data_pend @22 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_addr[31:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rdata[63:0] +tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.int_data_addr[3:0] @800028 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0] @28 (0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0] (1)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0] +tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_afi_re +tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rready tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.is_ct_addr @22 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ctba_r[31:7] @@ -1100,6 +1155,9 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ct_data[31:0] -group_end @200 - +@22 +tb_ahci.sysmem_dworda_rd[31:2] +tb_ahci.afi_sim_rd_data[63:0] @800200 -top @28 @@ -1228,10 +1286,37 @@ tb_ahci.simul_axi_hp_rd_i.was_data_fifo_write @200 - @28 +tb_ahci.simul_axi_hp_rd_i.sim_rd_valid +tb_ahci.simul_axi_hp_rd_i.sim_rd_ready +@22 +tb_ahci.simul_axi_hp_rd_i.sim_rd_data[63:0] +@200 +- +@28 +tb_ahci.simul_axi_hp_rd_i.aclk +@22 +tb_ahci.simul_axi_hp_rd_i.rcount[7:0] +tb_ahci.simul_axi_hp_rd_i.rdata[63:0] +@28 +tb_ahci.simul_axi_hp_rd_i.rready +tb_ahci.simul_axi_hp_rd_i.rvalid tb_ahci.MEM_SEL @22 tb_ahci.sysmem_dworda_rd[31:2] +@800200 +-rdata_fifo +@28 +tb_ahci.simul_axi_hp_rd_i.rdata_i.wem +@22 +tb_ahci.simul_axi_hp_rd_i.rdata_i.fill[7:0] +tb_ahci.simul_axi_hp_rd_i.rdata_i.fifo_fill[7:0] +@28 +tb_ahci.simul_axi_hp_rd_i.rdata_i.ram_nempty +tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full +@200 +- @1000200 +-rdata_fifo -simul_axi_hp_rd -top @200 -- 2.18.1