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Commit 5260a2c5 authored by Alexey Grebenkin's avatar Alexey Grebenkin
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Typo in gtxe2_wrapper fixed

parent 340db2c6
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Showing with 7 additions and 3 deletions
wrapper/gtxe2_channel_wrapper.v
View file @ 5260a2c5
...@@ -553,9 +553,9 @@ parameter RX_CLK25_DIV = 6; ...@@ -553,9 +553,9 @@ parameter RX_CLK25_DIV = 6;
parameter TX_CLK25_DIV = 6; parameter TX_CLK25_DIV = 6;
`ifdef OPEN_SOURCE_ONLY `ifdef OPEN_SOURCE_ONLY
GTXE2_CPL gtx_gpl #( GTXE2_CPL #(
`else // OPEN_SOURCE_ONLY `else // OPEN_SOURCE_ONLY
GTXE2_CHANNEL gtx_unisims #( GTXE2_CHANNEL #(
`endif // OPEN_SOURCE_ONLY `endif // OPEN_SOURCE_ONLY
// simulation common attributes, UG476 p.28 // simulation common attributes, UG476 p.28
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP), .SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
...@@ -807,7 +807,11 @@ GTXE2_CHANNEL gtx_unisims #( ...@@ -807,7 +807,11 @@ GTXE2_CHANNEL gtx_unisims #(
.RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLK25_DIV (RX_CLK25_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV) .TX_CLK25_DIV (TX_CLK25_DIV)
) )
( `ifdef OPEN_SOURCE_ONLY
gtx_gpl(
`else // OPEN_SOURCE_ONLY
gtx_unisims(
`endif // OPEN_SOURCE_ONLY
// clocking ports, UG476 p.37 // clocking ports, UG476 p.37
.CPLLREFCLKSEL (CPLLREFCLKSEL), .CPLLREFCLKSEL (CPLLREFCLKSEL),
.GTGREFCLK (GTGREFCLK), .GTGREFCLK (GTGREFCLK),
......
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