more debugging (4190b627) · Commits · Elphel / x393_sata

ahci/ahci_fis_receive.v

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -325,7 +325,8 @@ localparam DATA_TYPE_ERR = 3;
	if (store_sig[1]) sig_r[31:8] <= hba_data_in[23:0];		if (store_sig[1]) sig_r[31:8] <= hba_data_in[23:0];
	if (store_sig[3]) sig_r[ 7:0] <= hba_data_in[ 7:0];		if (store_sig[3]) sig_r[ 7:0] <= hba_data_in[ 7:0];

	if (reg_d2h) tf_err_sts <= hba_data_in[31:16]; // 15:0];		if (hba_rst) tf_err_sts <= 0;
			else if (reg_d2h) tf_err_sts <= hba_data_in[31:16]; // 15:0];
	// Sets pPioErr[pPmpCur] to Error field of the FIS		// Sets pPioErr[pPmpCur] to Error field of the FIS
	// Updates PxTFD.STS.ERR with pPioErr[pPmpCur] ??		// Updates PxTFD.STS.ERR with pPioErr[pPmpCur] ??
	else if (reg_ps[0]) tf_err_sts <= {hba_data_in[31:24],hba_data_in[23:16]};		else if (reg_ps[0]) tf_err_sts <= {hba_data_in[31:24],hba_data_in[23:16]};

ahci/axi_ahci_regs.v

+9 −8

device/sata_device.v

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -43,7 +43,7 @@ module sata_device(
	);		);
	`include "includes/fis_types.vh"		`include "includes/fis_types.vh"
	//`ifdef SIMULATION		//`ifdef SIMULATION
	reg [639:0] DEV_TITLE; // to show human-readable state in the GTKWave		reg [639:0] DEV_TITLE = 'bz; // to show human-readable state in the GTKWave
	// reg [31:0] DEV_DATA;		// reg [31:0] DEV_DATA;
	integer DEV_DATA;		integer DEV_DATA;
	//`endif		//`endif

generated/action_decoder.v

+1 −1

Original line number	Original line	Diff line number	Diff line
	/*******************************************************************************		/*******************************************************************************
	* Module: action_decoder		* Module: action_decoder
	* Date:2016-01-22		* Date:2016-01-24
	* Author: auto-generated file, see ahci_fsm_sequence.py		* Author: auto-generated file, see ahci_fsm_sequence.py
	* Description: Decode sequencer code to 1-hot actions		* Description: Decode sequencer code to 1-hot actions
	*******************************************************************************/		*******************************************************************************/

generated/condition_mux.v

+1 −1

Original line number	Original line	Diff line number	Diff line
	/*******************************************************************************		/*******************************************************************************
	* Module: condition_mux		* Module: condition_mux
	* Date:2016-01-22		* Date:2016-01-24
	* Author: auto-generated file, see ahci_fsm_sequence.py		* Author: auto-generated file, see ahci_fsm_sequence.py
	* Description: Select condition		* Description: Select condition
	*******************************************************************************/		*******************************************************************************/

Original line number	Original line	Diff line number	Diff line
	@@ -187,13 +187,13 @@ module axi_ahci_regs#(
	reg [2:0] arst_r = ~0; // previous state of arst		reg [2:0] arst_r = ~0; // previous state of arst
	reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access		reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access
	wire any_access = bram_wen_r \|\| bram_ren[0];		wire any_access = bram_wen_r \|\| bram_ren[0];
	reg bram_ren0_r;		// reg bram_ren0_r;
	wire [1:0] bram_ren_w = {bram_ren0_r, bram_ren[0] & ~write_busy_w}; // axibram_read does not mask bram_ren and bram_regen with dev_ready !		// wire [1:0] bram_ren_w = {bram_ren0_r, bram_ren[0] & ~write_busy_w}; // FIXED: axibram_read does not mask bram_ren and bram_regen with dev_ready !


	// assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen ? bram_waddr : pre_awaddr);		// assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen ? bram_waddr : pre_awaddr);
	// assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);		assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
	assign bram_addr = bram_ren_w[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);		// assign bram_addr = bram_ren_w[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);

	assign hba_arst = hba_rst_r; // hba _reset (currently does ~ the same as port reset)		assign hba_arst = hba_rst_r; // hba _reset (currently does ~ the same as port reset)
	assign port_arst = port_rst_r; // port _reset by software		assign port_arst = port_rst_r; // port _reset by software
	@@ -203,7 +203,7 @@ module axi_ahci_regs#(


	always @(posedge aclk) begin		always @(posedge aclk) begin
	bram_ren0_r <= bram_ren_w[0];		/// bram_ren0_r <= bram_ren_w[0];

	if (arst) write_busy_r <= 0;		if (arst) write_busy_r <= 0;
	else if (write_start_burst) write_busy_r <= 1;		else if (write_start_burst) write_busy_r <= 1;
	@@ -211,7 +211,8 @@ module axi_ahci_regs#(

	if (bram_wen) bram_wdata_r <= bram_wdata;		if (bram_wen) bram_wdata_r <= bram_wdata;

	if (bram_ren_w[1]) bram_rdata_r <= bram_rdata;		/// if (bram_ren_w[1]) bram_rdata_r <= bram_rdata;
			if (bram_ren[1]) bram_rdata_r <= bram_rdata;

	bram_wstb_r <= {4{bram_wen}} & bram_wstb;		bram_wstb_r <= {4{bram_wen}} & bram_wstb;

	@@ -403,8 +404,8 @@ sata_phy_rst_out will be released after the sata clock is stable
	.clk_a (aclk), // input		.clk_a (aclk), // input
	.addr_a (bram_addr), // input[9:0]		.addr_a (bram_addr), // input[9:0]
	/// .en_a (bram_ren[0] \|\| write_busy_w), // input		/// .en_a (bram_ren[0] \|\| write_busy_w), // input
	/// .en_a (bram_ren[0] \|\| bram_wen \|\| bram_wen_r), // input		.en_a (bram_ren[0] \|\| bram_wen \|\| bram_wen_r), // input
	.en_a (bram_ren_w[0] \|\| bram_wen \|\| bram_wen_r), // input		/// .en_a (bram_ren_w[0] \|\| bram_wen \|\| bram_wen_r), // input
	.regen_a (1'b0), // input		.regen_a (1'b0), // input
	// .we_a (write_busy_r && !nowrite), // input		// .we_a (write_busy_r && !nowrite), // input
	.we_a (bram_wstb_r), //bram_wen_d), // input[3:0]		.we_a (bram_wstb_r), //bram_wen_d), // input[3:0]

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