started debugging dma write (354a7663) · Commits · Elphel / x393_sata

ahci/ahci_dma.v

+4 −1

ahci/ahci_dma_rd_fifo.v

+14 −3

Original line number	Original line	Diff line number	Diff line
	@@ -59,7 +59,8 @@ module ahci_dma_rd_fifo#(
	// mclk domain		// mclk domain
	output [31:0] dout,		output [31:0] dout,
	output dout_vld,		output dout_vld,
	input dout_re		input dout_re,
			output last_data // pulse @mclk (input done for the last prd - slow send out FIS, no data for 2 clocks - that was the last
	);		);
	localparam ADDRESS_NUM = (1<<ADDRESS_BITS); // 8 for ADDRESS_BITS==3		localparam ADDRESS_NUM = (1<<ADDRESS_BITS); // 8 for ADDRESS_BITS==3
	reg [ADDRESS_BITS : 0] waddr; // 1 extra bit		reg [ADDRESS_BITS : 0] waddr; // 1 extra bit
	@@ -100,7 +101,6 @@ module ahci_dma_rd_fifo#(
	reg flush_r;		reg flush_r;
	wire done_flush_mclk;		wire done_flush_mclk;


	assign din_re = busy && fifo_half_hclk && din_av_safe_r;		assign din_re = busy && fifo_half_hclk && din_av_safe_r;
	assign fifo_wr = en_fifo_wr && fifo_half_hclk && (din_av_safe_r \|\| !busy);		assign fifo_wr = en_fifo_wr && fifo_half_hclk && (din_av_safe_r \|\| !busy);
	assign fifo_di_vld = (busy && (!extra_in \|\| (qwcntr != 0)))? 4'hf : last_mask ;		assign fifo_di_vld = (busy && (!extra_in \|\| (qwcntr != 0)))? 4'hf : last_mask ;
	@@ -182,9 +182,20 @@ module ahci_dma_rd_fifo#(
	.rst (mrst), // input		.rst (mrst), // input
	.src_clk (mclk), // input		.src_clk (mclk), // input
	.dst_clk (hclk), // input		.dst_clk (hclk), // input
	.in_pulse (done_flush_mclk), // input		.in_pulse (flush_r && din_re && (qwcntr == 0)), // input
	.out_pulse (done_flush), // output		.out_pulse (done_flush), // output
	.busy() // output		.busy() // output
	);		);

			pulse_cross_clock #(
			.EXTRA_DLY(0)
			) last_data_i (
			.rst (mrst), // input
			.src_clk (mclk), // input
			.dst_clk (hclk), // input
			.in_pulse (done_flush_mclk), // input
			.out_pulse (last_data), // output
			.busy() // output
			);

	endmodule		endmodule

ahci/ahci_fis_receive.v

+21 −12

Original line number	Original line	Diff line number	Diff line
	@@ -69,7 +69,8 @@ module ahci_fis_receive#(
	input set_sts_80, // set PxTFD.STS = 0x80 (may be combined with set_sts_7f), update		input set_sts_80, // set PxTFD.STS = 0x80 (may be combined with set_sts_7f), update

	input clear_xfer_cntr, // clear pXferCntr (is it needed as a separate input)?		input clear_xfer_cntr, // clear pXferCntr (is it needed as a separate input)?
	input decr_dwc, // decrement DMA Xfer counter // need pulse to 'update_prdbc' to write to registers		input decr_dwcr, // decrement DMA Xfer counter after read (in this module) // need pulse to 'update_prdbc' to write to registers
			input decr_dwcw, // decrement DMA Xfer counter after write (from decr_DXC_dw)// need pulse to 'update_prdbc' to write to registers
	input [11:0] decr_DXC_dw, // decrement value (in DWORDs)		input [11:0] decr_DXC_dw, // decrement value (in DWORDs)

	input pcmd_fre, // control bit enables saving FIS to memory (will be ignored for signature)		input pcmd_fre, // control bit enables saving FIS to memory (will be ignored for signature)
	@@ -89,7 +90,7 @@ module ahci_fis_receive#(
	output reg sactive0, // bit 0 of sActive DWORD received in SDB FIS		output reg sactive0, // bit 0 of sActive DWORD received in SDB FIS
	// Using even word count (will be rounded up), partial DWORD (last) will be handled by PRD length if needed		// Using even word count (will be rounded up), partial DWORD (last) will be handled by PRD length if needed
	output [31:2] xfer_cntr, // transfer counter in words for both DMA (31 bit) and PIO (lower 15 bits), updated after decr_dwc		output [31:2] xfer_cntr, // transfer counter in words for both DMA (31 bit) and PIO (lower 15 bits), updated after decr_dwc
	output reg xfer_cntr_zero,// valid next cycle		output xfer_cntr_zero,// valid next cycle
	output [11:0] data_in_dwords, // number of data dwords received (valid with 'done')		output [11:0] data_in_dwords, // number of data dwords received (valid with 'done')
	// FSM will send this pulse		// FSM will send this pulse
	// output reg data_in_words_apply, // apply data_in_words		// output reg data_in_words_apply, // apply data_in_words
	@@ -147,7 +148,7 @@ localparam DATA_TYPE_OK = 2;
	localparam DATA_TYPE_ERR = 3;		localparam DATA_TYPE_ERR = 3;


			reg xfer_cntr_zero_r;
	wire dma_in_start;		wire dma_in_start;
	wire dma_in_stop;		wire dma_in_stop;
	wire dma_skipping_extra; // skipping extra FIS data not needed for DMA		wire dma_skipping_extra; // skipping extra FIS data not needed for DMA
	@@ -166,6 +167,7 @@ localparam DATA_TYPE_ERR = 3;

	reg fis_rec_run; // running received FIS		reg fis_rec_run; // running received FIS
	reg is_data_fis;		reg is_data_fis;
			reg is_ignore;

	wire is_FIS_HEAD = data_in_ready && (hba_data_in_type == DATA_TYPE_FIS_HEAD);		wire is_FIS_HEAD = data_in_ready && (hba_data_in_type == DATA_TYPE_FIS_HEAD);
	wire is_FIS_NOT_HEAD = data_in_ready && (hba_data_in_type != DATA_TYPE_FIS_HEAD);		wire is_FIS_NOT_HEAD = data_in_ready && (hba_data_in_type != DATA_TYPE_FIS_HEAD);
	@@ -206,6 +208,8 @@ localparam DATA_TYPE_ERR = 3;
	reg fis_first_invalid_r;		reg fis_first_invalid_r;
	reg fis_first_flushing_r;		reg fis_first_flushing_r;

			assign xfer_cntr_zero = xfer_cntr_zero_r;

	// Forward data to DMA (dev->mem) engine		// Forward data to DMA (dev->mem) engine
	assign dma_in_valid = dma_in && dma_in_ready && (hba_data_in_type == DATA_TYPE_DMA) && data_in_ready && !too_long_err;		assign dma_in_valid = dma_in && dma_in_ready && (hba_data_in_type == DATA_TYPE_DMA) && data_in_ready && !too_long_err;
	// Will also try to skip to the end of too long FIS		// Will also try to skip to the end of too long FIS
	@@ -278,6 +282,7 @@ localparam DATA_TYPE_ERR = 3;
	reg_ps <= get_psfis ? 1 : 0;		reg_ps <= get_psfis ? 1 : 0;
	reg_d2h <= get_rfis ? 1 : 0;		reg_d2h <= get_rfis ? 1 : 0;
	reg_sdb <= get_rfis ? 1 : 0;		reg_sdb <= get_rfis ? 1 : 0;
			is_ignore <= get_ignore ? 1 : 0;
	end else if (wreg_we_r && !dwords_over) begin		end else if (wreg_we_r && !dwords_over) begin
	fis_dcount <= fis_dcount - 1; // update even if not writing to registers		fis_dcount <= fis_dcount - 1; // update even if not writing to registers
	if (fis_save) reg_addr_r <= reg_addr_r + 1; // update only when writing to registers		if (fis_save) reg_addr_r <= reg_addr_r + 1; // update only when writing to registers
	@@ -295,9 +300,11 @@ localparam DATA_TYPE_ERR = 3;

	if (hba_rst \|\|get_fis) dwords_over <= 0;		if (hba_rst \|\|get_fis) dwords_over <= 0;
	else if (wreg_we_r && !(\|fis_dcount)) dwords_over <= 1;		else if (wreg_we_r && !(\|fis_dcount)) dwords_over <= 1;
			/// else if (wreg_we_r && (!(\|fis_dcount) \|\| is_fis_end)) dwords_over <= 1;

	if (hba_rst) wreg_we_r <= 0;		if (hba_rst) wreg_we_r <= 0;
	else wreg_we_r <= fis_rec_run && data_in_ready && !is_fis_end && !dwords_over && (\|fis_dcount \|\| !wreg_we_r);		else wreg_we_r <= fis_rec_run && data_in_ready && !is_fis_end && !dwords_over && (\|fis_dcount \|\| !wreg_we_r) &&
			(!is_ignore \|\| !wreg_we_r); // Ignore - unknown length, ned to look for is_fis_end with latency

	fis_end_r <= {fis_end_r[0], fis_end_w};		fis_end_r <= {fis_end_r[0], fis_end_w};

	@@ -363,13 +370,15 @@ localparam DATA_TYPE_ERR = 3;
	if (reg_sdb[1]) sactive0 <= hba_data_in[0];		if (reg_sdb[1]) sactive0 <= hba_data_in[0];

	if (hba_rst \|\| reg_sdb[0] \|\| clear_xfer_cntr) xfer_cntr_r[31:2] <= 0;		if (hba_rst \|\| reg_sdb[0] \|\| clear_xfer_cntr) xfer_cntr_r[31:2] <= 0;
	else if (reg_ps[4] \|\| reg_ds[5]) xfer_cntr_r[31:2] <= {reg_ds[5]?hba_data_in[31:16]:16'b0, hba_data_in[15:2]} + hba_data_in[1]; // round up		else if (reg_ps[4] \|\| reg_ds[5]) xfer_cntr_r[31:2] <= {reg_ds[5]?hba_data_in[31:16]:16'b0,
	else if (decr_dwc) xfer_cntr_r[31:2] <= {xfer_cntr_r[31:2]} - {18'b0, decr_DXC_dw[11:0]};		hba_data_in[15:2]} + hba_data_in[1]; // round up
			else if ((decr_dwcw \|\| decr_dwcr) && !xfer_cntr_zero_r) xfer_cntr_r[31:2] <= {xfer_cntr_r[31:2]} -
			{18'b0, decr_dwcr? data_in_dwords: decr_DXC_dw[11:0]};

	if (hba_rst \|\| reg_sdb[0] \|\| reg_ps[4] \|\| reg_ds[5]) prdbc_r[31:2] <= 0;		if (hba_rst \|\| reg_sdb[0] \|\| reg_ps[4] \|\| reg_ds[5]) prdbc_r[31:2] <= 0;
	else if (decr_dwc) prdbc_r[31:2] <= {prdbc_r[31:2]} + {18'b0, decr_DXC_dw[11:0]};		else if (decr_dwcw \|\| decr_dwcr) prdbc_r[31:2] <= {prdbc_r[31:2]} + {18'b0, decr_dwcr? data_in_dwords: decr_DXC_dw[11:0]};

	xfer_cntr_zero <= xfer_cntr_r[31:2] == 0;		xfer_cntr_zero_r <= xfer_cntr_r[31:2] == 0;

	update_err_sts_r <= update_pio \|\| update_err_sts \|\| clear_bsy_drq \|\| set_bsy \|\| set_sts_7f \|\| set_sts_80;		update_err_sts_r <= update_pio \|\| update_err_sts \|\| clear_bsy_drq \|\| set_bsy \|\| set_sts_7f \|\| set_sts_80;
	// update_pio_r <= update_pio;		// update_pio_r <= update_pio;

ahci/ahci_fis_transmit.v

+32 −12

Original line number	Original line	Diff line number	Diff line
	@@ -72,6 +72,7 @@ module ahci_fis_transmit #(

	// ahci_fis_receive interface		// ahci_fis_receive interface
	input [31:2] xfer_cntr, // transfer counter in words for both DMA (31 bit) and PIO (lower 15 bits), updated after decr_dwc		input [31:2] xfer_cntr, // transfer counter in words for both DMA (31 bit) and PIO (lower 15 bits), updated after decr_dwc
			input xfer_cntr_zero, // transfer counter was not set


	output dma_ctba_ld, // load command table address from		output dma_ctba_ld, // load command table address from
	@@ -91,6 +92,7 @@ module ahci_fis_transmit #(
	input [31:0] dma_out, // 32-bit data from the DMA module, HBA -> device port		input [31:0] dma_out, // 32-bit data from the DMA module, HBA -> device port
	input dma_dav, // at least one dword is ready to be read from DMA module		input dma_dav, // at least one dword is ready to be read from DMA module
	output dma_re, // read dword from DMA module to the output register		output dma_re, // read dword from DMA module to the output register
			input last_h2d_data,// single pulse, after it watch for FIS end (no data for 2 clocks)

	// Data System memory or FIS -> device		// Data System memory or FIS -> device
	output reg [31:0] todev_data, // 32-bit data from the system memory to HBA (dma data)		output reg [31:0] todev_data, // 32-bit data from the system memory to HBA (dma data)
	@@ -108,7 +110,7 @@ module ahci_fis_transmit #(
	wire [1:0] fis_data_type;		wire [1:0] fis_data_type;
	wire [31:0] fis_data_out;		wire [31:0] fis_data_out;

	wire write_or_w = (dma_en_r?(dma_dav && todev_ready):fis_data_valid); // do not fill the buffer if FIFO is not ready for DMA,		wire write_or_w;
	// for fis_data_valid - longer latency		// for fis_data_valid - longer latency
	// wire fis_out_w = !dma_en_r && fis_data_valid && todev_ready;		// wire fis_out_w = !dma_en_r && fis_data_valid && todev_ready;
	wire dma_re_w = dma_en_r && dma_dav && todev_ready;		wire dma_re_w = dma_en_r && dma_dav && todev_ready;
	@@ -154,7 +156,7 @@ module ahci_fis_transmit #(
	reg fis_dw_first;		reg fis_dw_first;
	wire fis_dw_last;		wire fis_dw_last;

	reg [11:2] dx_dwords_left;		reg [11:0] dx_dwords_left;
	reg dx_fis_pend_r; // waiting to send first DWORD of the H2D data transfer		reg dx_fis_pend_r; // waiting to send first DWORD of the H2D data transfer
	wire dx_dma_last_w; // sending last adat word		wire dx_dma_last_w; // sending last adat word
	reg dx_busy_r;		reg dx_busy_r;
	@@ -166,9 +168,16 @@ module ahci_fis_transmit #(
	wire done_w = xmit_ok_r \|\| ((\|dx_err_r) && dx_busy_r) \|\| dma_start; // done on last transmit or error		wire done_w = xmit_ok_r \|\| ((\|dx_err_r) && dx_busy_r) \|\| dma_start; // done on last transmit or error

	reg fetch_cmd_busy_r;		reg fetch_cmd_busy_r;
			reg xfer_cntr_not_set;

	assign todev_valid = todev_full_r;		reg watch_prd_end;
			wire masked_last_h2d_data = xfer_cntr_not_set && last_h2d_data; // otherwise use xfer counter to find FIS end
			wire watch_prd_end_w = masked_last_h2d_data \|\| watch_prd_end; // Maybe not needed - just use watch_prd_end
			// reg [1:0] was_dma_re; // previous values of dma_re
			reg [2:0] was_dma_ndav; // inverted/masked previous values of dma_dav
			wire send_last_w = was_dma_ndav[2];
			// assign todev_valid = todev_full_r;
			assign todev_valid = todev_full_r && (!watch_prd_end_w \|\| dma_dav \|\| send_last_w);
	assign dma_re = dma_re_w;		assign dma_re = dma_re_w;
	assign reg_re = reg_re_r[1:0];		assign reg_re = reg_re_r[1:0];

	@@ -193,10 +202,13 @@ module ahci_fis_transmit #(
	assign fis_data_type = {fis_dw_last, (write_or_w && dx_fis_pend_r) \| (fis_dw_first && ct_stb)};		assign fis_data_type = {fis_dw_last, (write_or_w && dx_fis_pend_r) \| (fis_dw_first && ct_stb)};

	assign fis_data_out = ({32{dx_fis_pend_r}} & DATA_FIS) \| ({32{ct_stb}} & ct_data) ;		assign fis_data_out = ({32{dx_fis_pend_r}} & DATA_FIS) \| ({32{ct_stb}} & ct_data) ;
	assign dx_dma_last_w = dma_en_r && dma_re_w && (dx_dwords_left[11:2] == 1);		assign dx_dma_last_w = dma_en_r && dma_re_w && (dx_dwords_left[11:0] == 1);

	assign dx_err = dx_err_r;		assign dx_err = dx_err_r;
	assign dma_dev_wr = ch_w_r;		assign dma_dev_wr = ch_w_r;
			/// assign write_or_w = (dma_en_r?(dma_dav && todev_ready && ()):fis_data_valid); // do not fill the buffer if FIFO is not ready for DMA,
			assign write_or_w = (dma_en_r?(dma_dav && todev_ready && (!todev_full_r \|\| watch_prd_end_w)):fis_data_valid); // do not fill the buffer if FIFO is not ready for DMA,
			// When watching for FIS end, do not fill/use output register in the same cycle

	always @ (posedge mclk) begin		always @ (posedge mclk) begin
	// Mutliplex between DMA and FIS output to the output routed to transmit FIFO		// Mutliplex between DMA and FIS output to the output routed to transmit FIFO
	@@ -209,7 +221,13 @@ module ahci_fis_transmit #(

	if (hba_rst) todev_type <= 3; // invalid? - no, now first and last word in command FIS (impossible?)		if (hba_rst) todev_type <= 3; // invalid? - no, now first and last word in command FIS (impossible?)
	else if (write_or_w) todev_type <= dma_en_r? {dx_dma_last_w, 1'b0} : fis_data_type;		else if (write_or_w) todev_type <= dma_en_r? {dx_dma_last_w, 1'b0} : fis_data_type;
			else if (was_dma_ndav[1]) todev_type <= {1'b1, 1'b0}; // type = last in FIS

			if (hba_rst) was_dma_ndav <= 0;
			else was_dma_ndav <= {was_dma_ndav[1:0], ~dma_dav & todev_full_r & watch_prd_end_w} ;

			if (hba_rst \|\| dx_xmit \|\| done_w) watch_prd_end <= 0;
			else if (masked_last_h2d_data) watch_prd_end <= 1;
	// Read 3 DWORDs from the command header		// Read 3 DWORDs from the command header

	if (hba_rst) fetch_chead_r <= 0; // running 1		if (hba_rst) fetch_chead_r <= 0; // running 1
	@@ -291,8 +309,10 @@ module ahci_fis_transmit #(

	//TODO: update xfer length, prdtl (only after R_OK) - yes, do it outside		//TODO: update xfer length, prdtl (only after R_OK) - yes, do it outside

	if (dx_xmit) dx_dwords_left[11:2] <= (\|xfer_cntr[31:11])?10'h200:{1'b0,xfer_cntr[10:2]};		if (dx_xmit) xfer_cntr_not_set <= xfer_cntr_zero; // if it was zero - rely on PRDs
	else if (dma_re_w) dx_dwords_left[11:2] <= dx_dwords_left[11:2] - 1;
			if (dx_xmit) dx_dwords_left[11:0] <= (xfer_cntr_zero \|\| (\|xfer_cntr[31:13])) ? 12'h800 : {1'b0,xfer_cntr[12:2]};
			else if (dma_re_w) dx_dwords_left[11:0] <= dx_dwords_left[11:0] - 1;

	if (dx_xmit) dwords_sent <= 0;		if (dx_xmit) dwords_sent <= 0;
	else if (dma_re_w) dwords_sent <= dwords_sent + 1;		else if (dma_re_w) dwords_sent <= dwords_sent + 1;

ahci/ahci_fsm.v

+9 −7

Original line number	Original line	Diff line number	Diff line
	@@ -141,7 +141,7 @@ module ahci_fsm
	/// input dma_prd_done, // output (finished next prd)		/// input dma_prd_done, // output (finished next prd)
	output dma_prd_irq_clear, // reset pending prd_irq		output dma_prd_irq_clear, // reset pending prd_irq
	input dma_prd_irq_pend, // prd interrupt pending. This is just a condition for irq - actual will be generated after FIS OK		input dma_prd_irq_pend, // prd interrupt pending. This is just a condition for irq - actual will be generated after FIS OK
	/// input dma_cmd_busy, // output reg (DMA engine is processing PRDs)		input dma_cmd_busy, // output reg (DMA engine is processing PRDs)
	/// input dma_cmd_done, // output (last PRD is over)		/// input dma_cmd_done, // output (last PRD is over)
	output dma_cmd_abort, // try to abort a command		output dma_cmd_abort, // try to abort a command

	@@ -189,7 +189,8 @@ module ahci_fsm
	output set_sts_80, // set PxTFD.STS = 0x80 (may be combined with set_sts_7f), update		output set_sts_80, // set PxTFD.STS = 0x80 (may be combined with set_sts_7f), update
	output clear_xfer_cntr, // clear pXferCntr (is it needed as a separate input)?		output clear_xfer_cntr, // clear pXferCntr (is it needed as a separate input)?

	output decr_dwc, // decrement DMA Xfer counter // need pulse to 'update_prdbc' to write to registers		output decr_dwcr, // decrement DMA Xfer counter after read // need pulse to 'update_prdbc' to write to registers
			output decr_dwcw, // decrement DMA Xfer counter after write // need pulse to 'update_prdbc' to write to registers
	// output [11:0] decr_DXC_dw, // decrement value (in DWORDs)		// output [11:0] decr_DXC_dw, // decrement value (in DWORDs)
	input pxcmd_fre, // control bit enables saving FIS to memory		input pxcmd_fre, // control bit enables saving FIS to memory
	input pPioXfer, // state variable		input pPioXfer, // state variable
	@@ -422,7 +423,8 @@ module ahci_fsm
	.SET_STS_7F (set_sts_7f), // output reg		.SET_STS_7F (set_sts_7f), // output reg
	.SET_STS_80 (set_sts_80), // output reg		.SET_STS_80 (set_sts_80), // output reg
	.XFER_CNTR_CLEAR (clear_xfer_cntr), // output reg		.XFER_CNTR_CLEAR (clear_xfer_cntr), // output reg
	.DECR_DWC (decr_dwc), // output reg		.DECR_DWCR (decr_dwcr), // output reg
			.DECR_DWCW (decr_dwcw), // output reg
	.FIS_FIRST_FLUSH (fis_first_flush), // output reg		.FIS_FIRST_FLUSH (fis_first_flush), // output reg
	// FIS_TRANSMIT		// FIS_TRANSMIT
	.CLEAR_CMD_TO_ISSUE (clearCmdToIssue), // output reg		.CLEAR_CMD_TO_ISSUE (clearCmdToIssue), // output reg
	@@ -492,8 +494,8 @@ module ahci_fsm
	.PIO_I (pio_i), // input		.PIO_I (pio_i), // input
	.NPD (!pio_d), // input pio_d = 0 , "ch_a == 1" is not needed		.NPD (!pio_d), // input pio_d = 0 , "ch_a == 1" is not needed
	.PIOX (pPioXfer), // input		.PIOX (pPioXfer), // input
	.XFER0 (xfer_cntr_zero), // input xfer_cntr_zero		.XFER0 (xfer_cntr_zero && !dma_cmd_busy), // input xfer_cntr_zero
	.PIOX_XFER0 (pPioXfer && xfer_cntr_zero), // input pPioXfer && xfer_cntr_zero		.PIOX_XFER0 (pPioXfer && xfer_cntr_zero &&!dma_cmd_busy), // input pPioXfer && xfer_cntr_zero
	// FIS_TRANSMIT		// FIS_TRANSMIT
	.CTBAA_CTBAP (ch_a && ch_p), // input		.CTBAA_CTBAP (ch_a && ch_p), // input
	.CTBAP (ch_p), // input		.CTBAP (ch_p), // input

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