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Commit 256f87fb authored by Alexey Grebenkin's avatar Alexey Grebenkin
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Some changes to simplify ongoing synchronization with master branch (vdt version)

parent 680098f2
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Showing with 301 additions and 270 deletions
device/oob_dev.v
View file @ 256f87fb
...@@ -121,6 +121,8 @@ end ...@@ -121,6 +121,8 @@ end
reg [9:0] txelecidle_cnt; reg [9:0] txelecidle_cnt;
wire aligndet;
wire syncdet;
assign aligndet = ~|(rxdata ^ {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}) & ~|(rxcharisk ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5} assign aligndet = ~|(rxdata ^ {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}) & ~|(rxcharisk ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5}
assign syncdet = ~|(rxdata ^ {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}) & ~|(rxcharisk ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3} assign syncdet = ~|(rxdata ^ {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}) & ~|(rxcharisk ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3}
......
device/sata_phy_dev.v
View file @ 256f87fb
...@@ -52,9 +52,6 @@ module sata_phy_dev #( ...@@ -52,9 +52,6 @@ module sata_phy_dev #(
input wire [3:0] ll_charisk_in input wire [3:0] ll_charisk_in
); );
parameter CHIPSCOPE = "FALSE";
wire txcomfinish;
wire [31:0] txdata; wire [31:0] txdata;
wire [31:0] txdata_oob; wire [31:0] txdata_oob;
wire [3:0] txcharisk; wire [3:0] txcharisk;
...@@ -164,7 +161,7 @@ localparam RXEYERESET_TIME = 7'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + R ...@@ -164,7 +161,7 @@ localparam RXEYERESET_TIME = 7'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + R
reg [6:0] rxeyereset_cnt; reg [6:0] rxeyereset_cnt;
assign rxeyereset_done = rxeyereset_cnt == RXEYERESET_TIME; assign rxeyereset_done = rxeyereset_cnt == RXEYERESET_TIME;
always @ (posedge gtrefclk) always @ (posedge gtrefclk)
rxeyereset_cnt <= rxreset ? 3'h0 : rxeyereset_done ? rxeyereset_cnt : rxeyereset_cnt + 1'b1; rxeyereset_cnt <= rxreset ? 7'h0 : rxeyereset_done ? rxeyereset_cnt : rxeyereset_cnt + 1'b1;
/* /*
* Resets * Resets
...@@ -503,12 +500,12 @@ gtx( ...@@ -503,12 +500,12 @@ gtx(
.CPLLREFCLKLOST (), .CPLLREFCLKLOST (),
.CPLLREFCLKSEL (3'b001), .CPLLREFCLKSEL (3'b001),
.CPLLRESET (cpllreset), .CPLLRESET (cpllreset),
.GTRSVD (1'b0), .GTRSVD (16'b0),
.PCSRSVDIN (1'b0), .PCSRSVDIN (16'b0),
.PCSRSVDIN2 (1'b0), .PCSRSVDIN2 (5'b0),
.PMARSVDIN (1'b0), .PMARSVDIN (5'b0),
.PMARSVDIN2 (1'b0), .PMARSVDIN2 (5'b0),
.TSTIN (1'b1), .TSTIN (20'b1),
.TSTOUT (), .TSTOUT (),
.CLKRSVD (4'b0000), .CLKRSVD (4'b0000),
.GTGREFCLK (1'b0), .GTGREFCLK (1'b0),
...@@ -714,7 +711,7 @@ gtx( ...@@ -714,7 +711,7 @@ gtx(
.TXPCSRESET (txpcsreset), .TXPCSRESET (txpcsreset),
.TXPMARESET (1'b0), .TXPMARESET (1'b0),
.TXRESETDONE (txresetdone), .TXRESETDONE (txresetdone),
.TXCOMFINISH (txcomfinish), .TXCOMFINISH (),
.TXCOMINIT (txcominit), .TXCOMINIT (txcominit),
.TXCOMSAS (1'b0), .TXCOMSAS (1'b0),
.TXCOMWAKE (txcomwake), .TXCOMWAKE (txcomwake),
...@@ -740,6 +737,8 @@ assign rxchariscomma = twobytes_shift ? {rxchariscomma_gtx[7:4], rxchariscomm ...@@ -740,6 +737,8 @@ assign rxchariscomma = twobytes_shift ? {rxchariscomma_gtx[7:4], rxchariscomm
assign rxdisperr = twobytes_shift ? {rxdisperr_gtx[7:4] , rxdisperr_gtx[1:0] , rxdisperr_gtx[3:2] } : rxdisperr_gtx; assign rxdisperr = twobytes_shift ? {rxdisperr_gtx[7:4] , rxdisperr_gtx[1:0] , rxdisperr_gtx[3:2] } : rxdisperr_gtx;
assign rxnotintable = twobytes_shift ? {rxnotintable_gtx[7:4] , rxnotintable_gtx[1:0] , rxnotintable_gtx[3:2] } : rxnotintable_gtx; assign rxnotintable = twobytes_shift ? {rxnotintable_gtx[7:4] , rxnotintable_gtx[1:0] , rxnotintable_gtx[3:2] } : rxnotintable_gtx;
assign ll_err_out = rxdisperr[3:0] | rxnotintable[3:0];
/* /*
* Interfaces * Interfaces
*/ */
...@@ -751,7 +750,7 @@ assign rxn = rxn_in; ...@@ -751,7 +750,7 @@ assign rxn = rxn_in;
assign rxp = rxp_in; assign rxp = rxp_in;
assign txn_out = txn; assign txn_out = txn;
assign txp_out = txp; assign txp_out = txp;
assign ll_data_out = rxdata_out; assign ll_data_out = rxdata_out[31:0];
assign ll_charisk_out = rxcharisk_out; assign ll_charisk_out = rxcharisk_out;
assign txdata_in = ll_data_in; assign txdata_in = ll_data_in;
assign txcharisk_in = ll_charisk_in; assign txcharisk_in = ll_charisk_in;
......
dma/axi_regs.v
View file @ 256f87fb
...@@ -20,10 +20,7 @@ ...@@ -20,10 +20,7 @@
*******************************************************************************/ *******************************************************************************/
`include "axibram_read.v" `include "axibram_read.v"
`include "axibram_write.v" `include "axibram_write.v"
module axi_regs #( module axi_regs(
parameter REGISTERS_CNT = 20
)
(
input wire ACLK, // AXI PS Master GP1 Clock , input input wire ACLK, // AXI PS Master GP1 Clock , input
input wire ARESETN, // AXI PS Master GP1 Reset, output input wire ARESETN, // AXI PS Master GP1 Reset, output
// AXI PS Master GP1: Read Address // AXI PS Master GP1: Read Address
...@@ -31,13 +28,9 @@ module axi_regs #( ...@@ -31,13 +28,9 @@ module axi_regs #(
input wire ARVALID, // AXI PS Master GP1 ARVALID, output input wire ARVALID, // AXI PS Master GP1 ARVALID, output
output wire ARREADY, // AXI PS Master GP1 ARREADY, input output wire ARREADY, // AXI PS Master GP1 ARREADY, input
input wire [11:0] ARID, // AXI PS Master GP1 ARID[11:0], output input wire [11:0] ARID, // AXI PS Master GP1 ARID[11:0], output
input wire [1:0] ARLOCK, // AXI PS Master GP1 ARLOCK[1:0], output
input wire [3:0] ARCACHE, // AXI PS Master GP1 ARCACHE[3:0], output
input wire [2:0] ARPROT, // AXI PS Master GP1 ARPROT[2:0], output
input wire [3:0] ARLEN, // AXI PS Master GP1 ARLEN[3:0], output input wire [3:0] ARLEN, // AXI PS Master GP1 ARLEN[3:0], output
input wire [1:0] ARSIZE, // AXI PS Master GP1 ARSIZE[1:0], output input wire [1:0] ARSIZE, // AXI PS Master GP1 ARSIZE[1:0], output
input wire [1:0] ARBURST, // AXI PS Master GP1 ARBURST[1:0], output input wire [1:0] ARBURST, // AXI PS Master GP1 ARBURST[1:0], output
input wire [3:0] ARQOS, // AXI PS Master GP1 ARQOS[3:0], output
// AXI PS Master GP1: Read Data // AXI PS Master GP1: Read Data
output wire [31:0] RDATA, // AXI PS Master GP1 RDATA[31:0], input output wire [31:0] RDATA, // AXI PS Master GP1 RDATA[31:0], input
output wire RVALID, // AXI PS Master GP1 RVALID, input output wire RVALID, // AXI PS Master GP1 RVALID, input
...@@ -50,13 +43,9 @@ module axi_regs #( ...@@ -50,13 +43,9 @@ module axi_regs #(
input wire AWVALID, // AXI PS Master GP1 AWVALID, output input wire AWVALID, // AXI PS Master GP1 AWVALID, output
output wire AWREADY, // AXI PS Master GP1 AWREADY, input output wire AWREADY, // AXI PS Master GP1 AWREADY, input
input wire [11:0] AWID, // AXI PS Master GP1 AWID[11:0], output input wire [11:0] AWID, // AXI PS Master GP1 AWID[11:0], output
input wire [1:0] AWLOCK, // AXI PS Master GP1 AWLOCK[1:0], output
input wire [3:0] AWCACHE, // AXI PS Master GP1 AWCACHE[3:0], output
input wire [2:0] AWPROT, // AXI PS Master GP1 AWPROT[2:0], output
input wire [3:0] AWLEN, // AXI PS Master GP1 AWLEN[3:0], outpu:t input wire [3:0] AWLEN, // AXI PS Master GP1 AWLEN[3:0], outpu:t
input wire [1:0] AWSIZE, // AXI PS Master GP1 AWSIZE[1:0], output input wire [1:0] AWSIZE, // AXI PS Master GP1 AWSIZE[1:0], output
input wire [1:0] AWBURST, // AXI PS Master GP1 AWBURST[1:0], output input wire [1:0] AWBURST, // AXI PS Master GP1 AWBURST[1:0], output
input wire [3:0] AWQOS, // AXI PS Master GP1 AWQOS[3:0], output
// AXI PS Master GP1: Write Data // AXI PS Master GP1: Write Data
input wire [31:0] WDATA, // AXI PS Master GP1 WDATA[31:0], output input wire [31:0] WDATA, // AXI PS Master GP1 WDATA[31:0], output
input wire WVALID, // AXI PS Master GP1 WVALID, output input wire WVALID, // AXI PS Master GP1 WVALID, output
......
dma/dma_adapter.v
View file @ 256f87fb
...@@ -96,7 +96,7 @@ assign rd_start = set_busy & ~cmd_type; ...@@ -96,7 +96,7 @@ assign rd_start = set_busy & ~cmd_type;
always @ (posedge clk) always @ (posedge clk)
begin begin
cmd_type_r <= rst ? 1'b0 : set_busy ? cmd_type : cmd_type_r; cmd_type_r <= rst ? 1'b0 : set_busy ? cmd_type : cmd_type_r;
cmd_addr_r <= rst ? 1'b0 : set_busy ? cmd_addr : cmd_addr_r; cmd_addr_r <= rst ? 25'b0 : set_busy ? cmd_addr[31:7] : cmd_addr_r[31:7];
cmd_busy_r <= (cmd_busy_r | set_busy) & ~rst & ~clr_busy; cmd_busy_r <= (cmd_busy_r | set_busy) & ~rst & ~clr_busy;
end end
...@@ -123,24 +123,28 @@ always @ (posedge clk) ...@@ -123,24 +123,28 @@ always @ (posedge clk)
reg [3:0] rdwr_state; reg [3:0] rdwr_state;
// Get data from buffer // Get data from buffer
localparam READ_IDLE = 0; localparam IDLE = 0;
//localparam READ_IDLE = 0;
localparam READ_WAIT_ADDR = 3; localparam READ_WAIT_ADDR = 3;
localparam READ_DATA = 4; localparam READ_DATA = 4;
reg rd_reset_page; wire rd_reset_page;
reg rd_next_page; reg rd_next_page;
reg rd_data; wire [63:0] rd_data;
reg [6:0] rd_data_count; reg [6:0] rd_data_count;
reg rd_en; reg rd_en;
wire rd_stop; wire rd_stop;
wire rd_cnt_to_pull; wire [6:0] rd_cnt_to_pull;
assign rd_cnt_to_pull = 7'hf; assign rd_cnt_to_pull = 7'hf;
assign rd_stop = rd_ack_in & rd_data_count == rd_cnt_to_pull; assign rd_stop = rd_ack_in & rd_data_count == rd_cnt_to_pull;
assign rd_reset_page = 1'b0;
assign rd_data = buf_rdata;
assign rd_val_out = rd_en;
assign rd_data_out = rd_data; assign rd_data_out = rd_data;
always @ (posedge clk) /*always @ (posedge clk)
if (rst) if (rst)
begin begin
rdwr_state <= READ_IDLE; rdwr_state <= READ_IDLE;
...@@ -184,10 +188,10 @@ always @ (posedge clk) ...@@ -184,10 +188,10 @@ always @ (posedge clk)
rd_en <= 1'b0; rd_en <= 1'b0;
end end
endcase endcase
*/
// Put data into buffer // Put data into buffer
localparam WRITE_IDLE = 0; //localparam WRITE_IDLE = 0;
localparam WRITE_DATA = 1; localparam WRITE_DATA = 1;
localparam WRITE_WAIT_ADDR = 2; localparam WRITE_WAIT_ADDR = 2;
reg wr_en; reg wr_en;
...@@ -212,6 +216,11 @@ assign wr_ack_out = wr_val_in & rdwr_state == WRITE_DATA; ...@@ -212,6 +216,11 @@ assign wr_ack_out = wr_val_in & rdwr_state == WRITE_DATA;
always @ (posedge clk) always @ (posedge clk)
if (rst) if (rst)
begin begin
rdwr_state <= IDLE;
rd_done <= 1'b0;
rd_data_count <= 7'h0;
rd_next_page <= 1'b0;
rd_en <= 1'b0;
wr_done <= 1'b0; wr_done <= 1'b0;
wr_data_count <= 7'd0; wr_data_count <= 7'd0;
wr_val <= 1'b0; wr_val <= 1'b0;
...@@ -220,12 +229,16 @@ always @ (posedge clk) ...@@ -220,12 +229,16 @@ always @ (posedge clk)
wr_reset_page <= 1'b0; wr_reset_page <= 1'b0;
wr_en <= 1'b0; wr_en <= 1'b0;
wr_page_ready <= 1'b0; wr_page_ready <= 1'b0;
rdwr_state <= WRITE_IDLE;
end end
else else
case (rdwr_state) case (rdwr_state)
WRITE_IDLE: IDLE:
begin begin
rdwr_state <= rd_start ? READ_WAIT_ADDR : wr_start ? WRITE_DATA : IDLE;
rd_done <= 1'b0;
rd_data_count <= 7'h0;
rd_next_page <= 1'b0;
rd_en <= 1'b0;
wr_data_count <= 7'd0; wr_data_count <= 7'd0;
wr_done <= 1'b0; wr_done <= 1'b0;
wr_data <= 64'h0; wr_data <= 64'h0;
...@@ -233,30 +246,67 @@ always @ (posedge clk) ...@@ -233,30 +246,67 @@ always @ (posedge clk)
wr_reset_page <= wr_start ? 1'b1 : 1'b0; wr_reset_page <= wr_start ? 1'b1 : 1'b0;
wr_en <= 1'b0; wr_en <= 1'b0;
wr_page_ready <= 1'b0; wr_page_ready <= 1'b0;
rdwr_state <= wr_start ? WRITE_DATA : WRITE_IDLE;
end end
WRITE_DATA: WRITE_DATA:
begin begin
wr_done <= wr_stop & membr_state == WRITE_IDLE ? 1'b1 : 1'b0; wr_done <= wr_stop & membr_state == IDLE ? 1'b1 : 1'b0;
wr_data_count <= wr_val_in ? wr_data_count + 1'b1 : wr_data_count; wr_data_count <= wr_val_in ? wr_data_count + 1'b1 : wr_data_count;
wr_data <= wr_data_in; wr_data <= wr_data_in;
wr_next_page <= wr_stop ? 1'b1 : 1'b0; wr_next_page <= wr_stop ? 1'b1 : 1'b0;
wr_reset_page <= 1'b0; wr_reset_page <= 1'b0;
wr_en <= wr_val_in; wr_en <= wr_val_in;
wr_page_ready <= wr_stop ? 1'b1 : 1'b0; wr_page_ready <= wr_stop ? 1'b1 : 1'b0;
rdwr_state <= wr_stop & membr_state == WRITE_IDLE ? WRITE_IDLE : rdwr_state <= wr_stop & membr_state == IDLE ? IDLE :
wr_stop ? WRITE_WAIT_ADDR : WRITE_DATA; wr_stop ? WRITE_WAIT_ADDR : WRITE_DATA;
rd_done <= 1'b0;
rd_data_count <= 7'h0;
rd_next_page <= 1'b0;
rd_en <= 1'b0;
end end
WRITE_WAIT_ADDR: // in case all data is written into a buffer, but address is still being issued on axi bus WRITE_WAIT_ADDR: // in case all data is written into a buffer, but address is still being issued on axi bus
begin begin
wr_done <= membr_state == WRITE_IDLE ? 1'b1 : 1'b0; wr_done <= membr_state == IDLE ? 1'b1 : 1'b0;
wr_data_count <= 7'd0;
wr_data <= 64'h0;
wr_next_page <= 1'b0;
wr_reset_page <= 1'b0;
wr_en <= 1'b0;
wr_page_ready <= 1'b0;
rdwr_state <= membr_state == IDLE ? IDLE : WRITE_WAIT_ADDR;
rd_done <= 1'b0;
rd_data_count <= 7'h0;
rd_next_page <= 1'b0;
rd_en <= 1'b0;
end
READ_WAIT_ADDR: // wait until address information is sent to the bus and input buffer got data
begin
rdwr_state <= membr_state == IDLE & rdata_done ? READ_DATA : READ_WAIT_ADDR;
rd_done <= 1'b0;
rd_data_count <= 7'h0;
rd_next_page <= 1'b0;
rd_en <= 1'b0;
wr_done <= 1'b0;
wr_data_count <= 7'd0;
wr_data <= 64'h0;
wr_next_page <= 1'b0;
wr_reset_page <= 1'b0;
wr_en <= 1'b0;
wr_page_ready <= 1'b0;
end
READ_DATA:
begin
rdwr_state <= rd_stop ? IDLE : READ_DATA;
rd_done <= rd_stop ? 1'b1 : 1'b0;
rd_data_count <= rd_ack_in ? rd_data_count + 1'b1 : rd_data_count;
rd_next_page <= rd_stop ? 1'b1 : 1'b0;
rd_en <= rd_ack_in ? 1'b1 : 1'b0;
wr_done <= 1'b0;
wr_data_count <= 7'd0; wr_data_count <= 7'd0;
wr_data <= 64'h0; wr_data <= 64'h0;
wr_next_page <= 1'b0; wr_next_page <= 1'b0;
wr_reset_page <= 1'b0; wr_reset_page <= 1'b0;
wr_en <= 1'b0; wr_en <= 1'b0;
wr_page_ready <= 1'b0; wr_page_ready <= 1'b0;
rdwr_state <= membr_state == WRITE_IDLE ? WRITE_IDLE : WRITE_WAIT_ADDR;
end end
default: // read is executed default: // read is executed
begin begin
...@@ -267,7 +317,11 @@ always @ (posedge clk) ...@@ -267,7 +317,11 @@ always @ (posedge clk)
wr_reset_page <= 1'b0; wr_reset_page <= 1'b0;
wr_en <= 1'b0; wr_en <= 1'b0;
wr_page_ready <= 1'b0; wr_page_ready <= 1'b0;
rdwr_state <= rdwr_state; rdwr_state <= IDLE;
rd_done <= 1'b0;
rd_data_count <= 7'h0;
rd_next_page <= 1'b0;
rd_en <= 1'b0;
end end
endcase endcase
...@@ -296,7 +350,7 @@ localparam MEMBR_SIZE = 5; ...@@ -296,7 +350,7 @@ localparam MEMBR_SIZE = 5;
localparam MEMBR_LOADDR = 6; localparam MEMBR_LOADDR = 6;
localparam MEMBR_CTRL = 7; localparam MEMBR_CTRL = 7;
reg [32:0] membr_data; reg [31:0] membr_data;
reg [15:0] membr_addr; reg [15:0] membr_addr;
reg membr_start; reg membr_start;
reg membr_done; reg membr_done;
...@@ -374,7 +428,7 @@ always @ (posedge clk) ...@@ -374,7 +428,7 @@ always @ (posedge clk)
end end
MEMBR_LOADDR: MEMBR_LOADDR:
begin begin
membr_data <= cmd_addr_r; membr_data <= {7'h0, cmd_addr_r[31:7]};
membr_addr <= 16'h202; membr_addr <= 16'h202;
membr_start <= membr_inprocess ? 1'b0 : 1'b1; membr_start <= membr_inprocess ? 1'b0 : 1'b1;
membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1; membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1;
......
dma/dma_control.v
View file @ 256f87fb
...@@ -96,7 +96,7 @@ always @ (posedge sclk) ...@@ -96,7 +96,7 @@ always @ (posedge sclk)
// drive iface signals // drive iface signals
assign host_new_cmd = host_issued_set; assign host_new_cmd = host_issued_set;
assign host_cmd_type = dma_type; assign host_cmd_type = {1'b0, dma_type};
assign host_sector_count = sector_cnt; assign host_sector_count = sector_cnt;
assign host_sector_addr = lba; assign host_sector_addr = lba;
...@@ -134,6 +134,7 @@ begin ...@@ -134,6 +134,7 @@ begin
state_wait_done <= (state_wait_done | set_wait_done) & ~clr_wait_done & ~rst; state_wait_done <= (state_wait_done | set_wait_done) & ~clr_wait_done & ~rst;
end end
assign adp_val_sclk = set_wait_busy;
// conrol signals resync // conrol signals resync
reg adp_val_r; reg adp_val_r;
reg adp_val_rr; reg adp_val_rr;
...@@ -143,7 +144,7 @@ begin ...@@ -143,7 +144,7 @@ begin
adp_val_rr <= adp_val_r; adp_val_rr <= adp_val_r;
end end
assign adp_addr = current_addr; assign adp_addr = current_addr[31:7];
assign adp_type = current_type; assign adp_type = current_type;
assign adp_val = adp_val_rr; assign adp_val = adp_val_rr;
...@@ -208,9 +209,9 @@ assign last_data = (sector_cnt == quarter_sector_cnt[33:2] + 1'b1) & (&quarter_ ...@@ -208,9 +209,9 @@ assign last_data = (sector_cnt == quarter_sector_cnt[33:2] + 1'b1) & (&quarter_
// calculate outgoing address // calculate outgoing address
// increment every transaction to adapter // increment every transaction to adapter
always @ (posedge sclk) always @ (posedge sclk)
current_addr <= ~set_wait_busy ? current_addr : current_addr <= ~set_wait_busy ? current_addr[31:7] :
state_idle ? mem_address : // new dma request state_idle ? mem_address[31:7] : // new dma request
current_addr + 1'b1; // same dma request, next 128 bytes current_addr[31:7] + 1'b1; // same dma request, next 128 bytes
always @ (posedge sclk) always @ (posedge sclk)
current_type <= ~set_wait_busy ? current_type : current_type <= ~set_wait_busy ? current_type :
...@@ -262,13 +263,13 @@ end ...@@ -262,13 +263,13 @@ end
// write address -> sclk (rd) domain to compare // write address -> sclk (rd) domain to compare
always @ (posedge sclk) always @ (posedge sclk)
begin begin
from_wr_addr_gr_r <= rst ? 9'h0 : from_wr_addr; from_wr_addr_gr_r <= rst ? 9'h0 : from_wr_addr_gr;
from_wr_addr_gr_rr <= rst ? 9'h0 : from_wr_addr_gr_r; from_wr_addr_gr_rr <= rst ? 9'h0 : from_wr_addr_gr_r;
end end
// read address -> hclk (wr) domain to compare // read address -> hclk (wr) domain to compare
always @ (posedge hclk) always @ (posedge hclk)
begin begin
from_rd_addr_gr_r <= rst ? 10'h0 : from_rd_addr; from_rd_addr_gr_r <= rst ? 10'h0 : from_rd_addr_gr;
from_rd_addr_gr_rr <= rst ? 10'h0 : from_rd_addr_gr_r; from_rd_addr_gr_rr <= rst ? 10'h0 : from_rd_addr_gr_r;
end end
// translate resynced write address into ordinary (non-gray) address // translate resynced write address into ordinary (non-gray) address
...@@ -367,13 +368,13 @@ end ...@@ -367,13 +368,13 @@ end
// write address -> hclk (rd) domain to compare // write address -> hclk (rd) domain to compare
always @ (posedge hclk) always @ (posedge hclk)
begin begin
to_wr_addr_gr_r <= rst ? 10'h0 : to_wr_addr; to_wr_addr_gr_r <= rst ? 10'h0 : to_wr_addr_gr;
to_wr_addr_gr_rr <= rst ? 10'h0 : to_wr_addr_gr_r; to_wr_addr_gr_rr <= rst ? 10'h0 : to_wr_addr_gr_r;
end end
// read address -> sclk (wr) domain to compare // read address -> sclk (wr) domain to compare
always @ (posedge sclk) always @ (posedge sclk)
begin begin
to_rd_addr_gr_r <= rst ? 9'h0 : to_rd_addr; to_rd_addr_gr_r <= rst ? 9'h0 : to_rd_addr_gr;
to_rd_addr_gr_rr <= rst ? 9'h0 : to_rd_addr_gr_r; to_rd_addr_gr_rr <= rst ? 9'h0 : to_rd_addr_gr_r;
end end
// translate resynced write address into ordinary (non-gray) address // translate resynced write address into ordinary (non-gray) address
...@@ -400,8 +401,8 @@ endgenerate ...@@ -400,8 +401,8 @@ endgenerate
// to_wr_addr_r - write address some hclk ticks ago // to_wr_addr_r - write address some hclk ticks ago
// => we can say if the fifo have the possibility to be empty // => we can say if the fifo have the possibility to be empty
// since actual to_wr_addr could only be incremented // since actual to_wr_addr could only be incremented
assign to_full = {to_wr_addr, 1'b0} == to_rd_addr_r + 1'b1; assign to_full = to_wr_addr == {to_rd_addr_r, 1'b0} + 1'b1;
assign to_empty = {to_wr_addr_r, 1'b0} == to_rd_addr; // overflows must never be achieved assign to_empty = to_wr_addr_r == {to_rd_addr, 1'b0}; // overflows must never be achieved
// calculate bus responses in order to fifo status: // calculate bus responses in order to fifo status:
assign to_val = ~to_empty; assign to_val = ~to_empty;
assign in_val = ~in_busy & ~to_full; assign in_val = ~in_busy & ~to_full;
......
dma/dma_regs.v
View file @ 256f87fb
...@@ -18,10 +18,7 @@ ...@@ -18,10 +18,7 @@
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> . * along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/ *******************************************************************************/
module dma_regs #( module dma_regs(
parameter REGISTERS_CNT = 20
)
(
input wire rst, input wire rst,
input wire ACLK, input wire ACLK,
input wire sclk, input wire sclk,
...@@ -190,27 +187,27 @@ assign sh_autoact_val = bram_wen & (bram_waddr[7:0] == 8'hc); ...@@ -190,27 +187,27 @@ assign sh_autoact_val = bram_wen & (bram_waddr[7:0] == 8'hc);
assign sh_inter_val = bram_wen & (bram_waddr[7:0] == 8'hd); assign sh_inter_val = bram_wen & (bram_waddr[7:0] == 8'hd);
assign sh_dir_val = bram_wen & (bram_waddr[7:0] == 8'he); assign sh_dir_val = bram_wen & (bram_waddr[7:0] == 8'he);
assign cmd_val_out = bram_wen & (bram_waddr[7:0] == 8'hf); assign cmd_val_out = bram_wen & (bram_waddr[7:0] == 8'hf);
assign sh_port = bram_wen & (bram_waddr[7:0] == 8'h13); assign sh_port_val = bram_wen & (bram_waddr[7:0] == 8'h13);
assign sh_dma_cnt_val = bram_wen & (bram_waddr[7:0] == 8'h14); assign sh_dma_cnt_val = bram_wen & (bram_waddr[7:0] == 8'h14);
assign sh_notif_val = bram_wen & (bram_waddr[7:0] == 8'h15); assign sh_notif_val = bram_wen & (bram_waddr[7:0] == 8'h15);
assign sh_data = wdata; assign sh_data = wdata;
assign sh_feature = wdata; assign sh_feature = wdata[15:0];
assign sh_lba_lo = wdata; assign sh_lba_lo = wdata[23:0];
assign sh_lba_hi = wdata; assign sh_lba_hi = wdata[23:0];
assign sh_count = wdata; assign sh_count = wdata[15:0];
assign sh_command = wdata; assign sh_command = wdata[7:0];
assign sh_dev = wdata; assign sh_dev = wdata[7:0];
assign sh_control = wdata; assign sh_control = wdata[7:0];
assign sh_dma_id_lo = wdata; assign sh_dma_id_lo = wdata;
assign sh_dma_id_hi = wdata; assign sh_dma_id_hi = wdata;
assign sh_buf_off = wdata; assign sh_buf_off = wdata;
assign sh_tran_cnt = wdata; assign sh_tran_cnt = wdata[15:0];
assign sh_autoact = wdata; assign sh_autoact = wdata[0];
assign sh_inter = wdata; assign sh_inter = wdata[0];
assign sh_dir = wdata; assign sh_dir = wdata[0];
assign sh_port = wdata; assign sh_port = wdata[3:0];
assign sh_notif = wdata; assign sh_notif = wdata[0];
assign sh_dma_cnt = wdata; assign sh_dma_cnt = wdata;
assign cmd_out = wdata; assign cmd_out = wdata;
...@@ -231,27 +228,27 @@ always @ (posedge ACLK) begin ...@@ -231,27 +228,27 @@ always @ (posedge ACLK) begin
bram_raddr_r == 8'hf4 ? reg10 : bram_raddr_r == 8'hf4 ? reg10 :
bram_raddr_r == 8'hf5 ? reg14 : bram_raddr_r == 8'hf5 ? reg14 :
bram_raddr_r == 8'h00 ? sh_data_in : bram_raddr_r == 8'h00 ? sh_data_in :
bram_raddr_r == 8'h01 ? sh_feature_in : bram_raddr_r == 8'h01 ? {16'h0, sh_feature_in} :
bram_raddr_r == 8'h02 ? sh_lba_in[23:0] : bram_raddr_r == 8'h02 ? {8'h0, sh_lba_in[23:0]} :
bram_raddr_r == 8'h03 ? sh_lba_in[47:24] : bram_raddr_r == 8'h03 ? {8'h0, sh_lba_in[47:24]} :
bram_raddr_r == 8'h04 ? sh_count_in : bram_raddr_r == 8'h04 ? {16'h0, sh_count_in} :
bram_raddr_r == 8'h05 ? sh_command_in : bram_raddr_r == 8'h05 ? {24'h0, sh_command_in} :
bram_raddr_r == 8'h06 ? sh_dev_in : bram_raddr_r == 8'h06 ? {24'h0, sh_dev_in} :
bram_raddr_r == 8'h07 ? sh_control_in : bram_raddr_r == 8'h07 ? {24'h0, sh_control_in} :
bram_raddr_r == 8'h08 ? sh_dma_id_in[31:0] : bram_raddr_r == 8'h08 ? sh_dma_id_in[31:0] :
bram_raddr_r == 8'h09 ? sh_dma_id_in[63:32] : bram_raddr_r == 8'h09 ? sh_dma_id_in[63:32] :
bram_raddr_r == 8'h0a ? sh_dma_off_in : bram_raddr_r == 8'h0a ? sh_dma_off_in :
bram_raddr_r == 8'h0b ? sh_tran_cnt_in : // Transfer Count bram_raddr_r == 8'h0b ? {16'h0, sh_tran_cnt_in} : // Transfer Count
bram_raddr_r == 8'h0c ? sh_autoact_in : bram_raddr_r == 8'h0c ? {31'h0, sh_autoact_in} :
bram_raddr_r == 8'h0d ? sh_inter_in : bram_raddr_r == 8'h0d ? {31'h0, sh_inter_in} :
bram_raddr_r == 8'h0e ? sh_dir_in : bram_raddr_r == 8'h0e ? {31'h0, sh_dir_in} :
bram_raddr_r == 8'h0f ? cmd_in : bram_raddr_r == 8'h0f ? cmd_in :
bram_raddr_r == 8'h10 ? sh_err_in : bram_raddr_r == 8'h10 ? {24'h0, sh_err_in} :
bram_raddr_r == 8'h11 ? sh_status_in : bram_raddr_r == 8'h11 ? {24'h0, sh_status_in} :
bram_raddr_r == 8'h12 ? sh_estatus_in : // E_Status bram_raddr_r == 8'h12 ? {24'h0, sh_estatus_in} : // E_Status
bram_raddr_r == 8'h13 ? sh_port_in : bram_raddr_r == 8'h13 ? {28'h0, sh_port_in} :
bram_raddr_r == 8'h14 ? sh_dma_cnt_in : bram_raddr_r == 8'h14 ? sh_dma_cnt_in :
bram_raddr_r == 8'h15 ? sh_notif_in : bram_raddr_r == 8'h15 ? {31'h0, sh_notif_in} :
32'hd34db33f; 32'hd34db33f;
end end
assign bram_rdata = bram_rdata_r; assign bram_rdata = bram_rdata_r;
......
dma/sata_top.v
View file @ 256f87fb
...@@ -42,13 +42,9 @@ ...@@ -42,13 +42,9 @@
input wire ARVALID, // AXI PS Master GP1 ARVALID, output input wire ARVALID, // AXI PS Master GP1 ARVALID, output
output wire ARREADY, // AXI PS Master GP1 ARREADY, input output wire ARREADY, // AXI PS Master GP1 ARREADY, input
input wire [11:0] ARID, // AXI PS Master GP1 ARID[11:0], output input wire [11:0] ARID, // AXI PS Master GP1 ARID[11:0], output
input wire [1:0] ARLOCK, // AXI PS Master GP1 ARLOCK[1:0], output
input wire [3:0] ARCACHE, // AXI PS Master GP1 ARCACHE[3:0], output
input wire [2:0] ARPROT, // AXI PS Master GP1 ARPROT[2:0], output
input wire [3:0] ARLEN, // AXI PS Master GP1 ARLEN[3:0], output input wire [3:0] ARLEN, // AXI PS Master GP1 ARLEN[3:0], output
input wire [1:0] ARSIZE, // AXI PS Master GP1 ARSIZE[1:0], output input wire [1:0] ARSIZE, // AXI PS Master GP1 ARSIZE[1:0], output
input wire [1:0] ARBURST, // AXI PS Master GP1 ARBURST[1:0], output input wire [1:0] ARBURST, // AXI PS Master GP1 ARBURST[1:0], output
input wire [3:0] ARQOS, // AXI PS Master GP1 ARQOS[3:0], output
// AXI PS Master GP1: Read Data // AXI PS Master GP1: Read Data
output wire [31:0] RDATA, // AXI PS Master GP1 RDATA[31:0], input output wire [31:0] RDATA, // AXI PS Master GP1 RDATA[31:0], input
output wire RVALID, // AXI PS Master GP1 RVALID, input output wire RVALID, // AXI PS Master GP1 RVALID, input
...@@ -61,13 +57,9 @@ ...@@ -61,13 +57,9 @@
input wire AWVALID, // AXI PS Master GP1 AWVALID, output input wire AWVALID, // AXI PS Master GP1 AWVALID, output
output wire AWREADY, // AXI PS Master GP1 AWREADY, input output wire AWREADY, // AXI PS Master GP1 AWREADY, input
input wire [11:0] AWID, // AXI PS Master GP1 AWID[11:0], output input wire [11:0] AWID, // AXI PS Master GP1 AWID[11:0], output
input wire [1:0] AWLOCK, // AXI PS Master GP1 AWLOCK[1:0], output
input wire [3:0] AWCACHE, // AXI PS Master GP1 AWCACHE[3:0], output
input wire [2:0] AWPROT, // AXI PS Master GP1 AWPROT[2:0], output
input wire [3:0] AWLEN, // AXI PS Master GP1 AWLEN[3:0], outpu:t input wire [3:0] AWLEN, // AXI PS Master GP1 AWLEN[3:0], outpu:t
input wire [1:0] AWSIZE, // AXI PS Master GP1 AWSIZE[1:0], output input wire [1:0] AWSIZE, // AXI PS Master GP1 AWSIZE[1:0], output
input wire [1:0] AWBURST, // AXI PS Master GP1 AWBURST[1:0], output input wire [1:0] AWBURST, // AXI PS Master GP1 AWBURST[1:0], output
input wire [3:0] AWQOS, // AXI PS Master GP1 AWQOS[3:0], output
// AXI PS Master GP1: Write Data // AXI PS Master GP1: Write Data
input wire [31:0] WDATA, // AXI PS Master GP1 WDATA[31:0], output input wire [31:0] WDATA, // AXI PS Master GP1 WDATA[31:0], output
input wire WVALID, // AXI PS Master GP1 WVALID, output input wire WVALID, // AXI PS Master GP1 WVALID, output
...@@ -141,8 +133,8 @@ ...@@ -141,8 +133,8 @@
*/ */
output wire TXN, output wire TXN,
output wire TXP, output wire TXP,
output wire RXN, input wire RXN,
output wire RXP, input wire RXP,
input wire EXTCLK_P, input wire EXTCLK_P,
input wire EXTCLK_N input wire EXTCLK_N
...@@ -288,6 +280,9 @@ wire rdata_done; // = membridge.is_last_in_page & membridge.afi_rread ...@@ -288,6 +280,9 @@ wire rdata_done; // = membridge.is_last_in_page & membridge.afi_rread
//assign rst = ARESETN; //assign rst = ARESETN;
// TODO
assign hclk = ACLK;
axi_regs axi_regs( axi_regs axi_regs(
// axi iface // axi iface
...@@ -297,13 +292,9 @@ axi_regs axi_regs( ...@@ -297,13 +292,9 @@ axi_regs axi_regs(
.ARVALID (ARVALID), .ARVALID (ARVALID),
.ARREADY (ARREADY), .ARREADY (ARREADY),
.ARID (ARID), .ARID (ARID),
.ARLOCK (ARLOCK),
.ARCACHE (ARCACHE),
.ARPROT (ARPROT),
.ARLEN (ARLEN), .ARLEN (ARLEN),
.ARSIZE (ARSIZE), .ARSIZE (ARSIZE),
.ARBURST (ARBURST), .ARBURST (ARBURST),
.ARQOS (ARQOS),
.RDATA (RDATA), .RDATA (RDATA),
.RVALID (RVALID), .RVALID (RVALID),
.RREADY (RREADY), .RREADY (RREADY),
...@@ -314,13 +305,9 @@ axi_regs axi_regs( ...@@ -314,13 +305,9 @@ axi_regs axi_regs(
.AWVALID (AWVALID), .AWVALID (AWVALID),
.AWREADY (AWREADY), .AWREADY (AWREADY),
.AWID (AWID), .AWID (AWID),
.AWLOCK (AWLOCK),
.AWCACHE (AWCACHE),
.AWPROT (AWPROT),
.AWLEN (AWLEN), .AWLEN (AWLEN),
.AWSIZE (AWSIZE), .AWSIZE (AWSIZE),
.AWBURST (AWBURST), .AWBURST (AWBURST),
.AWQOS (AWQOS),
.WDATA (WDATA), .WDATA (WDATA),
.WVALID (WVALID), .WVALID (WVALID),
.WREADY (WREADY), .WREADY (WREADY),
...@@ -350,7 +337,7 @@ dma_regs dma_regs( ...@@ -350,7 +337,7 @@ dma_regs dma_regs(
.ACLK (ACLK), .ACLK (ACLK),
.sclk (sclk), .sclk (sclk),
// control iface // control iface
.mem_address (mem_address), .mem_address (mem_address[31:7]),
.lba (lba), .lba (lba),
.sector_cnt (sector_cnt), .sector_cnt (sector_cnt),
.dma_type (dma_type), .dma_type (dma_type),
...@@ -441,7 +428,7 @@ dma_control dma_control( ...@@ -441,7 +428,7 @@ dma_control dma_control(
.rst (sata_rst), .rst (sata_rst),
// registers iface // registers iface
.mem_address (mem_address), .mem_address (mem_address[31:7]),
.lba (lba), .lba (lba),
.sector_cnt (sector_cnt), .sector_cnt (sector_cnt),
.dma_type (dma_type), .dma_type (dma_type),
...@@ -450,7 +437,7 @@ dma_control dma_control( ...@@ -450,7 +437,7 @@ dma_control dma_control(
// adapter command iface // adapter command iface
.adp_busy (adp_busy), .adp_busy (adp_busy),
.adp_addr (adp_addr), .adp_addr (adp_addr[31:7]),
.adp_type (adp_type), .adp_type (adp_type),
.adp_val (adp_val), .adp_val (adp_val),
...@@ -490,7 +477,7 @@ dma_adapter dma_adapter( ...@@ -490,7 +477,7 @@ dma_adapter dma_adapter(
// command iface // command iface
.cmd_type (adp_type), .cmd_type (adp_type),
.cmd_val (adp_val), .cmd_val (adp_val),
.cmd_addr (adp_addr), .cmd_addr (adp_addr[31:7]),
.cmd_busy (adp_busy), .cmd_busy (adp_busy),
// data iface // data iface
.wr_data_in (to_data), .wr_data_in (to_data),
......
dma/top.v
View file @ 256f87fb
...@@ -38,10 +38,8 @@ module top #( ...@@ -38,10 +38,8 @@ module top #(
input wire EXTCLK_P, input wire EXTCLK_P,
input wire EXTCLK_N input wire EXTCLK_N
); );
parameter REGISTERS_CNT = 20;
wire [32*REGISTERS_CNT - 1:0] outmem;
wire clrstart;
wire axi_aclk0;
wire sclk; wire sclk;
wire sata_rst; wire sata_rst;
wire extrst; wire extrst;
...@@ -55,13 +53,9 @@ wire [31:0] ARADDR; ...@@ -55,13 +53,9 @@ wire [31:0] ARADDR;
wire ARVALID; wire ARVALID;
wire ARREADY; wire ARREADY;
wire [11:0] ARID; wire [11:0] ARID;
wire [1:0] ARLOCK;
wire [3:0] ARCACHE;
wire [2:0] ARPROT;
wire [3:0] ARLEN; wire [3:0] ARLEN;
wire [1:0] ARSIZE; wire [1:0] ARSIZE;
wire [1:0] ARBURST; wire [1:0] ARBURST;
wire [3:0] ARQOS;
wire [31:0] RDATA; wire [31:0] RDATA;
wire RVALID; wire RVALID;
wire RREADY; wire RREADY;
...@@ -72,13 +66,9 @@ wire [31:0] AWADDR; ...@@ -72,13 +66,9 @@ wire [31:0] AWADDR;
wire AWVALID; wire AWVALID;
wire AWREADY; wire AWREADY;
wire [11:0] AWID; wire [11:0] AWID;
wire [1:0] AWLOCK;
wire [3:0] AWCACHE;
wire [2:0] AWPROT;
wire [3:0] AWLEN; wire [3:0] AWLEN;
wire [1:0] AWSIZE; wire [1:0] AWSIZE;
wire [1:0] AWBURST; wire [1:0] AWBURST;
wire [3:0] AWQOS;
wire [31:0] WDATA; wire [31:0] WDATA;
wire WVALID; wire WVALID;
wire WREADY; wire WREADY;
...@@ -137,35 +127,14 @@ wire [ 7:0] afi0_rcount; // input[7:0] ...@@ -137,35 +127,14 @@ wire [ 7:0] afi0_rcount; // input[7:0]
wire [ 2:0] afi0_racount; // input[2:0] wire [ 2:0] afi0_racount; // input[2:0]
wire afi0_rdissuecap1en; // output wire afi0_rdissuecap1en; // output
// send_dma
wire [7:0] cmd_ad;
wire cmd_stb;
wire [7:0] status_ad;
wire status_rq;
wire status_start;
wire frame_start_chn;
wire next_page_chn;
wire cmd_wrmem;
wire page_ready_chn;
wire frame_done_chn;
wire [15:0] line_unfinished_chn1;
wire suspend_chn1;
wire xfer_reset_page_rd;
wire buf_wpage_nxt;
wire buf_wr;
wire [63:0] buf_wdata;
wire xfer_reset_page_wr;
wire buf_rpage_nxt;
wire buf_rd;
wire [63:0] buf_rdata;
assign comb_rst=~frst[0] | frst[1]; assign comb_rst=~frst[0] | frst[1];
always @(posedge comb_rst or posedge axi_aclk0) begin always @(posedge comb_rst or posedge axi_aclk0) begin
if (comb_rst) axi_rst_pre <= 1'b1; if (comb_rst) axi_rst_pre <= 1'b1;
else axi_rst_pre <= 1'b0; else axi_rst_pre <= 1'b0;
end end
BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(/*fclk[0]*/ sclk)); //BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(/*fclk[0]*/ sclk));
assign axi_aclk = sclk;
BUFG bufg_axi_aclk0_i (.O(axi_aclk0),.I(fclk[0])); BUFG bufg_axi_aclk0_i (.O(axi_aclk0),.I(fclk[0]));
BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre)); BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
BUFG bufg_extrst_i (.O(extrst),.I(axi_rst_pre)); BUFG bufg_extrst_i (.O(extrst),.I(axi_rst_pre));
...@@ -191,13 +160,9 @@ sata_top sata_top( ...@@ -191,13 +160,9 @@ sata_top sata_top(
.ARVALID (ARVALID), .ARVALID (ARVALID),
.ARREADY (ARREADY), .ARREADY (ARREADY),
.ARID (ARID), .ARID (ARID),
.ARLOCK (ARLOCK),
.ARCACHE (ARCACHE),
.ARPROT (ARPROT),
.ARLEN (ARLEN), .ARLEN (ARLEN),
.ARSIZE (ARSIZE), .ARSIZE (ARSIZE),
.ARBURST (ARBURST), .ARBURST (ARBURST),
.ARQOS (ARQOS),
// AXI PS Master GP1: Read Data // AXI PS Master GP1: Read Data
.RDATA (RDATA), .RDATA (RDATA),
.RVALID (RVALID), .RVALID (RVALID),
...@@ -210,13 +175,9 @@ sata_top sata_top( ...@@ -210,13 +175,9 @@ sata_top sata_top(
.AWVALID (AWVALID), .AWVALID (AWVALID),
.AWREADY (AWREADY), .AWREADY (AWREADY),
.AWID (AWID), .AWID (AWID),
.AWLOCK (AWLOCK),
.AWCACHE (AWCACHE),
.AWPROT (AWPROT),
.AWLEN (AWLEN), .AWLEN (AWLEN),
.AWSIZE (AWSIZE), .AWSIZE (AWSIZE),
.AWBURST (AWBURST), .AWBURST (AWBURST),
.AWQOS (AWQOS),
// AXI PS Master GP1: Write Data // AXI PS Master GP1: Write Data
.WDATA (WDATA), .WDATA (WDATA),
.WVALID (WVALID), .WVALID (WVALID),
...@@ -615,13 +576,13 @@ PS7 ps7_i ( ...@@ -615,13 +576,13 @@ PS7 ps7_i (
.MAXIGP1ARVALID (ARVALID), // AXI PS Master GP1 ARVALID, output .MAXIGP1ARVALID (ARVALID), // AXI PS Master GP1 ARVALID, output
.MAXIGP1ARREADY (ARREADY), // AXI PS Master GP1 ARREADY, input .MAXIGP1ARREADY (ARREADY), // AXI PS Master GP1 ARREADY, input
.MAXIGP1ARID (ARID), // AXI PS Master GP1 ARID[11:0], output .MAXIGP1ARID (ARID), // AXI PS Master GP1 ARID[11:0], output
.MAXIGP1ARLOCK (ARLOCK), // AXI PS Master GP1 ARLOCK[1:0], output .MAXIGP1ARLOCK (), // AXI PS Master GP1 ARLOCK[1:0], output
.MAXIGP1ARCACHE (ARCACHE), // AXI PS Master GP1 ARCACHE[3:0], output .MAXIGP1ARCACHE (), // AXI PS Master GP1 ARCACHE[3:0], output
.MAXIGP1ARPROT (ARPROT), // AXI PS Master GP1 ARPROT[2:0], output .MAXIGP1ARPROT (), // AXI PS Master GP1 ARPROT[2:0], output
.MAXIGP1ARLEN (ARLEN), // AXI PS Master GP1 ARLEN[3:0], output .MAXIGP1ARLEN (ARLEN), // AXI PS Master GP1 ARLEN[3:0], output
.MAXIGP1ARSIZE (ARSIZE), // AXI PS Master GP1 ARSIZE[1:0], output .MAXIGP1ARSIZE (ARSIZE), // AXI PS Master GP1 ARSIZE[1:0], output
.MAXIGP1ARBURST (ARBURST), // AXI PS Master GP1 ARBURST[1:0], output .MAXIGP1ARBURST (ARBURST), // AXI PS Master GP1 ARBURST[1:0], output
.MAXIGP1ARQOS (ARQOS), // AXI PS Master GP1 ARQOS[3:0], output .MAXIGP1ARQOS (), // AXI PS Master GP1 ARQOS[3:0], output
// AXI PS Master GP1: Read Data // AXI PS Master GP1: Read Data
.MAXIGP1RDATA (RDATA), // AXI PS Master GP1 RDATA[31:0], input .MAXIGP1RDATA (RDATA), // AXI PS Master GP1 RDATA[31:0], input
.MAXIGP1RVALID (RVALID), // AXI PS Master GP1 RVALID, input .MAXIGP1RVALID (RVALID), // AXI PS Master GP1 RVALID, input
...@@ -634,13 +595,13 @@ PS7 ps7_i ( ...@@ -634,13 +595,13 @@ PS7 ps7_i (
.MAXIGP1AWVALID (AWVALID), // AXI PS Master GP1 AWVALID, output .MAXIGP1AWVALID (AWVALID), // AXI PS Master GP1 AWVALID, output
.MAXIGP1AWREADY (AWREADY), // AXI PS Master GP1 AWREADY, input .MAXIGP1AWREADY (AWREADY), // AXI PS Master GP1 AWREADY, input
.MAXIGP1AWID (AWID), // AXI PS Master GP1 AWID[11:0], output .MAXIGP1AWID (AWID), // AXI PS Master GP1 AWID[11:0], output
.MAXIGP1AWLOCK (AWLOCK), // AXI PS Master GP1 AWLOCK[1:0], output .MAXIGP1AWLOCK (), // AXI PS Master GP1 AWLOCK[1:0], output
.MAXIGP1AWCACHE (AWCACHE), // AXI PS Master GP1 AWCACHE[3:0], output .MAXIGP1AWCACHE (), // AXI PS Master GP1 AWCACHE[3:0], output
.MAXIGP1AWPROT (AWPROT), // AXI PS Master GP1 AWPROT[2:0], output .MAXIGP1AWPROT (), // AXI PS Master GP1 AWPROT[2:0], output
.MAXIGP1AWLEN (AWLEN), // AXI PS Master GP1 AWLEN[3:0], output .MAXIGP1AWLEN (AWLEN), // AXI PS Master GP1 AWLEN[3:0], output
.MAXIGP1AWSIZE (AWSIZE), // AXI PS Master GP1 AWSIZE[1:0], output .MAXIGP1AWSIZE (AWSIZE), // AXI PS Master GP1 AWSIZE[1:0], output
.MAXIGP1AWBURST (AWBURST), // AXI PS Master GP1 AWBURST[1:0], output .MAXIGP1AWBURST (AWBURST), // AXI PS Master GP1 AWBURST[1:0], output
.MAXIGP1AWQOS (AWQOS), // AXI PS Master GP1 AWQOS[3:0], output .MAXIGP1AWQOS (), // AXI PS Master GP1 AWQOS[3:0], output
// AXI PS Master GP1: Write Data // AXI PS Master GP1: Write Data
.MAXIGP1WDATA (WDATA), // AXI PS Master GP1 WDATA[31:0], output .MAXIGP1WDATA (WDATA), // AXI PS Master GP1 WDATA[31:0], output
.MAXIGP1WVALID (WVALID), // AXI PS Master GP1 WVALID, output .MAXIGP1WVALID (WVALID), // AXI PS Master GP1 WVALID, output
......
gtxe2_gpl @ fedd4e5b
Subproject commit c4c7e57675cc07463b0c9c09937281652a60a6bf Subproject commit fedd4e5b128fca4cf4726c63709412cacc92bd1b
host/command.v
View file @ 256f87fb
...@@ -185,7 +185,7 @@ begin ...@@ -185,7 +185,7 @@ begin
sh_inter <= rst ? 1'h0 : al_sh_inter_val_in ? al_sh_inter_in : tl_sh_inter_val_in ? tl_sh_inter_in : sh_inter; sh_inter <= rst ? 1'h0 : al_sh_inter_val_in ? al_sh_inter_in : tl_sh_inter_val_in ? tl_sh_inter_in : sh_inter;
sh_dir <= rst ? 1'h0 : al_sh_dir_val_in ? al_sh_dir_in : tl_sh_dir_val_in ? tl_sh_dir_in : sh_dir; sh_dir <= rst ? 1'h0 : al_sh_dir_val_in ? al_sh_dir_in : tl_sh_dir_val_in ? tl_sh_dir_in : sh_dir;
sh_dma_id[31:0] <= rst ? 32'h0 : al_sh_dma_id_lo_val_in ? al_sh_dma_id_lo_in : tl_sh_dma_id_val_in ? tl_sh_dma_id_in[31:0] : sh_dma_id[31:0]; sh_dma_id[31:0] <= rst ? 32'h0 : al_sh_dma_id_lo_val_in ? al_sh_dma_id_lo_in : tl_sh_dma_id_val_in ? tl_sh_dma_id_in[31:0] : sh_dma_id[31:0];
sh_dma_id[63:32] <= rst ? 32'h0 : al_sh_dma_id_lo_val_in ? al_sh_dma_id_hi_in : tl_sh_dma_id_val_in ? tl_sh_dma_id_in[63:32] : sh_dma_id[63:32]; sh_dma_id[63:32] <= rst ? 32'h0 : al_sh_dma_id_hi_val_in ? al_sh_dma_id_hi_in : tl_sh_dma_id_val_in ? tl_sh_dma_id_in[63:32] : sh_dma_id[63:32];
sh_dma_off <= rst ? 32'h0 : al_sh_buf_off_val_in ? al_sh_buf_off_in : tl_sh_dma_off_val_in ? tl_sh_dma_off_in : sh_dma_off; sh_dma_off <= rst ? 32'h0 : al_sh_buf_off_val_in ? al_sh_buf_off_in : tl_sh_dma_off_val_in ? tl_sh_dma_off_in : sh_dma_off;
sh_dma_cnt <= rst ? 32'h0 : al_sh_dma_cnt_val_in ? al_sh_dma_cnt_in : tl_sh_dma_cnt_val_in ? tl_sh_dma_cnt_in : sh_dma_cnt; sh_dma_cnt <= rst ? 32'h0 : al_sh_dma_cnt_val_in ? al_sh_dma_cnt_in : tl_sh_dma_cnt_val_in ? tl_sh_dma_cnt_in : sh_dma_cnt;
sh_tran_cnt <= rst ? 16'h0 : al_sh_tran_cnt_val_in ? al_sh_tran_cnt_in : tl_sh_tran_cnt_val_in ? tl_sh_tran_cnt_in : sh_tran_cnt; sh_tran_cnt <= rst ? 16'h0 : al_sh_tran_cnt_val_in ? al_sh_tran_cnt_in : tl_sh_tran_cnt_val_in ? tl_sh_tran_cnt_in : sh_tran_cnt;
...@@ -243,9 +243,9 @@ assign tl_data_last_out = 1'b0; ...@@ -243,9 +243,9 @@ assign tl_data_last_out = 1'b0;
assign tl_data_val_out = 1'b0; assign tl_data_val_out = 1'b0;
always @ (posedge clk) always @ (posedge clk)
waddr <= rst ? 1'b0 : ~tl_data_val_in ? waddr : (raddr == waddr + 1'b1) ? waddr : waddr + 1'b1; waddr <= rst ? 10'b0 : ~tl_data_val_in ? waddr : (raddr == waddr + 1'b1) ? waddr : waddr + 1'b1;
always @ (posedge clk) always @ (posedge clk)
raddr <= rst ? 1'b0 : al_sh_data_strobe_in ? raddr + 1'b1 : raddr; raddr <= rst ? 10'b0 : al_sh_data_strobe_in ? raddr + 1'b1 : raddr;
ram_1kx32_1kx32 rbuf( ram_1kx32_1kx32 rbuf(
.rclk (clk), // clock for read port .rclk (clk), // clock for read port
......
host/gtx_10x8dec.v
View file @ 256f87fb
...@@ -80,6 +80,7 @@ begin ...@@ -80,6 +80,7 @@ begin
end end
// overall expected disparity when the table values would apper - disp0_r. // overall expected disparity when the table values would apper - disp0_r.
// disp1_rr shows expected after 0st byte would be considered // disp1_rr shows expected after 0st byte would be considered
reg correct_table_disp;
wire expected_disparity; wire expected_disparity;
wire expected_disparity_interm; wire expected_disparity_interm;
...@@ -99,7 +100,6 @@ always @ (posedge clk) ...@@ -99,7 +100,6 @@ always @ (posedge clk)
disparity <= rst ? 1'b0 : inv_disp1 ^ inv_disp0 ? ~disparity : disparity; disparity <= rst ? 1'b0 : inv_disp1 ^ inv_disp0 ? ~disparity : disparity;
// to correct disparity if once an error occured // to correct disparity if once an error occured
reg correct_table_disp;
always @ (posedge clk) always @ (posedge clk)
correct_table_disp <= rst ? 1'b0 : disperror[1] ? ~correct_table_disp : correct_table_disp; correct_table_disp <= rst ? 1'b0 : disperror[1] ? ~correct_table_disp : correct_table_disp;
......
host/gtx_comma_align.v
View file @ 256f87fb
...@@ -71,7 +71,7 @@ reg [19:0] indata_r; ...@@ -71,7 +71,7 @@ reg [19:0] indata_r;
wire [38:0] window; wire [38:0] window;
always @ (posedge clk) always @ (posedge clk)
indata_r <= indata; indata_r <= indata;
assign window = {indata, indata_r}; assign window = {indata[18:0], indata_r};
// there is only 1 matched subwindow due to 20-bit comma's non-repetative pattern // there is only 1 matched subwindow due to 20-bit comma's non-repetative pattern
wire [19:0] subwindow [19:0]; wire [19:0] subwindow [19:0];
......
host/gtx_elastic.v
View file @ 256f87fb
...@@ -139,8 +139,8 @@ endgenerate ...@@ -139,8 +139,8 @@ endgenerate
// wr_addr_r - write address some rclk ticks ago // wr_addr_r - write address some rclk ticks ago
// => we can say if the fifo have the possibility to be empty // => we can say if the fifo have the possibility to be empty
// since actual wr_addr could only be incremented // since actual wr_addr could only be incremented
assign full = {wr_addr, 1'b0} == rd_addr_r + 1'b1; assign full = wr_addr == rd_addr_r + 1'b1;
assign empty = {wr_addr_r, 1'b0} == rd_addr; assign empty = wr_addr_r == rd_addr;
assign outram = ram[rd_addr]; assign outram = ram[rd_addr];
...@@ -262,8 +262,6 @@ wire skip_write; ...@@ -262,8 +262,6 @@ wire skip_write;
wire rmv1_req_wclk; wire rmv1_req_wclk;
wire rmv2_req_wclk; wire rmv2_req_wclk;
reg next_prim_loaded; reg next_prim_loaded;
always @ (wclk)
next_prim_loaded <= state_wait_next_p;
wire state_bypass_rmv; wire state_bypass_rmv;
reg state_wait1_align; reg state_wait1_align;
...@@ -285,6 +283,9 @@ wire clr_skip2_align; ...@@ -285,6 +283,9 @@ wire clr_skip2_align;
wire clr_wait_next_p; wire clr_wait_next_p;
wire clr_send_ack; wire clr_send_ack;
always @ (wclk)
next_prim_loaded <= state_wait_next_p;
assign state_bypass_rmv = ~state_wait1_align & ~state_skip1_align & ~state_wait2_align & ~state_skip2_align & ~state_wait_next_p & ~state_send_ack; assign state_bypass_rmv = ~state_wait1_align & ~state_skip1_align & ~state_wait2_align & ~state_skip2_align & ~state_wait_next_p & ~state_send_ack;
assign set_wait1_align = state_bypass_rmv & rmv1_req_wclk & ~rmv2_req_wclk; assign set_wait1_align = state_bypass_rmv & rmv1_req_wclk & ~rmv2_req_wclk;
...@@ -372,13 +373,13 @@ assign align_2nd = outram[15:0] == 16'h7B4A ...@@ -372,13 +373,13 @@ assign align_2nd = outram[15:0] == 16'h7B4A
& outram[21:20] == 2'b00; & outram[21:20] == 2'b00;
// whole align primitive is the last thing we read from fifo // whole align primitive is the last thing we read from fifo
reg read_align; reg read_align;
wire pause_read;
always @ (posedge rclk) always @ (posedge rclk)
read_align <= rst ? 1'b0 : pause_read | align_1st & align_2nd; read_align <= rst ? 1'b0 : pause_read | align_1st & align_2nd;
// just to alternate alignp's words, = 0 => 1st word, = 1 => 2nd word // just to alternate alignp's words, = 0 => 1st word, = 1 => 2nd word
reg align_altern; reg align_altern;
wire pause_read;
// also pause when offset gets ok, but only 1st word of alignp is sent - need to send 2nd word // also pause when offset gets ok, but only 1st word of alignp is sent - need to send 2nd word
assign pause_read = read_align & offset_less & fifo_stable | align_altern; assign pause_read = read_align & offset_less & fifo_stable | align_altern;
......
host/gtx_wrap.v
View file @ 256f87fb
...@@ -30,8 +30,7 @@ module gtx_wrap #( ...@@ -30,8 +30,7 @@ module gtx_wrap #(
parameter RXCDRPHRESET_TIME = 5'h1, parameter RXCDRPHRESET_TIME = 5'h1,
parameter RXCDRFREQRESET_TIME = 5'h1, parameter RXCDRFREQRESET_TIME = 5'h1,
parameter RXDFELPMRESET_TIME = 7'hf, parameter RXDFELPMRESET_TIME = 7'hf,
parameter RXISCANRESET_TIME = 5'h1, parameter RXISCANRESET_TIME = 5'h1
parameter RXEYERESET_TIME = 7'h25
) )
( (
output wire cplllock, output wire cplllock,
...@@ -74,7 +73,11 @@ module gtx_wrap #( ...@@ -74,7 +73,11 @@ module gtx_wrap #(
output wire [DATA_BYTE_WIDTH - 1:0] rxdisperr output wire [DATA_BYTE_WIDTH - 1:0] rxdisperr
); );
// resets while PCS resets wire rxresetdone_gtx;
wire txresetdone_gtx;
wire wrap_rxreset_;
wire wrap_txreset_;
// resets while PCS resets, active low
assign wrap_rxreset_ = rxuserrdy & rxresetdone_gtx; assign wrap_rxreset_ = rxuserrdy & rxresetdone_gtx;
assign wrap_txreset_ = txuserrdy & txresetdone_gtx; assign wrap_txreset_ = txuserrdy & txresetdone_gtx;
...@@ -149,6 +152,8 @@ if (DATA_BYTE_WIDTH == 4) begin ...@@ -149,6 +152,8 @@ if (DATA_BYTE_WIDTH == 4) begin
) )
txdata_resynchro( txdata_resynchro(
.rst (txreset), .rst (txreset),
.rrst (txreset),
.wrst (txreset),
.rclk (txusrclk), .rclk (txusrclk),
.wclk (txusrclk2), .wclk (txusrclk2),
.we (1'b1), .we (1'b1),
...@@ -166,8 +171,8 @@ end ...@@ -166,8 +171,8 @@ end
else else
if (DATA_BYTE_WIDTH == 2) begin if (DATA_BYTE_WIDTH == 2) begin
// no resync is needed => straightforward assignments // no resync is needed => straightforward assignments
assign txdata_enc_in = txdata; assign txdata_enc_in = txdata[15:0];
assign txcharisk_enc_in = txcharisk; assign txcharisk_enc_in = txcharisk[1:0];
assign txcominit_gtx = txcominit; assign txcominit_gtx = txcominit;
assign txcomwake_gtx = txcomwake; assign txcomwake_gtx = txcomwake;
assign txelecidle_gtx = txelecidle; assign txelecidle_gtx = txelecidle;
...@@ -261,6 +266,8 @@ wire [1:0] rxnotintable_els_out; ...@@ -261,6 +266,8 @@ wire [1:0] rxnotintable_els_out;
wire [1:0] rxdisperr_els_out; wire [1:0] rxdisperr_els_out;
wire lword_strobe; wire lword_strobe;
wire isaligned; wire isaligned;
wire elastic_full;
wire elastic_empty;
gtx_elastic #( gtx_elastic #(
.DEPTH_LOG2 (3), .DEPTH_LOG2 (3),
...@@ -302,8 +309,6 @@ gtx_elastic( ...@@ -302,8 +309,6 @@ gtx_elastic(
*/ */
wire rxcomwakedet_gtx; wire rxcomwakedet_gtx;
wire rxcominitdet_gtx; wire rxcominitdet_gtx;
wire rxresetdone_gtx;
wire txresetdone_gtx;
// insert resync if it's necessary // insert resync if it's necessary
...@@ -335,7 +340,7 @@ if (DATA_BYTE_WIDTH == 4) begin ...@@ -335,7 +340,7 @@ if (DATA_BYTE_WIDTH == 4) begin
rxdata_els_out, // 16 rxdata_els_out, // 16
rxdata_resync_buf[21:0]}; // 22 / 51 total rxdata_resync_buf[21:0]}; // 22 / 51 total
always @ (posedge rxusrclk) always @ (posedge rxusrclk)
rxdata_resync_buf <= ~wrap_rxreset_ ? 36'h0 : ~rxdata_resync_strobe ? {elastic_full, elastic_empty, rxdisperr_els_out, rxnotintable_els_out, rxcharisk_els_out, rxdata_els_out} : rxdata_resync_buf; rxdata_resync_buf <= ~wrap_rxreset_ ? 24'h0 : ~rxdata_resync_strobe ? {elastic_full, elastic_empty, rxdisperr_els_out, rxnotintable_els_out, rxcharisk_els_out, rxdata_els_out} : rxdata_resync_buf;
always @ (posedge rxusrclk2) always @ (posedge rxusrclk2)
rxdata_resync_nempty_r <= rxdata_resync_nempty; rxdata_resync_nempty_r <= rxdata_resync_nempty;
...@@ -346,6 +351,8 @@ if (DATA_BYTE_WIDTH == 4) begin ...@@ -346,6 +351,8 @@ if (DATA_BYTE_WIDTH == 4) begin
) )
rxdata_resynchro( rxdata_resynchro(
.rst (~wrap_rxreset_), .rst (~wrap_rxreset_),
.rrst (~wrap_rxreset_),
.wrst (~wrap_rxreset_),
.rclk (rxusrclk2), .rclk (rxusrclk2),
.wclk (rxusrclk), .wclk (rxusrclk),
.we (rxdata_resync_strobe), .we (rxdata_resync_strobe),
...@@ -362,10 +369,10 @@ if (DATA_BYTE_WIDTH == 4) begin ...@@ -362,10 +369,10 @@ if (DATA_BYTE_WIDTH == 4) begin
assign txresetdone = rxdata_resync_out[46]; assign txresetdone = rxdata_resync_out[46];
assign rxelsfull = rxdata_resync_out[45]; assign rxelsfull = rxdata_resync_out[45];
assign rxelsempty = rxdata_resync_out[44]; assign rxelsempty = rxdata_resync_out[44];
assign rxdisperr = {rxdata_resync_out[43:42], rxdata_resync_out[20:20]}; assign rxdisperr[3:0] = {rxdata_resync_out[43:42], rxdata_resync_out[21:20]};
assign rxnotintable = {rxdata_resync_out[41:40], rxdata_resync_out[19:18]}; assign rxnotintable[3:0] = {rxdata_resync_out[41:40], rxdata_resync_out[19:18]};
assign rxcharisk = {rxdata_resync_out[39:38], rxdata_resync_out[17:16]}; assign rxcharisk[3:0] = {rxdata_resync_out[39:38], rxdata_resync_out[17:16]};
assign rxdata = {rxdata_resync_out[37:22], rxdata_resync_out[15:0] }; assign rxdata[31:0] = {rxdata_resync_out[37:22], rxdata_resync_out[15:0] };
end end
else else
if (DATA_BYTE_WIDTH == 2) begin if (DATA_BYTE_WIDTH == 2) begin
...@@ -377,10 +384,10 @@ if (DATA_BYTE_WIDTH == 2) begin ...@@ -377,10 +384,10 @@ if (DATA_BYTE_WIDTH == 2) begin
assign txresetdone = txresetdone_gtx; assign txresetdone = txresetdone_gtx;
assign rxelsfull = elastic_full; assign rxelsfull = elastic_full;
assign rxelsempty = elastic_empty; assign rxelsempty = elastic_empty;
assign rxdisperr = rxdisperr_els_out; assign rxdisperr[1:0] = rxdisperr_els_out;
assign rxnotintable = rxnotintable_els_out; assign rxnotintable[1:0] = rxnotintable_els_out;
assign rxcharisk = rxcharisk_els_out; assign rxcharisk[1:0] = rxcharisk_els_out;
assign rxdata = rxdata_els_out; assign rxdata[15:0] = rxdata_els_out;
end end
else begin else begin
// unconsidered case // unconsidered case
...@@ -601,12 +608,12 @@ gtx( ...@@ -601,12 +608,12 @@ gtx(
.CPLLREFCLKLOST (), .CPLLREFCLKLOST (),
.CPLLREFCLKSEL (3'b001), .CPLLREFCLKSEL (3'b001),
.CPLLRESET (cpllreset), .CPLLRESET (cpllreset),
.GTRSVD (1'b0), .GTRSVD (16'b0),
.PCSRSVDIN (1'b0), .PCSRSVDIN (16'b0),
.PCSRSVDIN2 (1'b0), .PCSRSVDIN2 (5'b0),
.PMARSVDIN (1'b0), .PMARSVDIN (5'b0),
.PMARSVDIN2 (1'b0), .PMARSVDIN2 (5'b0),
.TSTIN (1'b1), .TSTIN (20'h1),
.TSTOUT (), .TSTOUT (),
.CLKRSVD (4'b0000), .CLKRSVD (4'b0000),
.GTGREFCLK (1'b0), .GTGREFCLK (1'b0),
...@@ -624,8 +631,8 @@ gtx( ...@@ -624,8 +631,8 @@ gtx(
.DRPRDY (), .DRPRDY (),
.DRPWE (1'b0), .DRPWE (1'b0),
.GTREFCLKMONITOR (), .GTREFCLKMONITOR (),
.QPLLCLK (gtrefclk), .QPLLCLK (/*gtrefclk*/),
.QPLLREFCLK (gtrefclk), .QPLLREFCLK (/*gtrefclk*/),
.RXSYSCLKSEL (2'b00), .RXSYSCLKSEL (2'b00),
.TXSYSCLKSEL (2'b00), .TXSYSCLKSEL (2'b00),
.DMONITOROUT (), .DMONITOROUT (),
...@@ -768,7 +775,7 @@ gtx( ...@@ -768,7 +775,7 @@ gtx(
.TXCHARDISPVAL (txchardispval_gtx), .TXCHARDISPVAL (txchardispval_gtx),
.TXUSRCLK (txusrclk), .TXUSRCLK (txusrclk),
.TXUSRCLK2 (txusrclk), .TXUSRCLK2 (txusrclk),
.TXELECIDLE (txelecidle), .TXELECIDLE (txelecidle_gtx),
.TXMARGIN (3'd0), .TXMARGIN (3'd0),
.TXRATE (3'd0), .TXRATE (3'd0),
.TXSWING (1'b0), .TXSWING (1'b0),
......
host/link.v
View file @ 256f87fb
...@@ -100,6 +100,7 @@ module link #( ...@@ -100,6 +100,7 @@ module link #(
output wire [DATA_BYTE_WIDTH*8 - 1:0] phy_data_out, output wire [DATA_BYTE_WIDTH*8 - 1:0] phy_data_out,
output wire [DATA_BYTE_WIDTH - 1:0] phy_isk_out // charisk output wire [DATA_BYTE_WIDTH - 1:0] phy_isk_out // charisk
); );
wire frame_done;
// scrambled data // scrambled data
wire [DATA_BYTE_WIDTH*8 - 1:0] scrambler_out; wire [DATA_BYTE_WIDTH*8 - 1:0] scrambler_out;
wire dec_err; // doc, p.311 wire dec_err; // doc, p.311
...@@ -109,15 +110,11 @@ wire crc_bad; ...@@ -109,15 +110,11 @@ wire crc_bad;
// current crc // current crc
wire [31:0] crc_dword; wire [31:0] crc_dword;
reg data_txing; // if there are still some data to transmit and the transaction wasn't cancelled
always @ (posedge clk)
data_txing <= rst | (data_last_in & data_strobe_out | dword_val & rcvd_dword[CODE_DMATP]) ? 1'b0 : frame_req ? 1'b1 : data_txing;
// send primitives variety count, including CRC and DATA as primitives // send primitives variety count, including CRC and DATA as primitives
localparam PRIM_NUM = 15; localparam PRIM_NUM = 15;
// list of bits of rcvd_dword
wire [PRIM_NUM - 1:0] rcvd_dword; // shows current processing primitive (or just data dword) wire [PRIM_NUM - 1:0] rcvd_dword; // shows current processing primitive (or just data dword)
wire dword_val; wire dword_val;
// list of bits of rcvd_dword
localparam CODE_DATA = 0; localparam CODE_DATA = 0;
localparam CODE_CRC = 1; localparam CODE_CRC = 1;
localparam CODE_SYNCP = 2; localparam CODE_SYNCP = 2;
...@@ -134,6 +131,9 @@ localparam CODE_DMATP = 12; ...@@ -134,6 +131,9 @@ localparam CODE_DMATP = 12;
localparam CODE_OKP = 13; localparam CODE_OKP = 13;
localparam CODE_ERRP = 14; localparam CODE_ERRP = 14;
reg data_txing; // if there are still some data to transmit and the transaction wasn't cancelled
always @ (posedge clk)
data_txing <= rst | (data_last_in & data_strobe_out | dword_val & rcvd_dword[CODE_DMATP]) ? 1'b0 : frame_req ? 1'b1 : data_txing;
// fsm // fsm
// states and transitions are taken from the doc, "Link Layer State Machine" chapter // states and transitions are taken from the doc, "Link Layer State Machine" chapter
...@@ -391,21 +391,21 @@ generate ...@@ -391,21 +391,21 @@ generate
if (DATA_BYTE_WIDTH == 2) if (DATA_BYTE_WIDTH == 2)
begin begin
reg prim_word; // word counter in a primitive TODO logic reg prim_word; // word counter in a primitive TODO logic
assign prim_data[CODE_SYNCP] = prim_word ? PRIM_SYNCP_HI : PRIM_SYNCP_LO; assign prim_data[CODE_SYNCP] [15:0] = prim_word ? PRIM_SYNCP_HI : PRIM_SYNCP_LO;
assign prim_data[CODE_ALIGNP] = prim_word ? PRIM_ALIGNP_HI : PRIM_ALIGNP_LO; assign prim_data[CODE_ALIGNP][15:0] = prim_word ? PRIM_ALIGNP_HI : PRIM_ALIGNP_LO;
assign prim_data[CODE_XRDYP] = prim_word ? PRIM_XRDYP_HI : PRIM_XRDYP_LO; assign prim_data[CODE_XRDYP] [15:0] = prim_word ? PRIM_XRDYP_HI : PRIM_XRDYP_LO;
assign prim_data[CODE_SOFP] = prim_word ? PRIM_SOFP_HI : PRIM_SOFP_LO; assign prim_data[CODE_SOFP] [15:0] = prim_word ? PRIM_SOFP_HI : PRIM_SOFP_LO;
assign prim_data[CODE_DATA] = scrambler_out; assign prim_data[CODE_DATA] [15:0] = scrambler_out[15:0];
assign prim_data[CODE_HOLDAP] = prim_word ? PRIM_HOLDAP_HI : PRIM_HOLDAP_LO; assign prim_data[CODE_HOLDAP][15:0] = prim_word ? PRIM_HOLDAP_HI : PRIM_HOLDAP_LO;
assign prim_data[CODE_HOLDP] = prim_word ? PRIM_HOLDP_HI : PRIM_HOLDP_LO; assign prim_data[CODE_HOLDP] [15:0] = prim_word ? PRIM_HOLDP_HI : PRIM_HOLDP_LO;
assign prim_data[CODE_CRC] = scrambler_out; assign prim_data[CODE_CRC] [15:0] = scrambler_out[15:0];
assign prim_data[CODE_EOFP] = prim_word ? PRIM_EOFP_HI : PRIM_EOFP_LO; assign prim_data[CODE_EOFP] [15:0] = prim_word ? PRIM_EOFP_HI : PRIM_EOFP_LO;
assign prim_data[CODE_WTRMP] = prim_word ? PRIM_WTRMP_HI : PRIM_WTRMP_LO; assign prim_data[CODE_WTRMP] [15:0] = prim_word ? PRIM_WTRMP_HI : PRIM_WTRMP_LO;
assign prim_data[CODE_RRDYP] = prim_word ? PRIM_RRDYP_HI : PRIM_RRDYP_LO; assign prim_data[CODE_RRDYP] [15:0] = prim_word ? PRIM_RRDYP_HI : PRIM_RRDYP_LO;
assign prim_data[CODE_IPP] = prim_word ? PRIM_IPP_HI : PRIM_IPP_LO; assign prim_data[CODE_IPP] [15:0] = prim_word ? PRIM_IPP_HI : PRIM_IPP_LO;
assign prim_data[CODE_DMATP] = prim_word ? PRIM_DMATP_HI : PRIM_DMATP_LO; assign prim_data[CODE_DMATP] [15:0] = prim_word ? PRIM_DMATP_HI : PRIM_DMATP_LO;
assign prim_data[CODE_OKP] = prim_word ? PRIM_OKP_HI : PRIM_OKP_LO; assign prim_data[CODE_OKP] [15:0] = prim_word ? PRIM_OKP_HI : PRIM_OKP_LO;
assign prim_data[CODE_ERRP] = prim_word ? PRIM_ERRP_HI : PRIM_ERRP_LO; assign prim_data[CODE_ERRP] [15:0] = prim_word ? PRIM_ERRP_HI : PRIM_ERRP_LO;
always @ (posedge clk) always @ (posedge clk)
begin begin
$display("%m: unsupported data width"); $display("%m: unsupported data width");
...@@ -577,7 +577,6 @@ assign rcvd_dword[CODE_ERRP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_W ...@@ -577,7 +577,6 @@ assign rcvd_dword[CODE_ERRP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_W
assign dec_err = |phy_err_in; assign dec_err = |phy_err_in;
// form a response to transport layer // form a response to transport layer
wire frame_done;
assign frame_done = frame_done_good | frame_done_bad; assign frame_done = frame_done_good | frame_done_bad;
assign frame_done_good = state_wait & dword_val & rcvd_dword[CODE_OKP]; assign frame_done_good = state_wait & dword_val & rcvd_dword[CODE_OKP];
assign frame_done_bad = state_wait & dword_val & rcvd_dword[CODE_ERRP]; assign frame_done_bad = state_wait & dword_val & rcvd_dword[CODE_ERRP];
......
host/oob.v
View file @ 256f87fb
...@@ -274,6 +274,10 @@ always @ (posedge clk) ...@@ -274,6 +274,10 @@ always @ (posedge clk)
cominit_req_r <= (cominit_req_r | cominit_req_set) & ~(cominit_allow & cominit_req) & ~rst; cominit_req_r <= (cominit_req_r | cominit_req_set) & ~(cominit_allow & cominit_req) & ~rst;
assign cominit_req = cominit_req_set | cominit_req_r; assign cominit_req = cominit_req_set | cominit_req_r;
// primitives
wire [63:0] alignp = {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100, 8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100};
wire [63:0] syncp = {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100, 8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100};
// detect which primitives sends the device after comwake was done // detect which primitives sends the device after comwake was done
generate generate
if (DATA_BYTE_WIDTH == 2) if (DATA_BYTE_WIDTH == 2)
...@@ -281,26 +285,26 @@ generate ...@@ -281,26 +285,26 @@ generate
reg detected_alignp_f; reg detected_alignp_f;
always @ (posedge clk) always @ (posedge clk)
detected_alignp_f <= rst | ~state_wait_align ? 1'b0 : detected_alignp_f <= rst | ~state_wait_align ? 1'b0 :
~|(rxdata ^ {8'b01001010, 8'b10111100}) & ~|(rxcharisk ^ 2'b01); // {D10.2, K28.5} ~|(rxdata[15:0] ^ alignp[15:0]) & ~|(rxcharisk[1:0] ^ 2'b01); // {D10.2, K28.5}
assign detected_alignp = detected_alignp_f & ~|(rxdata ^ {8'b01111011, 8'b01001010}) & ~|(rxcharisk ^ 2'b00); // {D27.3, D10.2} assign detected_alignp = detected_alignp_f & ~|(rxdata[15:0] ^ alignp[31:16]) & ~|(rxcharisk[1:0] ^ 2'b00); // {D27.3, D10.2}
reg detected_syncp_f; reg detected_syncp_f;
always @ (posedge clk) always @ (posedge clk)
detected_syncp_f <= rst | ~state_wait_synp ? 1'b0 : detected_syncp_f <= rst | ~state_wait_synp ? 1'b0 :
~|(rxdata ^ {8'b10010101, 8'b01111100}) & ~|(rxcharisk ^ 2'b01); // {D21.4, K28.3} ~|(rxdata[15:0] ^ syncp[15:0]) & ~|(rxcharisk[1:0] ^ 2'b01); // {D21.4, K28.3}
assign detected_syncp = detected_syncp_f & ~|(rxdata ^ {8'b10110101, 8'b10110101}) & ~|(rxcharisk ^ 2'b00); // {D21.5, D21.5} assign detected_syncp = detected_syncp_f & ~|(rxdata[15:0] ^ syncp[31:16]) & ~|(rxcharisk[1:0] ^ 2'b00); // {D21.5, D21.5}
end end
else else
if (DATA_BYTE_WIDTH == 4) if (DATA_BYTE_WIDTH == 4)
begin begin
assign detected_alignp = ~|(rxdata ^ {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}) & ~|(rxcharisk ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5} assign detected_alignp = ~|(rxdata[31:0] ^ alignp[31:0]) & ~|(rxcharisk[3:0] ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5}
assign detected_syncp = ~|(rxdata ^ {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}) & ~|(rxcharisk ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3} assign detected_syncp = ~|(rxdata[31:0] ^ syncp[31:0]) & ~|(rxcharisk[3:0] ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3}
end end
else else
if (DATA_BYTE_WIDTH == 8) if (DATA_BYTE_WIDTH == 8)
begin begin
assign detected_alignp = ~|(rxdata ^ {2{8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}}) & ~|(rxcharisk ^ 8'h11); // {D27.3, D10.2, D10.2, K28.5} assign detected_alignp = ~|(rxdata[63:0] ^ alignp[63:0]) & ~|(rxcharisk[7:0] ^ 8'h11); // {D27.3, D10.2, D10.2, K28.5}
assign detected_syncp = ~|(rxdata ^ {2{8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}}) & ~|(rxcharisk ^ 8'h11); // {D21.5, D21.5, D21.4, K28.3} assign detected_syncp = ~|(rxdata[63:0] ^ syncp[63:0]) & ~|(rxcharisk[7:0] ^ 8'h11); // {D21.5, D21.5, D21.4, K28.3}
end end
else else
begin begin
...@@ -367,21 +371,21 @@ generate ...@@ -367,21 +371,21 @@ generate
always @ (posedge clk) always @ (posedge clk)
align_odd <= rst | ~state_wait_synp ? 1'b0 : ~align_odd; align_odd <= rst | ~state_wait_synp ? 1'b0 : ~align_odd;
assign txcharisk_align = align_odd ? 2'b01 : 2'b00; assign txcharisk_align[DATA_BYTE_WIDTH - 1:0] = align_odd ? 2'b01 : 2'b00;
assign txdata_align = align_odd ? {8'b01001010, 8'b10111100} : // {D10.2, K28.5} assign txdata_align[DATA_BYTE_WIDTH*8 - 1:0] = align_odd ? alignp[15:0] : // {D10.2, K28.5}
{8'b01111011, 8'b01001010}; // {D27.3, D10.2} alignp[31:16]; // {D27.3, D10.2}
end end
else else
if (DATA_BYTE_WIDTH == 4) if (DATA_BYTE_WIDTH == 4)
begin begin
assign txcharisk_align = 4'h1; assign txcharisk_align[DATA_BYTE_WIDTH - 1:0] = 4'h1;
assign txdata_align = {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}; // {D27.3, D10.2, D10.2, K28.5} assign txdata_align[DATA_BYTE_WIDTH*8 - 1:0] = alignp[DATA_BYTE_WIDTH*8 - 1:0]; // {D27.3, D10.2, D10.2, K28.5}
end end
else else
if (DATA_BYTE_WIDTH == 8) if (DATA_BYTE_WIDTH == 8)
begin begin
assign txcharisk_align = 8'h11; assign txcharisk_align[DATA_BYTE_WIDTH - 1:0] = 8'h11;
assign txdata_align = {2{8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}}; // 2x{D27.3, D10.2, D10.2, K28.5} assign txdata_align[DATA_BYTE_WIDTH*8 - 1:0] = alignp[DATA_BYTE_WIDTH*8 - 1:0]; // 2x{D27.3, D10.2, D10.2, K28.5}
end end
else else
always @ (posedge clk) always @ (posedge clk)
...@@ -411,7 +415,7 @@ end ...@@ -411,7 +415,7 @@ end
`endif `endif
always @ (posedge clk) always @ (posedge clk)
rxcom_timer <= rst | rxcominit_done & state_wait_cominit | rxcomwake_done & state_wait_comwake | rxcominitdet & state_wait_cominit | rxcomwakedet & state_wait_comwake ? 10'h0 : cominit_req_l & state_idle | rxcominitdet_l & state_wait_cominit | rxcomwakedet_l & state_wait_comwake ? rxcom_timer + CLK_TO_TIMER_CONTRIB : 10'h0; rxcom_timer <= rst | rxcominit_done & state_wait_cominit | rxcomwake_done & state_wait_comwake | rxcominitdet & state_wait_cominit | rxcomwakedet & state_wait_comwake ? 10'h0 : cominit_req_l & state_idle | rxcominitdet_l & state_wait_cominit | rxcomwakedet_l & state_wait_comwake ? rxcom_timer + CLK_TO_TIMER_CONTRIB[9:0] : 10'h0;
// set data outputs to gtx // set data outputs to gtx
assign txdata_out = txdata; assign txdata_out = txdata;
...@@ -420,7 +424,7 @@ assign txcharisk_out = txcharisk; ...@@ -420,7 +424,7 @@ assign txcharisk_out = txcharisk;
// rxelectidle timer logic // rxelectidle timer logic
assign eidle_timer_done = eidle_timer == 64; assign eidle_timer_done = eidle_timer == 64;
always @ (posedge clk) always @ (posedge clk)
eidle_timer <= rst | rxelecidle | ~state_wait_eidle ? 8'b0 : eidle_timer + CLK_TO_TIMER_CONTRIB; eidle_timer <= rst | rxelecidle | ~state_wait_eidle ? 8'b0 : eidle_timer + CLK_TO_TIMER_CONTRIB[7:0];
endmodule endmodule
host/sata_host.v
View file @ 256f87fb
...@@ -147,7 +147,6 @@ wire [7:0] tl2cl_sh_status; ...@@ -147,7 +147,6 @@ wire [7:0] tl2cl_sh_status;
wire [7:0] tl2cl_sh_estatus; // E_Status wire [7:0] tl2cl_sh_estatus; // E_Status
wire [7:0] tl2cl_sh_dev; wire [7:0] tl2cl_sh_dev;
wire [3:0] tl2cl_sh_port; wire [3:0] tl2cl_sh_port;
wire tl2cl_shter_in;
wire tl2cl_sh_dir; wire tl2cl_sh_dir;
wire tl2cl_sh_inter; wire tl2cl_sh_inter;
wire [63:0] tl2cl_sh_dma_id; wire [63:0] tl2cl_sh_dma_id;
...@@ -164,7 +163,6 @@ wire tl2cl_sh_status_val; ...@@ -164,7 +163,6 @@ wire tl2cl_sh_status_val;
wire tl2cl_sh_estatus_val; // E_Status wire tl2cl_sh_estatus_val; // E_Status
wire tl2cl_sh_dev_val; wire tl2cl_sh_dev_val;
wire tl2cl_sh_port_val; wire tl2cl_sh_port_val;
wire tl2cl_shter_val_in;
wire tl2cl_sh_dir_val; wire tl2cl_sh_dir_val;
wire tl2cl_sh_inter_val; wire tl2cl_sh_inter_val;
wire tl2cl_sh_dma_id_val; wire tl2cl_sh_dma_id_val;
...@@ -560,7 +558,7 @@ transport transport( ...@@ -560,7 +558,7 @@ transport transport(
// oob sequence is reinitiated and link now is not established or rxelecidle // oob sequence is reinitiated and link now is not established or rxelecidle
wire link_reset; //wire link_reset; // use ~phy_ready instead
// phy is ready - link is established // phy is ready - link is established
wire phy_ready; wire phy_ready;
......
host/sata_phy.v
View file @ 256f87fb
...@@ -46,7 +46,7 @@ module sata_phy #( ...@@ -46,7 +46,7 @@ module sata_phy #(
// to link layer // to link layer
output wire [DATA_BYTE_WIDTH * 8 - 1:0] ll_data_out, output wire [DATA_BYTE_WIDTH * 8 - 1:0] ll_data_out,
output wire [DATA_BYTE_WIDTH - 1:0] ll_charisk_out, output wire [DATA_BYTE_WIDTH - 1:0] ll_charisk_out,
output wire [DATA_BYTE_WIDTH - 1:0] ll_err_out, // TODO!!! output wire [DATA_BYTE_WIDTH - 1:0] ll_err_out,
// from link layer // from link layer
input wire [DATA_BYTE_WIDTH * 8 - 1:0] ll_data_in, input wire [DATA_BYTE_WIDTH * 8 - 1:0] ll_data_in,
...@@ -61,6 +61,10 @@ wire [DATA_BYTE_WIDTH - 1:0] txcharisk; ...@@ -61,6 +61,10 @@ wire [DATA_BYTE_WIDTH - 1:0] txcharisk;
wire [DATA_BYTE_WIDTH - 1:0] rxcharisk; wire [DATA_BYTE_WIDTH - 1:0] rxcharisk;
wire [DATA_BYTE_WIDTH - 1:0] txcharisk_in; wire [DATA_BYTE_WIDTH - 1:0] txcharisk_in;
wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_out; wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_out;
wire [DATA_BYTE_WIDTH - 1:0] rxdisperr;
wire [DATA_BYTE_WIDTH - 1:0] rxnotintable;
assign ll_err_out = rxdisperr | rxnotintable;
// once gtx_ready -> 1, gtx_configured latches // once gtx_ready -> 1, gtx_configured latches
// after this point it's possible to perform additional resets and reconfigurations by higher-level logic // after this point it's possible to perform additional resets and reconfigurations by higher-level logic
...@@ -170,7 +174,7 @@ localparam RXEYERESET_TIME = 7'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + R ...@@ -170,7 +174,7 @@ localparam RXEYERESET_TIME = 7'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + R
reg [6:0] rxeyereset_cnt; reg [6:0] rxeyereset_cnt;
assign rxeyereset_done = rxeyereset_cnt == RXEYERESET_TIME; assign rxeyereset_done = rxeyereset_cnt == RXEYERESET_TIME;
always @ (posedge gtrefclk) always @ (posedge gtrefclk)
rxeyereset_cnt <= rxreset ? 3'h0 : rxeyereset_done ? rxeyereset_cnt : rxeyereset_cnt + 1'b1; rxeyereset_cnt <= rxreset ? 7'h0 : rxeyereset_done ? rxeyereset_cnt : rxeyereset_cnt + 1'b1;
/* /*
* Resets * Resets
...@@ -322,8 +326,7 @@ gtx_wrap #( ...@@ -322,8 +326,7 @@ gtx_wrap #(
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME), .RXCDRPHRESET_TIME (RXCDRPHRESET_TIME),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME), .RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME),
.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME), .RXDFELPMRESET_TIME (RXDFELPMRESET_TIME),
.RXISCANRESET_TIME (RXISCANRESET_TIME), .RXISCANRESET_TIME (RXISCANRESET_TIME)
.RXEYERESET_TIME (RXEYERESET_TIME)
) )
gtx_wrap gtx_wrap
( (
...@@ -360,7 +363,9 @@ gtx_wrap ...@@ -360,7 +363,9 @@ gtx_wrap
.txdata (txdata), .txdata (txdata),
.txcharisk (txcharisk), .txcharisk (txcharisk),
.rxdata (rxdata), .rxdata (rxdata),
.rxcharisk (rxcharisk) .rxcharisk (rxcharisk),
.rxdisperr (rxdisperr),
.rxnotintable (rxnotintable)
); );
/* /*
* Interfaces * Interfaces
...@@ -368,7 +373,8 @@ gtx_wrap ...@@ -368,7 +373,8 @@ gtx_wrap
assign cplllockdetclk = gtrefclk; //TODO assign cplllockdetclk = gtrefclk; //TODO
assign drpclk = gtrefclk; assign drpclk = gtrefclk;
assign clk = usrclk2; //assign clk = usrclk2;
BUFG bufg_sclk (.O(clk),.I(usrclk2));
assign rxn = rxn_in; assign rxn = rxn_in;
assign rxp = rxp_in; assign rxp = rxp_in;
assign txn_out = txn; assign txn_out = txn;
......
host/transport.v
View file @ 256f87fb
...@@ -176,6 +176,8 @@ module transport #( ...@@ -176,6 +176,8 @@ module transport #(
output wire watchdog_dwords output wire watchdog_dwords
); );
reg [7:0] state;
//TODO //TODO
assign sync_escape_req = 1'b0; assign sync_escape_req = 1'b0;
assign incom_stop_req = 1'b0; assign incom_stop_req = 1'b0;
...@@ -221,8 +223,6 @@ localparam [2:0] CMD_TYPE_DMA_SETUP = 3'h2; ...@@ -221,8 +223,6 @@ localparam [2:0] CMD_TYPE_DMA_SETUP = 3'h2;
localparam [2:0] CMD_TYPE_DATA = 3'h3; localparam [2:0] CMD_TYPE_DATA = 3'h3;
localparam [2:0] CMD_TYPE_BIST_ACT = 3'h4; localparam [2:0] CMD_TYPE_BIST_ACT = 3'h4;
// asserts after FIS is sent
reg cmd_done_f;
// current header dword // current header dword
wire [31:0] ll_header_dword; wire [31:0] ll_header_dword;
// current dword shall be header's // current dword shall be header's
...@@ -237,9 +237,6 @@ reg [13:0] dword_cnt; ...@@ -237,9 +237,6 @@ reg [13:0] dword_cnt;
assign watchdog_dwords = dword_cnt == 14'd2049; assign watchdog_dwords = dword_cnt == 14'd2049;
// ask for a receiving termination in case of errors // ask for a receiving termination in case of errors
reg incom_stop_req_timeout; reg incom_stop_req_timeout;
// dma activate is received when its type met and no errors occurs
assign got_dma_activate = state == STATE_INCOMING & cl_data_last_in & ll_data_val_in & ll_data_in[7:0] == 8'h39;
assign got_dma_activate_port = {4{got_dma_activate}} & ll_data_in[11:8];
// global TL fsm // global TL fsm
/* /*
...@@ -287,8 +284,6 @@ localparam STATE_OUT_BIST = 8'hb0; // BIST Activate FIS Host to Device ...@@ -287,8 +284,6 @@ localparam STATE_OUT_BIST = 8'hb0; // BIST Activate FIS Host to Device
localparam STATE_OUT_WAIT_RESP = 8'hc0; // localparam STATE_OUT_WAIT_RESP = 8'hc0; //
localparam STATE_IN_UNRECOG = 8'hf0; // Unrecognized FIS from Device localparam STATE_IN_UNRECOG = 8'hf0; // Unrecognized FIS from Device
reg [7:0] state;
always @ (posedge clk) always @ (posedge clk)
if (rst) if (rst)
begin begin
...@@ -1127,17 +1122,17 @@ assign header_regfis = dword_cnt[2:0] == 3'h0 ? {sh_feature_in[7:0], sh_comm ...@@ -1127,17 +1122,17 @@ assign header_regfis = dword_cnt[2:0] == 3'h0 ? {sh_feature_in[7:0], sh_comm
/*dword_cnt[2:0] == 3'h4 ?*/ {32'h0000}; // Reserved /*dword_cnt[2:0] == 3'h4 ?*/ {32'h0000}; // Reserved
// DMA Setup FIS header // DMA Setup FIS header
wire [31:0] header_dmas; wire [31:0] header_dmas;
assign header_dmas = dword_cnt[3:0] == 3'h0 ? {8'h0, 8'h0, sh_autoact_in, sh_inter_in, sh_dir_in, 1'b0, cmd_port_r, 8'h41} : // Reserved, Reserved, A I D R PMPort, FIS Type assign header_dmas = dword_cnt[3:0] == 4'h0 ? {8'h0, 8'h0, sh_autoact_in, sh_inter_in, sh_dir_in, 1'b0, cmd_port_r, 8'h41} : // Reserved, Reserved, A I D R PMPort, FIS Type
dword_cnt[3:0] == 3'h1 ? {sh_dma_id_in[31:0]} : // DMA Buffer Identifier Low dword_cnt[3:0] == 4'h1 ? {sh_dma_id_in[31:0]} : // DMA Buffer Identifier Low
dword_cnt[3:0] == 3'h2 ? {sh_dma_id_in[63:32]} : // DMA Buffer Identifier High dword_cnt[3:0] == 4'h2 ? {sh_dma_id_in[63:32]} : // DMA Buffer Identifier High
dword_cnt[3:0] == 3'h4 ? {sh_buf_off_in[31:0]} : // DMA Buffer Offset dword_cnt[3:0] == 4'h4 ? {sh_buf_off_in[31:0]} : // DMA Buffer Offset
dword_cnt[3:0] == 3'h5 ? {sh_dma_cnt_in[31:0]} : // DMA Transfer Count dword_cnt[3:0] == 4'h5 ? {sh_dma_cnt_in[31:0]} : // DMA Transfer Count
/* 3'h3 | 3'h6 */ {32'h0000}; // Reserved /* 4'h3 | 4'h6 */ {32'h0000}; // Reserved
// BIST Activate FIS header // BIST Activate FIS header
wire [31:0] header_bist; // TODO wire [31:0] header_bist; // TODO
assign header_bist = dword_cnt[3:0] == 3'h0 ? {8'h00, 8'h00, 4'h0, cmd_port_r, 8'h58} : // Reserved, T A S L F P R V, R R R R PMPort, FIS Type assign header_bist = dword_cnt[2:0] == 3'h0 ? {8'h00, 8'h00, 4'h0, cmd_port_r, 8'h58} : // Reserved, T A S L F P R V, R R R R PMPort, FIS Type
dword_cnt[3:0] == 3'h1 ? {32'h00000000} : // Data1 dword_cnt[2:0] == 3'h1 ? {32'h00000000} : // Data1
dword_cnt[3:0] == 3'h2 ? {32'h00000000} : // Data2 dword_cnt[2:0] == 3'h2 ? {32'h00000000} : // Data2
{32'h00000000}; {32'h00000000};
// Data FIS header // Data FIS header
wire [31:0] header_data; wire [31:0] header_data;
...@@ -1212,6 +1207,9 @@ assign sh_tran_cnt_val_out = ll_data_last_in; ...@@ -1212,6 +1207,9 @@ assign sh_tran_cnt_val_out = ll_data_last_in;
assign sh_notif_val_out = ll_data_last_in; assign sh_notif_val_out = ll_data_last_in;
assign sh_autoact_val_out = ll_data_last_in; assign sh_autoact_val_out = ll_data_last_in;
// dma activate is received when its type met and no errors occurs
assign got_dma_activate = state == STATE_INCOMING & cl_data_last_in & ll_data_val_in & ll_data_in[7:0] == 8'h39;
assign got_dma_activate_port = {4{got_dma_activate}} & ll_data_in[11:8];
`ifdef CHECKERS_ENABLED `ifdef CHECKERS_ENABLED
always @ (posedge clk) always @ (posedge clk)
......
simul/build
View file @ 256f87fb
...@@ -17,8 +17,7 @@ if [ "$GTX_PATH" == '' ] ...@@ -17,8 +17,7 @@ if [ "$GTX_PATH" == '' ]
then then
export GTX_PATH=$SATA_PATH export GTX_PATH=$SATA_PATH
fi fi
#iverilog $SATA_PATH/tb/tb_top.v $SATA_PATH/x393/glbl.v $SATA_PATH/gtxe2_gpl/GTXE2_CHANNEL.v -I$SATA_PATH/device -I$SATA_PATH/host -I$SATA_PATH/dma -I$SATA_PATH/tb -I$SATA_PATH -I$SATA_PATH/x393/axi -I$SATA_PATH/x393 -I$SATA_PATH/x393/wrap -y$SATA_PATH/x393/util_modules -y$SATA_PATH/x393/wrap -y$UNISIMS_PATH -y$SATA_PATH/x393/memctrl -y$SATA_PATH/x393/axi -y$SATA_PATH/x393/simulation_modules $SATA_PATH/x393/simulation_modules/simul_axi_fifo_out.v -y$SATA_PATH/x393/ -D SIMULATION -D CHECKERS_ENABLED iverilog $SATA_PATH/tb/tb_top.v $SATA_PATH/x393/glbl.v $SATA_PATH/gtxe2_gpl/GTXE2_CHANNEL.v -I$SATA_PATH/device -I$SATA_PATH/host -I$SATA_PATH/dma -I$SATA_PATH/tb -I$SATA_PATH -I$SATA_PATH/x393/axi -I$SATA_PATH/x393 -I$SATA_PATH/x393/wrap -y$SATA_PATH/x393/util_modules -y$SATA_PATH/x393/wrap -y$UNISIMS_PATH -y$SATA_PATH/x393/memctrl -y$SATA_PATH/x393/axi -y$SATA_PATH/x393/simulation_modules $SATA_PATH/x393/simulation_modules/simul_axi_fifo_out.v -y$SATA_PATH/x393/ -D SIMULATION -D CHECKERS_ENABLED -D PRELOAD_BRAMS
iverilog $SATA_PATH/tb/tb_top.v $SATA_PATH/x393/glbl.v $SATA_PATH/gtxe2_gpl/GTXE2_CHANNEL.v -I$SATA_PATH/device -I$SATA_PATH/host -I$SATA_PATH/dma -I$SATA_PATH/tb -I$SATA_PATH -I$SATA_PATH/x393/axi -I$SATA_PATH/x393 -I$SATA_PATH/x393/wrap -y$SATA_PATH/x393/util_modules -y$SATA_PATH/x393/wrap -y$UNISIMS_PATH -y$SATA_PATH/x393/memctrl -y$SATA_PATH/x393/axi -y$SATA_PATH/x393/simulation_modules $SATA_PATH/x393/simulation_modules/simul_axi_fifo_out.v -y$SATA_PATH/x393/ -D SIMULATION -D CHECKERS_ENABLED
#iverilog $SATA_PATH/neat_phy.v $SATA_PATH/x393/glbl.v $SATA_PATH/gtxe2_gpl/GTXE2_CHANNEL.v $SATA_PATH/neat_oob.v -y$UNISIMS_PATH #iverilog $SATA_PATH/neat_phy.v $SATA_PATH/x393/glbl.v $SATA_PATH/gtxe2_gpl/GTXE2_CHANNEL.v $SATA_PATH/neat_oob.v -y$UNISIMS_PATH
#iverilog $SATA_PATH/tb/tb_top.v $SATA_PATH/x393/glbl.v -f opts -stb -sglbl $1 2>&1| tee $LOGFILE_PATH #iverilog $SATA_PATH/tb/tb_top.v $SATA_PATH/x393/glbl.v -f opts -stb -sglbl $1 2>&1| tee $LOGFILE_PATH
......
synt/top.xdc 0 → 100644
View file @ 256f87fb
# bind gtx reference clock
set_property PACKAGE_PIN U6 [get_ports EXTCLK_P]
set_property PACKAGE_PIN U5 [get_ports EXTCLK_N]
# bind sata inputs/outputs
set_property PACKAGE_PIN AA5 [get_ports RXN]
set_property PACKAGE_PIN AA6 [get_ports RXP]
set_property PACKAGE_PIN AB3 [get_ports TXN]
set_property PACKAGE_PIN AB4 [get_ports TXP]
# manually placing usrpll in the same region where gtx is located : x0y0
startgroup
place_cell sata_top/sata_host/phy/usrclk_pll PLLE2_ADV_X0Y0/PLLE2_ADV
endgroup
synt/top_timing.xdc 0 → 100644
View file @ 256f87fb
# clock, received via FCLK input from PS7
# barely used for now
create_clock -name axi_aclk0 -period 20.000 -waveform {0.000 10.000} {get_nets axi_aclk0}
# external clock 150Mhz
create_clock -name gtrefclk -period 6.666 -waveform {0.000 3.333} {get_nets sata_top.sata_host.sata_phy.gtrefclk}
# after plls inside of GTX:
create_clock -name txoutclk -period 13.333 -waveform {0.000 6.666} {get_nets sata_top.sata_host.sata_phy.txoutclk}
# txoutclk -> userpll, which gives us 2 clocks: userclk and userclk2. The second one is sata host clk
create_generate_clock -name usrclk -source [get_clocks txoutclk] -multiply_by 2 [get_nets sata_top.sata_host.sata_phy.usrclk]
create_generate_clock -name sclk -source [get_clocks txoutclk] [get_nets sata_top.sata_host.sata_phy.usrclk2]
tb/tb_top.v
View file @ 256f87fb
...@@ -38,6 +38,10 @@ begin ...@@ -38,6 +38,10 @@ begin
$dumpvars(0,tb); $dumpvars(0,tb);
end end
reg EXTCLK_P = 1'b1;
reg EXTCLK_N = 1'b0;
//reg serial_clk = 1'b1;
reg [11:0] ARID_IN_r; reg [11:0] ARID_IN_r;
reg [31:0] ARADDR_IN_r; reg [31:0] ARADDR_IN_r;
reg [3:0] ARLEN_IN_r; reg [3:0] ARLEN_IN_r;
...@@ -67,7 +71,7 @@ reg [31:0] SIMUL_AXI_READ; ...@@ -67,7 +71,7 @@ reg [31:0] SIMUL_AXI_READ;
reg [SIMUL_AXI_READ_WIDTH-1:0] SIMUL_AXI_ADDR; reg [SIMUL_AXI_READ_WIDTH-1:0] SIMUL_AXI_ADDR;
// SuppressWarnings VEditor // SuppressWarnings VEditor
reg SIMUL_AXI_FULL; // some data available reg SIMUL_AXI_FULL; // some data available
wire SIMUL_AXI_EMPTY= ~rvalid && rready && (rid==LAST_ARID); //SuppressThisWarning VEditor : may be unused, just for simulation // use it to wait for? wire SIMUL_AXI_EMPTY;
reg [31:0] registered_rdata; // here read data from task reg [31:0] registered_rdata; // here read data from task
//reg CLK; //reg CLK;
...@@ -134,10 +138,10 @@ wire bvalid; ...@@ -134,10 +138,10 @@ wire bvalid;
wire bready; wire bready;
integer NUM_WORDS_READ; integer NUM_WORDS_READ;
integer NUM_WORDS_EXPECTED; integer NUM_WORDS_EXPECTED;
reg [15:0] ENABLED_CHANNELS = 0; // currently enabled memory channels
// integer SCANLINE_CUR_X; // integer SCANLINE_CUR_X;
// integer SCANLINE_CUR_Y; // integer SCANLINE_CUR_Y;
wire AXI_RD_EMPTY=NUM_WORDS_READ==NUM_WORDS_EXPECTED; //SuppressThisWarning VEditor : may be unused, just for simulation wire AXI_RD_EMPTY=NUM_WORDS_READ==NUM_WORDS_EXPECTED; //SuppressThisWarning VEditor : may be unused, just for simulation
assign SIMUL_AXI_EMPTY= ~rvalid && rready && (rid==LAST_ARID); //SuppressThisWarning VEditor : may be unused, just for simulation // use it to wait for?
wire [11:0] #(AXI_TASK_HOLD) ARID_IN = ARID_IN_r; wire [11:0] #(AXI_TASK_HOLD) ARID_IN = ARID_IN_r;
wire [31:0] #(AXI_TASK_HOLD) ARADDR_IN = ARADDR_IN_r; wire [31:0] #(AXI_TASK_HOLD) ARADDR_IN = ARADDR_IN_r;
...@@ -333,9 +337,6 @@ simul_axi_read #( ...@@ -333,9 +337,6 @@ simul_axi_read #(
.burst(), // burst in progress - just debug .burst(), // burst in progress - just debug
.err_out()); // data last does not match predicted or FIFO over/under run - just debug .err_out()); // data last does not match predicted or FIFO over/under run - just debug
reg EXTCLK_P = 1'b1;
reg EXTCLK_N = 1'b0;
reg serial_clk = 1'b1;
// device-under-test instance // device-under-test instance
wire rxn; wire rxn;
......
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