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Commit 1fefe120 authored by Andrey Filippov's avatar Andrey Filippov
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FSM modifications, first time driver recognized disk

parent 98d19134
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.project
View file @ 1fefe120
......@@ -52,87 +52,87 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160229131258090.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160229185157261.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160229131258090.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160229185157261.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160229131258090.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160229185157261.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160229131258090.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160229185157261.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160229131258090.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160229185157261.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160229131258090.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160229185157261.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160229131105264.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160229184939748.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160229131258090.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160229185157261.log</location>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160229131105264.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160229184939748.log</location>
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<name>vivado_logs/VivadoTimingReportImplemented.log</name>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160229131258090.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160229185157261.log</location>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160229131105264.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160229184939748.log</location>
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<link>
<name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160229131258090.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160229185157261.dcp</location>
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<name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160229131258090.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160229185157261.dcp</location>
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<name>vivado_state/x393_sata-opt.dcp</name>
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<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160229131258090.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160229185157261.dcp</location>
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<name>vivado_state/x393_sata-place.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160229131258090.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160229185157261.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-route.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160229131258090.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160229185157261.dcp</location>
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<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160229131105264.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160229184939748.dcp</location>
</link>
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</projectDescription>
ahci/ahci_fsm.v
View file @ 1fefe120
......@@ -247,6 +247,13 @@ module ahci_fsm
);
`include "includes/ahci_localparams.vh" // @SuppressThisWarning VEditor : Unused localparams
`include "includes/fis_types.vh" // @SuppressThisWarning VEditor : Some localparams unused
// Reset addresses - later use generated
localparam LABEL_POR = 11'h000;
localparam LABEL_HBA_RST = 11'h002;
localparam LABEL_PORT_RST = 11'h004;
localparam LABEL_COMINIT = 11'h006;
localparam LABEL_ST_CLEARED = 11'h008;
wire tfd_bsy = tfd_sts[7];
wire tfd_drq = tfd_sts[3];
wire tfd_sts_err = tfd_sts[0];
......@@ -276,7 +283,8 @@ module ahci_fsm
(syncesc_send_pend && syncesc_send_done) ||
dma_abort_done ||
asynq_rq; // cominit_got || pcmd_st_cleared
reg fsm_act_done; // made later by 1 cycle so the new conditions are latched
reg fsm_act_done; // made later by 1 cycle so the new conditions are latched // TODO:check is enough ? Adding 1 extra
reg fsm_act_pre_done;
wire fsm_wait_act_w = pgm_data[16]; // this action requires waiting for done
wire fsm_last_act_w = pgm_data[17];
......@@ -304,6 +312,10 @@ module ahci_fsm
// reg unsolicited_cominit_en; // allow unsolicited COMINITs
// wire en_cominit; // en_cominit
// New variable:
reg pisn32; // pIssueSlot != 32
wire clear_pisn32; // additional clear when in P:NotRunning state
assign fsm_next = (fsm_preload || (fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]) && !async_pend_r[0]; // quiet if received cominit is pending
assign update_all = fsm_jump[0];
......@@ -333,12 +345,12 @@ module ahci_fsm
else if (pgm_wa) pgm_waddr <= pgm_ad[ 9:0];
else if (pgm_wd) pgm_waddr <= pgm_waddr + 1;
end
// Reset addresses - later use generated
localparam LABEL_POR = 11'h000;
localparam LABEL_HBA_RST = 11'h002;
localparam LABEL_PORT_RST = 11'h004;
localparam LABEL_COMINIT = 11'h006;
localparam LABEL_ST_CLEARED = 11'h008;
always @ (posedge mclk) begin
if (hba_rst || pxci0_clear || clear_pisn32) pisn32 <= 0;
else if (fetch_cmd) pisn32 <= 1;
end
always @ (posedge mclk) begin
/// if (hba_rst) unsolicited_cominit_en <= !was_port_rst;
......@@ -352,8 +364,9 @@ module ahci_fsm
was_rst <= hba_rst;
fsm_act_done <= fsm_act_done_w; // delay by 1 clock cycle
/// fsm_act_done <= fsm_act_done_w; // delay by 1 clock cycle
fsm_act_pre_done <= fsm_act_done_w; // delay by 1 clock cycle
fsm_act_done <= fsm_act_pre_done; // TODO - verify delay by 2 is needed to latch
fsm_jump <= {fsm_jump[1:0], pre_jump_w | (was_rst & ~hba_rst)};
if (fsm_jump[0]) pgm_addr <= pgm_jump_addr;
......@@ -472,7 +485,7 @@ module ahci_fsm
.R_OK (send_R_OK), // output reg
.R_ERR (send_R_ERR), // output reg
// .EN_COMINIT (en_cominit), // output reg
.EN_COMINIT (), // output reg
.EN_COMINIT (clear_pisn32), // output reg
// FIS TRANSMIT/WAIT DONE
.FETCH_CMD (fetch_cmd), // output reg
.ATAPI_XMIT (atapi_xmit), // output reg
......@@ -496,7 +509,8 @@ module ahci_fsm
.condition (cond_met_w), // output
//COMPOSITE
.ST_NB_ND (pcmd_st && !tfd_bsy &&!tfd_drq), // input PxCMD.ST & !PxTFD.STS.BSY & !PxTFD.STS.DRQ
.PXCI0_NOT_CMDTOISSUE (pxci0 && !pCmdToIssue), // input pxci0 && !pCmdToIssue was pIssueSlot==32, -> p:SelectCmd
// .PXCI0_NOT_CMDTOISSUE (pxci0 && !pCmdToIssue), // input pxci0 && !pCmdToIssue was pIssueSlot==32, -> p:SelectCmd
.PXCI0_NOT_CMDTOISSUE (pxci0 && !pisn32), // input pxci0 && !pCmdToIssue was pIssueSlot==32, -> p:SelectCmd
.PCTI_CTBAR_XCZ (pCmdToIssue && xfer_cntr_zero && ch_r ), // input pCmdToIssue && ch_r && xfer_cntr_zero
.PCTI_XCZ (pCmdToIssue && xfer_cntr_zero), // input pCmdToIssue && xfer_cntr_zero
.NST_D2HR (!pcmd_st && (fis_type == FIS_D2HR)), // input !ST && (FIS == FIS_D2HR) TODO: does it mean either BSY or DRQ are 1?
......
generated/action_decoder.v
View file @ 1fefe120
/*******************************************************************************
* Module: action_decoder
* Date:2016-02-22
* Date:2016-02-29
* Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Decode sequencer code to 1-hot actions
*******************************************************************************/
......
generated/condition_mux.v
View file @ 1fefe120
/*******************************************************************************
* Module: condition_mux
* Date:2016-02-22
* Date:2016-02-29
* Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Select condition
*******************************************************************************/
......
helpers/ahci_fsm_sequence.py
View file @ 1fefe120
......@@ -285,6 +285,9 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{LBL:'RegFIS:Accept', ACT: 'R_OK'}, # send R_OK
{ ACT: 'UPDATE_ERR_STS'}, # update_err_sts
{ ACT: 'NOP'}, # 3 NOPs to propagate changes afte no-wait action
{ ACT: 'NOP'}, #
{ ACT: 'NOP'}, #
{IF: 'TFD_STS_ERR', GOTO:'ERR:FatalTaskfile'}, # 1. tfd_sts[0]
{IF: 'NB_ND', GOTO:'RegFIS:ClearCI'}, # 2. PxTFD.STS.BSY =’0’ and PxTFD.STS.DRQ =’0’
{ GOTO:'RegFIS:UpdateSig'}, # 3.
......@@ -296,6 +299,7 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{LBL:'RegFIS:SetIntr', ACT: 'SIRQ_DHR'}, # sirq_DHR
{ GOTO:'RegFIS:UpdateSig'}, # 2. (PxIE/IRQ is handled)
#RegFIS:SetIS, RegFIS:GenIntr are handled by hardware, skipping
{LBL:'RegFIS:UpdateSig', ACT: 'UPDATE_SIG'}, # update_sig will only update if pUpdateSig
{ GOTO:'PM:Aggr' }, # 1
......@@ -313,6 +317,9 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'P:Idle' }, # 5.
{LBL:'PIO:Update', ACT: 'UPDATE_PIO'}, # update_pio - update PxTFD.STS and PxTFD.ERR from pio_*
{ ACT: 'NOP'}, # 3 NOPs to propagate changes afte no-wait action
{ ACT: 'NOP'}, #
{ ACT: 'NOP'}, #
{IF: 'TFD_STS_ERR', GOTO:'ERR:FatalTaskfile'}, # 1. tfd_sts[0]
{IF: 'NB_ND', GOTO:'PIO:ClearCI'}, # 2. PxTFD.STS.BSY =’0’ and PxTFD.STS.DRQ =’0’
{IF: 'PIO_I', GOTO:'PIO:SetIntr'}, # 3. pio_i
......@@ -320,6 +327,7 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{LBL:'PIO:ClearCI', ACT: 'UPDATE_PRDBC'}, # update_prdbc
{ ACT: 'PXCI0_CLEAR'}, # pxci0_clear, reset both (pIssueSlot:=32) and PxCI[0]
{IF: 'PIO_I', GOTO:'PIO:SetIntr'}, # 2. pio_i
{ GOTO:'PM:Aggr' }, # 3.
#PIO:Ccc - not implemented
......@@ -398,6 +406,9 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{LBL:'SDB:Accept', ACT: 'R_OK'}, # get_sdbfis Is in only for Native CC ?
{ ACT: 'UPDATE_ERR_STS'}, # update_err_sts
{ ACT: 'NOP'}, # 3 NOPs to propagate changes afte no-wait action
{ ACT: 'NOP'}, #
{ ACT: 'NOP'}, #
{IF: 'TFD_STS_ERR', GOTO:'ERR:FatalTaskfile'}, # 1. tfd_sts[0]
{IF: 'FIS_I', GOTO:'SDB:SetIntr'}, # 3. fis_i
{ GOTO:'PM:Aggr' }, # 4.
......
includes/ahxi_fsm_code.vh
View file @ 1fefe120
, .INIT_00 (256'h00100000000E0000000C02020035000000220000000C0000000A0000000C0000)
, .INIT_01 (256'h1C3B9448543244190060001B0108001B00500402040401040022000600120000)
, .INIT_02 (256'h001BC8300014000C0210002B24FD25050180001B0003004200180000001B4454)
, .INIT_02 (256'h001BC8300014000C0210002B2506250E0180001B0003004200180000001B4454)
, .INIT_03 (256'h44394C6A2C44141B0012003B01080028000A04080022001B01020110001B0005)
, .INIT_04 (256'h003B0210001B14480102005004020404003BB07F707C00A0003B8C6D845484C0)
, .INIT_05 (256'h045A0000005024FD25050240004E24FD25050240005E0000003B0000001B0210)
, .INIT_06 (256'h903B02200204006D0402009000E4A89568F218EB18CD98A958D9388464560C27)
, .INIT_07 (256'h0000003BB07F0000005200840022003BB07F707C307930F202080073D10750FA)
, .INIT_08 (256'hC891002200440093288D290100140210008824FD25050180009ED0FF0120003B)
, .INIT_09 (256'h29010024003B48810CAF29010210009924FD250504400052000C009300050093)
, .INIT_0A (256'h003000AF021000AD24FD2505024000520081005248A700220044003B48A728A3)
, .INIT_0B (256'h003B889E00300009003B889E50BC0044008800B7D0FF50FA042000B3883B089E)
, .INIT_0C (256'h24FD25050140003B889E50BC00440048021000C7C50524FD24FD00C000C20030)
, .INIT_0D (256'h29010014021000DD24FD25050280003B34D4000000D6001100D6C8D4021000D1)
, .INIT_0E (256'h021000EF24FD25050240003B0401021000E824FD25050480005201010052C8E2)
, .INIT_0F (256'h002100FF041001030021008400F8000000F8021000F624FD2505024000F80082)
, .INIT_10 (256'h0000000000000000000000000000003B00410107041001030000010302010103)
, .INIT_04 (256'h003B0210001B14480102005004020404003BB07F707C00A0003B8C6D845484C6)
, .INIT_05 (256'h045A000000502506250E0240004E2506250E0240005E0000003B0000001B0210)
, .INIT_06 (256'h903B02200204006D0402009000EDA89868FB18F418D398AF58DF388464560C27)
, .INIT_07 (256'h0000003BB07F0000005200840022003BB07F707C307930FB02080073D1105103)
, .INIT_08 (256'h00962890290A0000000000000014021000882506250E018000A1D1080120003B)
, .INIT_09 (256'h48810CB5290A0210009C2506250E04400052000C009600050096C89400220044)
, .INIT_0A (256'h024000520081005248AD00220044003B48AD28A9290A0000000000000024003B)
, .INIT_0B (256'h50C20044008800BDD1085103042000B9883B08A1003000B5021000B32506250E)
, .INIT_0C (256'h00440048021000CDC50E2506250600C000C80030003B88A100300009003B88A1)
, .INIT_0D (256'h0280003B34DA000000DC001100DCC8DA021000D72506250E0140003B88A150C2)
, .INIT_0E (256'h2506250E0480005201010052C8EB290A0000000000000014021000E32506250E)
, .INIT_0F (256'h021000FF2506250E024001010082021000F82506250E0240003B0401021000F1)
, .INIT_10 (256'h01100410010C0000010C0201010C002101080410010C00210084010100000101)
, .INIT_11 (256'h00000000000000000000000000000000000000000000000000000000003B0041)
, .INITP_00 (256'h8220098170902401E272722222800309418810820809C8020188800222222222)
, .INITP_01 (256'h8882227209C82720A09C22089C680272181A01CB889C8605A2A89C882068270C)
, .INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000008888)
, .INITP_01 (256'h89C827209C828009C22089C680272181A01CB889C8605A00AA2722081A00270C)
, .INITP_02 (256'h0000000000000000000000000000000000000000000000000000000222222208)
py393sata/x393sata.py
View file @ 1fefe120
......@@ -79,7 +79,8 @@ INT_STS= 0xf800700c
MAXI1_ADDR = 0x80000000
DATASCOPE_ADDR = 0x1000 + MAXI1_ADDR
COMMAND_HEADER0_OFFS = 0x800 # offset of the command header 0 in MAXI1 space
COMMAND_BUFFER_OFFSET = 0x0 # Just at the beginning of available memory
#COMMAND_BUFFER_OFFSET = 0x0 # Just at the beginning of available memory
COMMAND_BUFFER_OFFSET = 0x10 # Simulating offset in the AHCI driver
COMMAND_BUFFER_SIZE = 0x100 # 256 bytes - 128 before PRDT, 128+ - PRDTs (16 bytes each)
PRD_OFFSET = 0x80 # Start of the PRD table
FB_OFFS = 0xc00 # Needs 0x100 bytes
......@@ -600,13 +601,16 @@ class x393sata(object):
(5 << 0) | # 'CFL' - number of DWORDs in this CFIS
(0 << 5) | # 'A' Not ATAPI
(0 << 6) | # 'W' Not write to device
(1 << 7) | # 'P' Prefetchable = 1
# (1 << 7) | # 'P' Prefetchable = 1
(0 << 7) | # 'P' Prefetchable = 0
(0 << 8) | # 'R' Not a Reset
(0 << 9) | # 'B' Not a BIST
(1 << 10) | # 'C' Do clear BSY/CI after transmitting this command
# (1 << 10) | # 'C' Do clear BSY/CI after transmitting this command
(0 << 10) | # 'C' Do clear BSY/CI after transmitting this command
(1 << 16)) # 'PRDTL' - number of PRDT entries (just one)
self.x393_mem.write_mem(MAXI1_ADDR + COMMAND_HEADER0_OFFS + (2 << 2),
(COMMAND_ADDRESS) & 0xffffffc0) # 'CTBA' - Command table base address
# self.x393_mem.write_mem(MAXI1_ADDR + COMMAND_HEADER0_OFFS + (2 << 2),
# (COMMAND_ADDRESS) & 0xffffffc0) # 'CTBA' - Command table base address
self.x393_mem.write_mem(MAXI1_ADDR + COMMAND_HEADER0_OFFS + (2 << 2), (COMMAND_ADDRESS)) # 'CTBA' - Command table base address
# Write some junk to the higher addresses of the CFIS
#Only was needed for debugging, removing
"""
......
tb/tb_ahci.tf
View file @ 1fefe120
......@@ -805,7 +805,8 @@ localparam SYS_MEM_START = 32'h24180000; // 16384 bytes (4096 DWORDs of the syst
localparam SYS_MEM_SIZE = 16384; // bytes - size of system memory
// realtive to the system memory area
///localparam COMMAND_TABLE = 32'h3f00; // 256 bytes for a command table in the system memory
localparam COMMAND_TABLE = 32'h1000; // 256 bytes for a command table in the system memory
//localparam COMMAND_TABLE = 32'h1000; // 256 bytes for a command table in the system memory
localparam COMMAND_TABLE = 32'h1010; // testing non-aligned
//0x24181000
localparam IDENTIFY_BUF = 32'h3d00; // 512 bytes for a command table in the system memory
localparam PRD_OFFSET = 'h80; // start of PRD table - 128-th byte in command table
......@@ -896,13 +897,15 @@ localparam ATA_RBUF_DMA = 'he9; // Read 512 bytes from device buffer in DMA mod
maxigp1_writep ((CLB_OFFS32 + 0) << 2, (5 << 0) | // 'CFL' - number of DWORDs in thes CFIS
(0 << 5) | // 'A' Not ATAPI
(0 << 6) | // 'W' Not write to device
(1 << 7) | // 'P' Prefetchable = 1
// (1 << 7) | // 'P' Prefetchable = 1
(0 << 7) | // 'P' Prefetchable = 1
(0 << 8) | // 'R' Not a Reset
(0 << 9) | // 'B' Not a BIST
// (0 << 10) | // 'C' Do not clear BSY/CI after transmitting this command
(1 << 10) | // 'C' Do clear BSY/CI after transmitting this command
(0 << 10) | // 'C' Do not clear BSY/CI after transmitting this command
// (1 << 10) | // 'C' Do clear BSY/CI after transmitting this command
(1 << 16)); // 'PRDTL' - number of PRDT entries (just one)
maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address
// maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address
maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE)); // 'CTBA' - Command table base address
// Set Command Issued
maxigp1_writep (HBA_PORT__PxCI__CI__ADDR << 2, 1); // 'PxCI' - Set 'Command issue' for slot 0 (the only one)
// relax and enjoy
......@@ -934,7 +937,8 @@ localparam ATA_RBUF_DMA = 'he9; // Read 512 bytes from device buffer in DMA mod
// (0 << 10) | // 'C' Do not clear BSY/CI after transmitting this command
(1 << 10) | // 'C' Do clear BSY/CI after transmitting this command
(1 << 16)); // 'PRDTL' - number of PRDT entries (just one)
maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address
// maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address
maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE)); // 'CTBA' - Command table base address
// Set Command Issued
maxigp1_writep (HBA_PORT__PxCI__CI__ADDR << 2, 1); // 'PxCI' - Set 'Command issue' for slot 0 (the only one)
// relax and enjoy
......@@ -984,7 +988,8 @@ localparam ATA_RBUF_DMA = 'he9; // Read 512 bytes from device buffer in DMA mod
// (0 << 10) | // 'C' Do not clear BSY/CI after transmitting this command
(1 << 10) | // 'C' Do clear BSY/CI after transmitting this command
(4 << 16)); // 'PRDTL' - number of PRDT entries (4)
maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address
/// maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address
maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE)); // 'CTBA' - Command table base address
// Set Command Issued
maxigp1_writep (HBA_PORT__PxCI__CI__ADDR << 2, 1); // 'PxCI' - Set 'Command issue' for slot 0 (the only one)
// relax and enjoy
......@@ -1037,7 +1042,8 @@ localparam ATA_RBUF_DMA = 'he9; // Read 512 bytes from device buffer in DMA mod
// (0 << 10) | // 'C' Do not clear BSY/CI after transmitting this command
(1 << 10) | // 'C' Do clear BSY/CI after transmitting this command
(4 << 16)); // 'PRDTL' - number of PRDT entries (4)
maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address
/// maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address
maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE)); // 'CTBA' - Command table base address
// Set Command Issued
maxigp1_writep (HBA_PORT__PxCI__CI__ADDR << 2, 1); // 'PxCI' - Set 'Command issue' for slot 0 (the only one)
// relax and enjoy
......@@ -1075,7 +1081,8 @@ localparam ATA_RBUF_DMA = 'he9; // Read 512 bytes from device buffer in DMA mod
// (0 << 10) | // 'C' Do not clear BSY/CI after transmitting this command
(1 << 10) | // 'C' Do clear BSY/CI after transmitting this command
(1 << 16)); // 'PRDTL' - number of PRDT entries (1)
maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address
/// maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address
maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE)); // 'CTBA' - Command table base address
// Set Command Issued
maxigp1_writep (HBA_PORT__PxCI__CI__ADDR << 2, 1); // 'PxCI' - Set 'Command issue' for slot 0 (the only one)
// relax and enjoy
......
tb_ahci_01.sav
View file @ 1fefe120
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Mon Feb 29 20:08:59 2016
[*] Tue Mar 1 01:47:21 2016
[*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160229121502137.fst"
[dumpfile_mtime] "Mon Feb 29 19:15:38 2016"
[dumpfile_size] 4797559
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160229184025832.fst"
[dumpfile_mtime] "Tue Mar 1 01:42:30 2016"
[dumpfile_size] 15004446
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 29997600
[size] 1209 773
[pos] 2205 445
*-17.454018 30010000 62346574 72998842 74025406 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 47816000
[size] 1823 1180
[pos] 0 42
*-18.256386 48747934 62346574 72998842 74025406 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev.linkMonitorFIS.
......@@ -23,7 +23,6 @@
[treeopen] tb_ahci.dut.
[treeopen] tb_ahci.dut.axi_hp_clk_i.
[treeopen] tb_ahci.dut.sata_top.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.crc.
......@@ -40,14 +39,12 @@
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.ahci_dma_rd_stuff_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i.
......@@ -60,9 +57,9 @@
[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.
[treeopen] tb_ahci.simul_axi_read_i.
[sst_width] 368
[signals_width] 322
[signals_width] 409
[sst_expanded] 1
[sst_vpaned_height] 349
[sst_vpaned_height] 573
@820
tb_ahci.TESTBENCH_TITLE[639:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0]
......@@ -2532,9 +2529,82 @@ tb_ahci.simul_axi_hp_wr_i.wdata_i.fill[7:0]
-simul_axi_hp_wr
@800200
-ahci_dma
@23
@200
-
@800200
-debug_non_prefetchable
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.update_pio
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.update_err_sts
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_transitions[1:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_transitions_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.tfd_bsy
@29
[color] 3
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.conditions_ce
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.tfd_drq
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.tfd_sts[7:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.pxci0
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pxci0_clear
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pxci0
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pisn32
[color] 2
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0]
@22
[color] 2
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_jump_addr[9:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.fetch_cmd
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.cfis_xmit
tb_ahci.dut.sata_top.ahci_top_i.fsnd_ch_p
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.dma_start
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.dma_prd_start
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.dx_fis_pend_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.write_or_w
@1000200
-debug_non_prefetchable
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
@1401200
-group_end
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rdata[63:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_addr[31:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.wcount[21:1]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.wcount_plus_data_addr[21:1]
......
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