FSM modifications, first time driver recognized disk (1fefe120) · Commits · Elphel / x393_sata

.project

+17 −17

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		@@ -52,87 +52,87 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160229131258090.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160229185157261.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160229131258090.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160229185157261.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160229131258090.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160229185157261.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160229131258090.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160229185157261.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160229131258090.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160229185157261.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160229131258090.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160229185157261.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160229131105264.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160229184939748.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160229131258090.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160229185157261.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160229131105264.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160229184939748.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160229131258090.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160229185157261.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160229131105264.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160229184939748.log</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-opt-phys.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160229131258090.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160229185157261.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-opt-power.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160229131258090.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160229185157261.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-opt.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160229131258090.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160229185157261.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-place.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160229131258090.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160229185157261.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-route.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160229131258090.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160229185157261.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-synth.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160229131105264.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160229184939748.dcp</location>
		</link>
		</linkedResources>
		</projectDescription>

ahci/ahci_fsm.v

+26 −12

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		@@ -247,6 +247,13 @@ module ahci_fsm
		);
		`include "includes/ahci_localparams.vh" // @SuppressThisWarning VEditor : Unused localparams
		`include "includes/fis_types.vh" // @SuppressThisWarning VEditor : Some localparams unused
		// Reset addresses - later use generated
		localparam LABEL_POR = 11'h000;
		localparam LABEL_HBA_RST = 11'h002;
		localparam LABEL_PORT_RST = 11'h004;
		localparam LABEL_COMINIT = 11'h006;
		localparam LABEL_ST_CLEARED = 11'h008;

		wire tfd_bsy = tfd_sts[7];
		wire tfd_drq = tfd_sts[3];
		wire tfd_sts_err = tfd_sts[0];
		@@ -276,7 +283,8 @@ module ahci_fsm
		(syncesc_send_pend && syncesc_send_done) \|\|
		dma_abort_done \|\|
		asynq_rq; // cominit_got \|\| pcmd_st_cleared
		reg fsm_act_done; // made later by 1 cycle so the new conditions are latched
		reg fsm_act_done; // made later by 1 cycle so the new conditions are latched // TODO:check is enough ? Adding 1 extra
		reg fsm_act_pre_done;
		wire fsm_wait_act_w = pgm_data[16]; // this action requires waiting for done
		wire fsm_last_act_w = pgm_data[17];

		@@ -304,6 +312,10 @@ module ahci_fsm
		// reg unsolicited_cominit_en; // allow unsolicited COMINITs
		// wire en_cominit; // en_cominit

		// New variable:
		reg pisn32; // pIssueSlot != 32
		wire clear_pisn32; // additional clear when in P:NotRunning state

		assign fsm_next = (fsm_preload \|\| (fsm_actions && !update_busy && !fsm_act_busy) \|\| fsm_transitions[0]) && !async_pend_r[0]; // quiet if received cominit is pending
		assign update_all = fsm_jump[0];

		@@ -333,12 +345,12 @@ module ahci_fsm
		else if (pgm_wa) pgm_waddr <= pgm_ad[ 9:0];
		else if (pgm_wd) pgm_waddr <= pgm_waddr + 1;
		end
		// Reset addresses - later use generated
		localparam LABEL_POR = 11'h000;
		localparam LABEL_HBA_RST = 11'h002;
		localparam LABEL_PORT_RST = 11'h004;
		localparam LABEL_COMINIT = 11'h006;
		localparam LABEL_ST_CLEARED = 11'h008;

		always @ (posedge mclk) begin
		if (hba_rst \|\| pxci0_clear \|\| clear_pisn32) pisn32 <= 0;
		else if (fetch_cmd) pisn32 <= 1;

		end

		always @ (posedge mclk) begin
		/// if (hba_rst) unsolicited_cominit_en <= !was_port_rst;
		@@ -352,8 +364,9 @@ module ahci_fsm

		was_rst <= hba_rst;

		fsm_act_done <= fsm_act_done_w; // delay by 1 clock cycle

		/// fsm_act_done <= fsm_act_done_w; // delay by 1 clock cycle
		fsm_act_pre_done <= fsm_act_done_w; // delay by 1 clock cycle
		fsm_act_done <= fsm_act_pre_done; // TODO - verify delay by 2 is needed to latch
		fsm_jump <= {fsm_jump[1:0], pre_jump_w \| (was_rst & ~hba_rst)};

		if (fsm_jump[0]) pgm_addr <= pgm_jump_addr;
		@@ -472,7 +485,7 @@ module ahci_fsm
		.R_OK (send_R_OK), // output reg
		.R_ERR (send_R_ERR), // output reg
		// .EN_COMINIT (en_cominit), // output reg
		.EN_COMINIT (), // output reg
		.EN_COMINIT (clear_pisn32), // output reg
		// FIS TRANSMIT/WAIT DONE
		.FETCH_CMD (fetch_cmd), // output reg
		.ATAPI_XMIT (atapi_xmit), // output reg
		@@ -496,7 +509,8 @@ module ahci_fsm
		.condition (cond_met_w), // output
		//COMPOSITE
		.ST_NB_ND (pcmd_st && !tfd_bsy &&!tfd_drq), // input PxCMD.ST & !PxTFD.STS.BSY & !PxTFD.STS.DRQ
		.PXCI0_NOT_CMDTOISSUE (pxci0 && !pCmdToIssue), // input pxci0 && !pCmdToIssue was pIssueSlot==32, -> p:SelectCmd
		// .PXCI0_NOT_CMDTOISSUE (pxci0 && !pCmdToIssue), // input pxci0 && !pCmdToIssue was pIssueSlot==32, -> p:SelectCmd
		.PXCI0_NOT_CMDTOISSUE (pxci0 && !pisn32), // input pxci0 && !pCmdToIssue was pIssueSlot==32, -> p:SelectCmd
		.PCTI_CTBAR_XCZ (pCmdToIssue && xfer_cntr_zero && ch_r ), // input pCmdToIssue && ch_r && xfer_cntr_zero
		.PCTI_XCZ (pCmdToIssue && xfer_cntr_zero), // input pCmdToIssue && xfer_cntr_zero
		.NST_D2HR (!pcmd_st && (fis_type == FIS_D2HR)), // input !ST && (FIS == FIS_D2HR) TODO: does it mean either BSY or DRQ are 1?

generated/action_decoder.v

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		/*******************************************************************************
		* Module: action_decoder
		* Date:2016-02-22
		* Date:2016-02-29
		* Author: auto-generated file, see ahci_fsm_sequence.py
		* Description: Decode sequencer code to 1-hot actions
		*******************************************************************************/

generated/condition_mux.v

+1 −1

Original line number	Diff line number	Diff line
		/*******************************************************************************
		* Module: condition_mux
		* Date:2016-02-22
		* Date:2016-02-29
		* Author: auto-generated file, see ahci_fsm_sequence.py
		* Description: Select condition
		*******************************************************************************/

helpers/ahci_fsm_sequence.py

+11 −0

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		@@ -285,6 +285,9 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},

		{LBL:'RegFIS:Accept', ACT: 'R_OK'}, # send R_OK
		{ ACT: 'UPDATE_ERR_STS'}, # update_err_sts
		{ ACT: 'NOP'}, # 3 NOPs to propagate changes afte no-wait action
		{ ACT: 'NOP'}, #
		{ ACT: 'NOP'}, #
		{IF: 'TFD_STS_ERR', GOTO:'ERR:FatalTaskfile'}, # 1. tfd_sts[0]
		{IF: 'NB_ND', GOTO:'RegFIS:ClearCI'}, # 2. PxTFD.STS.BSY =’0’ and PxTFD.STS.DRQ =’0’
		{ GOTO:'RegFIS:UpdateSig'}, # 3.
		@@ -296,6 +299,7 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},

		{LBL:'RegFIS:SetIntr', ACT: 'SIRQ_DHR'}, # sirq_DHR
		{ GOTO:'RegFIS:UpdateSig'}, # 2. (PxIE/IRQ is handled)

		#RegFIS:SetIS, RegFIS:GenIntr are handled by hardware, skipping
		{LBL:'RegFIS:UpdateSig', ACT: 'UPDATE_SIG'}, # update_sig will only update if pUpdateSig
		{ GOTO:'PM:Aggr' }, # 1
		@@ -313,6 +317,9 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
		{ GOTO:'P:Idle' }, # 5.

		{LBL:'PIO:Update', ACT: 'UPDATE_PIO'}, # update_pio - update PxTFD.STS and PxTFD.ERR from pio_*
		{ ACT: 'NOP'}, # 3 NOPs to propagate changes afte no-wait action
		{ ACT: 'NOP'}, #
		{ ACT: 'NOP'}, #
		{IF: 'TFD_STS_ERR', GOTO:'ERR:FatalTaskfile'}, # 1. tfd_sts[0]
		{IF: 'NB_ND', GOTO:'PIO:ClearCI'}, # 2. PxTFD.STS.BSY =’0’ and PxTFD.STS.DRQ =’0’
		{IF: 'PIO_I', GOTO:'PIO:SetIntr'}, # 3. pio_i
		@@ -320,6 +327,7 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},

		{LBL:'PIO:ClearCI', ACT: 'UPDATE_PRDBC'}, # update_prdbc
		{ ACT: 'PXCI0_CLEAR'}, # pxci0_clear, reset both (pIssueSlot:=32) and PxCI[0]

		{IF: 'PIO_I', GOTO:'PIO:SetIntr'}, # 2. pio_i
		{ GOTO:'PM:Aggr' }, # 3.
		#PIO:Ccc - not implemented
		@@ -398,6 +406,9 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},

		{LBL:'SDB:Accept', ACT: 'R_OK'}, # get_sdbfis Is in only for Native CC ?
		{ ACT: 'UPDATE_ERR_STS'}, # update_err_sts
		{ ACT: 'NOP'}, # 3 NOPs to propagate changes afte no-wait action
		{ ACT: 'NOP'}, #
		{ ACT: 'NOP'}, #
		{IF: 'TFD_STS_ERR', GOTO:'ERR:FatalTaskfile'}, # 1. tfd_sts[0]
		{IF: 'FIS_I', GOTO:'SDB:SetIntr'}, # 3. fis_i
		{ GOTO:'PM:Aggr' }, # 4.

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