Commit 1ede10e9 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

converted to a Makefile project

parent f96d208f

.gitignore

+2 −0
Original line number Diff line number Diff line
@@ -12,3 +12,5 @@ x393.prj 
*.old

*.pyc

*.pickle

bitbake-logs                                                                                                                                               

sysroots

Makefile

0 → 100644
+24 −0
Original line number Diff line number Diff line 
VERILOGDIR=   $(DESTDIR)/usr/local/verilog

INSTALLDIR=   $(DESTDIR)/usr/local/bin

SCRIPTPATH=   py393sata

 

OWN = -o root -g root



INSTMODE   = 0755

DOCMODE    = 0644



PYTHON_EXE = $(SCRIPTPATH)/*.py

FPGA_BITFILES =   x393_sata.bit



all:

	@echo "make all in x393sata"

install:

	@echo "make install in x393sata"

	$(INSTALL) $(OWN) -d $(VERILOGDIR)

	$(INSTALL) $(OWN) -d $(INSTALLDIR)



	$(INSTALL) $(OWN) -m $(INSTMODE) $(PYTHON_EXE)                          $(INSTALLDIR)

	$(INSTALL) $(OWN) -m $(DOCMODE)  $(FPGA_BITFILES)                       $(VERILOGDIR)

clean:

	@echo "make clean in x393sata"

	
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