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x393_sata
Commit 17ebdc3d authored by Andrey Filippov's avatar Andrey Filippov
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started simulation

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.settings/com.elphel.vdt.iverilog.prefs
View file @ 17ebdc3d
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_122_IVerilogOther<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_119_GTKWaveSavFile<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->iverilog_122_GrepFindErrWarn<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@-> com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_122_IVerilogOther<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_119_GTKWaveSavFile<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->iverilog_122_GrepFindErrWarn<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->iverilog_95_IcarusTopFile<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
iverilog_101_TopModulesOther=glbl<-@\#\#@-> iverilog_101_TopModulesOther=glbl<-@\#\#@->
iverilog_102_TopModulesOther=glbl<-@\#\#@-> iverilog_102_TopModulesOther=glbl<-@\#\#@->
...@@ -15,7 +15,7 @@ iverilog_113_SaveLogsPreprocessor=true ...@@ -15,7 +15,7 @@ iverilog_113_SaveLogsPreprocessor=true
iverilog_114_SaveLogsSimulator=true iverilog_114_SaveLogsSimulator=true
iverilog_115_SaveLogsSimulator=true iverilog_115_SaveLogsSimulator=true
iverilog_119_GTKWaveSavFile=tb_top_02.sav iverilog_119_GTKWaveSavFile=tb_top_02.sav
iverilog_120_GTKWaveSavFile=tb_top_02.sav iverilog_120_GTKWaveSavFile=tb_ahci_01.sav
iverilog_122_GrepFindErrWarn=error|warning|sorry iverilog_122_GrepFindErrWarn=error|warning|sorry
iverilog_77_Param_Exe=/usr/local/bin/iverilog iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp iverilog_78_VVP_Exe=/usr/local/bin/vvp
...@@ -24,4 +24,5 @@ iverilog_81_TopModulesOther=glbl<-@\#\#@-> ...@@ -24,4 +24,5 @@ iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@-> iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_88_ShowNoProblem=true iverilog_88_ShowNoProblem=true
iverilog_89_ShowNoProblem=true iverilog_89_ShowNoProblem=true
iverilog_95_IcarusTopFile=tb/tb_ahci.tf
iverilog_99_GrepFindErrWarn=error|warning|sorry iverilog_99_GrepFindErrWarn=error|warning|sorry
ahci/ahci_fsm.v
View file @ 17ebdc3d
...@@ -316,7 +316,8 @@ module ahci_fsm ...@@ -316,7 +316,8 @@ module ahci_fsm
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (hba_rst) pgm_jump_addr <= (was_hba_rst || was_port_rst) ? (was_hba_rst? LABEL_HBA_RST:LABEL_PORT_RST) : LABEL_POR; if (hba_rst) pgm_jump_addr <= (was_hba_rst || was_port_rst) ? (was_hba_rst? LABEL_HBA_RST:LABEL_PORT_RST) : LABEL_POR;
else if (async_pend_r[1]) pgm_jump_addr <= async_from_st? LABEL_ST_CLEARED : LABEL_COMINIT; // else if (async_pend_r[1]) pgm_jump_addr <= async_from_st? LABEL_ST_CLEARED : LABEL_COMINIT;
else if (async_pend_r[0]) pgm_jump_addr <= async_from_st? LABEL_ST_CLEARED : LABEL_COMINIT;
else if (fsm_transitions[0] && (!cond_met_w || !fsm_transitions[1])) pgm_jump_addr <= pgm_data[9:0]; else if (fsm_transitions[0] && (!cond_met_w || !fsm_transitions[1])) pgm_jump_addr <= pgm_data[9:0];
was_rst <= hba_rst; was_rst <= hba_rst;
......
ahci/ahci_top.v
View file @ 17ebdc3d
...@@ -21,10 +21,12 @@ ...@@ -21,10 +21,12 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module ahci_top#( module ahci_top#(
parameter PREFETCH_ALWAYS = 0, parameter PREFETCH_ALWAYS = 0,
parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen
parameter ADDRESS_BITS = 10 // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle) parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
parameter HBA_RESET_BITS = 9, // duration of HBA reset in aclk periods (9: ~10usec)
parameter RESET_TO_FIRST_ACCESS = 1 // keep port reset until first R/W any register by software
)( )(
input aclk, // clock - should be buffered input aclk, // clock - should be buffered
input arst, // @aclk sync reset, active high input arst, // @aclk sync reset, active high
...@@ -32,8 +34,8 @@ module ahci_top#( ...@@ -32,8 +34,8 @@ module ahci_top#(
input mrst, // reset in mclk clock domain (after SATA PLL is on) input mrst, // reset in mclk clock domain (after SATA PLL is on)
// async reset for SATA (mrst will be response to it) // async reset for SATA (mrst will be response to it)
output hba_arst, // hba async reset (currently does ~ the same as port reset) output hba_arst, // hba async reset (currently does ~ the same as port reset)
output port_arst, // port0 async reset by software output port_arst, // port0 async set by software (does not include arst)
output port_arst_any, // port0 async set by software and by arst
input hclk, // AXI HP interface clock for 64-bit DMA (current - 150MHz input hclk, // AXI HP interface clock for 64-bit DMA (current - 150MHz
input hrst, // reset in hclk clock domain input hrst, // reset in hclk clock domain
// MAXIGP1 // MAXIGP1
...@@ -594,7 +596,9 @@ module ahci_top#( ...@@ -594,7 +596,9 @@ module ahci_top#(
axi_ahci_regs #( axi_ahci_regs #(
.ADDRESS_BITS(10) .ADDRESS_BITS (ADDRESS_BITS),
.HBA_RESET_BITS (HBA_RESET_BITS),
.RESET_TO_FIRST_ACCESS (RESET_TO_FIRST_ACCESS)
) axi_ahci_regs_i ( ) axi_ahci_regs_i (
.aclk (aclk), // input .aclk (aclk), // input
.arst (arst), // input .arst (arst), // input
...@@ -632,6 +636,7 @@ module ahci_top#( ...@@ -632,6 +636,7 @@ module ahci_top#(
.soft_write_data (soft_write_data), // output[31:0] .soft_write_data (soft_write_data), // output[31:0]
.soft_write_en (soft_write_en), // output .soft_write_en (soft_write_en), // output
.hba_arst (hba_arst), // output // does not include arst .hba_arst (hba_arst), // output // does not include arst
.port_arst_any (port_arst_any), // async set by arst
.port_arst (port_arst), // output // does not include arst .port_arst (port_arst), // output // does not include arst
.hba_clk (mclk), // input .hba_clk (mclk), // input
.hba_rst (mrst), // input // deasserted when mclk is stable .hba_rst (mrst), // input // deasserted when mclk is stable
......
ahci/axi_ahci_regs.v
View file @ 17ebdc3d
...@@ -40,7 +40,8 @@ ...@@ -40,7 +40,8 @@
module axi_ahci_regs#( module axi_ahci_regs#(
// parameter ADDRESS_BITS = 8 // number of memory address bits // parameter ADDRESS_BITS = 8 // number of memory address bits
parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle) parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
parameter HBA_RESET_BITS = 9 // duration of HBA reset in aclk periods (9: ~10usec) parameter HBA_RESET_BITS = 9, // duration of HBA reset in aclk periods (9: ~10usec)
parameter RESET_TO_FIRST_ACCESS = 1 // keep port reset until first R/W any register by software
)( )(
input aclk, // clock - should be buffered input aclk, // clock - should be buffered
input arst, // @aclk sync reset, active high input arst, // @aclk sync reset, active high
...@@ -89,6 +90,7 @@ module axi_ahci_regs#( ...@@ -89,6 +90,7 @@ module axi_ahci_regs#(
// Apply next 2 resets and arst OR-ed to SATA.extrst // Apply next 2 resets and arst OR-ed to SATA.extrst
output hba_arst, // hba async reset (currently does ~ the same as port reset) output hba_arst, // hba async reset (currently does ~ the same as port reset)
output port_arst, // port0 async reset by software output port_arst, // port0 async reset by software
output port_arst_any, // port0 async reset by POR or software
// 2. HBA R/W registers, use hba clock // 2. HBA R/W registers, use hba clock
input hba_clk, // SATA clock, now 75MHz input hba_clk, // SATA clock, now 75MHz
...@@ -161,9 +163,10 @@ module axi_ahci_regs#( ...@@ -161,9 +163,10 @@ module axi_ahci_regs#(
wire [31:0] wmask = {{8{bram_wstb_r[3]}},{8{bram_wstb_r[2]}},{8{bram_wstb_r[1]}},{8{bram_wstb_r[0]}}}; wire [31:0] wmask = {{8{bram_wstb_r[3]}},{8{bram_wstb_r[2]}},{8{bram_wstb_r[1]}},{8{bram_wstb_r[0]}}};
reg [ADDRESS_BITS-1:0] bram_waddr_r; reg [ADDRESS_BITS-1:0] bram_waddr_r;
reg [HBA_RESET_BITS-1:0] hba_reset_cntr = 1; // time to keep hba_reset_r active after writing to GHC.HR reg [HBA_RESET_BITS-1:0] hba_reset_cntr; // time to keep hba_reset_r active after writing to GHC.HR
reg hba_rst_r; // hba _reset (currently does ~ the same as port reset) reg hba_rst_r; // hba _reset (currently does ~ the same as port reset)
reg port_rst_r; // port _reset by software reg port_rst_r; // port _reset by software
reg port_arst_any_r = 1; // port _reset by software or POR
wire high_sel = bram_waddr_r[ADDRESS_BITS-1]; // high addresses - use single-cycle writes without read-modify-write wire high_sel = bram_waddr_r[ADDRESS_BITS-1]; // high addresses - use single-cycle writes without read-modify-write
wire afi_cache_set_w = bram_wen_r && !high_sel && (bram_addr == HBA_PORT__AFI_CACHE__WR_CM__ADDR); wire afi_cache_set_w = bram_wen_r && !high_sel && (bram_addr == HBA_PORT__AFI_CACHE__WR_CM__ADDR);
...@@ -178,17 +181,19 @@ module axi_ahci_regs#( ...@@ -178,17 +181,19 @@ module axi_ahci_regs#(
wire port_rst_on = set_port_rst && ahci_regs_di[0]; wire port_rst_on = set_port_rst && ahci_regs_di[0];
reg was_hba_rst_aclk; // last reset was hba reset (not counting system reset) reg was_hba_rst_aclk; // last reset was hba reset (not counting system reset)
reg was_port_rst_aclk; // last reset was port reset reg was_port_rst_aclk; // last reset was port reset
reg [2:0] was_hba_rst_r; // last reset was hba reset (not counting system reset) reg [2:0] was_hba_rst_r; // last reset was hba reset (not counting system reset)
reg [2:0] was_port_rst_r; // last reset was port reset reg [2:0] was_port_rst_r; // last reset was port reset
reg [2:0] arst_r = ~0; // previous state of arst
reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access
wire any_access = bram_wen_r || bram_ren[0];
// assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen ? bram_waddr : pre_awaddr); // assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen ? bram_waddr : pre_awaddr);
assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr); assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
assign hba_arst = hba_rst_r; // hba _reset (currently does ~ the same as port reset) assign hba_arst = hba_rst_r; // hba _reset (currently does ~ the same as port reset)
assign port_arst = port_rst_r; // port _reset by software assign port_arst = port_rst_r; // port _reset by software
assign port_arst_any = port_arst_any_r;
assign was_hba_rst = was_hba_rst_r[0]; assign was_hba_rst = was_hba_rst_r[0];
assign was_port_rst = was_port_rst_r[0]; assign was_port_rst = was_port_rst_r[0];
always @(posedge aclk) begin always @(posedge aclk) begin
...@@ -221,6 +226,17 @@ module axi_ahci_regs#( ...@@ -221,6 +226,17 @@ module axi_ahci_regs#(
end end
endgenerate endgenerate
// always @ (posedge aclk or posedge arst) begin
always @ (posedge aclk) begin
if (arst) wait_first_access <= RESET_TO_FIRST_ACCESS;
else if (any_access) wait_first_access <= 0;
if (arst) port_arst_any_r <= 1;
else if (set_port_rst) port_arst_any_r <= ahci_regs_di[0]; // write "1" - reset on, write 0 - reset off
else if (wait_first_access && any_access) port_arst_any_r <= 0;
else if (arst_r[2] && !arst_r[1]) port_arst_any_r <= wait_first_access;
end
always @(posedge aclk) begin always @(posedge aclk) begin
if (arst) hba_reset_cntr <= 0; // 1; no HBA reset at arst if (arst) hba_reset_cntr <= 0; // 1; no HBA reset at arst
else if (set_hba_rst) hba_reset_cntr <= {HBA_RESET_BITS{1'b1}}; else if (set_hba_rst) hba_reset_cntr <= {HBA_RESET_BITS{1'b1}};
...@@ -236,6 +252,9 @@ module axi_ahci_regs#( ...@@ -236,6 +252,9 @@ module axi_ahci_regs#(
if (arst || set_hba_rst) was_port_rst_aclk <= 0; if (arst || set_hba_rst) was_port_rst_aclk <= 0;
else if (port_rst_on) was_port_rst_aclk <= 1; else if (port_rst_on) was_port_rst_aclk <= 1;
if (arst) arst_r <= ~0;
else arst_r <= arst_r << 1;
end end
......
ahci/sata_ahci_top.v
View file @ 17ebdc3d
...@@ -35,7 +35,14 @@ ...@@ -35,7 +35,14 @@
/* /*
* Takes commands from axi iface as a slave, transfers data with another axi iface as a master * Takes commands from axi iface as a slave, transfers data with another axi iface as a master
*/ */
module sata_ahci_top( module sata_ahci_top#(
parameter PREFETCH_ALWAYS = 0,
// parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
// parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen
parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
parameter HBA_RESET_BITS = 9, // duration of HBA reset in aclk periods (9: ~10usec)
parameter RESET_TO_FIRST_ACCESS = 1 // keep port reset until first R/W any register by software
)(
output wire sata_clk, output wire sata_clk,
output wire sata_rst, output wire sata_rst,
input wire arst, // extrst, input wire arst, // extrst,
...@@ -157,11 +164,11 @@ ...@@ -157,11 +164,11 @@
// wire sata_clk; // wire sata_clk;
// wire sata_rst; // wire sata_rst;
wire hba_arst; wire hba_arst; // @SuppressThisWarning VEditor unused
wire port_arst; // @SuppressThisWarning VEditor unused
wire port_arst_any;
wire exrst = port_arst_any; // now both hba_arst and port_arst are the same?
wire port_arst;
wire exrst = port_arst; // now both hba_arst and port_arst are the same?
// Data/type FIFO, host -> device // Data/type FIFO, host -> device
...@@ -224,10 +231,12 @@ ...@@ -224,10 +231,12 @@
ahci_top #( ahci_top #(
.PREFETCH_ALWAYS(0), .PREFETCH_ALWAYS (PREFETCH_ALWAYS),
.READ_REG_LATENCY(2), // .READ_REG_LATENCY (READ_REG_LATENCY),
.READ_CT_LATENCY(1), // .READ_CT_LATENCY (READ_CT_LATENCY),
.ADDRESS_BITS(10) .ADDRESS_BITS (ADDRESS_BITS),
.HBA_RESET_BITS (HBA_RESET_BITS),
.RESET_TO_FIRST_ACCESS (RESET_TO_FIRST_ACCESS)
) ahci_top_i ( ) ahci_top_i (
.aclk (ACLK), // input .aclk (ACLK), // input
.arst (arst), // input .arst (arst), // input
...@@ -235,6 +244,8 @@ ...@@ -235,6 +244,8 @@
.mrst (sata_rst), // input .mrst (sata_rst), // input
.hba_arst (hba_arst), // output .hba_arst (hba_arst), // output
.port_arst (port_arst), // output .port_arst (port_arst), // output
.port_arst_any (port_arst_any), // port0 async set by software and by arst
.hclk (hclk), // input .hclk (hclk), // input
.hrst (hrst), // input .hrst (hrst), // input
......
generated/action_decoder.v
View file @ 17ebdc3d
/******************************************************************************* /*******************************************************************************
* Module: action_decoder * Module: action_decoder
* Date:2016-01-19 * Date:2016-01-22
* Author: auto-generated file, see ahci_fsm_sequence.py * Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Decode sequencer code to 1-hot actions * Description: Decode sequencer code to 1-hot actions
*******************************************************************************/ *******************************************************************************/
......
generated/condition_mux.v
View file @ 17ebdc3d
/******************************************************************************* /*******************************************************************************
* Module: condition_mux * Module: condition_mux
* Date:2016-01-19 * Date:2016-01-22
* Author: auto-generated file, see ahci_fsm_sequence.py * Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Select condition * Description: Select condition
*******************************************************************************/ *******************************************************************************/
......
host/oob_ctrl.v
View file @ 17ebdc3d
...@@ -37,49 +37,32 @@ module oob_ctrl #( ...@@ -37,49 +37,32 @@ module oob_ctrl #(
parameter CLK_SPEED_GRADE = 1 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz parameter CLK_SPEED_GRADE = 1 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
) )
( (
// sata clk = usrclk2 input wire clk, // input wire // sata clk = usrclk2
input wire clk, input wire rst, // input wire // reset oob
// reset oob input wire gtx_ready, // input wire // gtx is ready = all resets are done
input wire rst, output wire [11:0] debug, // output[11:0] wire
// gtx is ready = all resets are done input wire rxcominitdet_in,// input wire // oob responses
input wire gtx_ready, input wire rxcomwakedet_in,// input wire // oob responses
output wire [11:0] debug, input wire rxelecidle_in, // input wire // oob responses
// oob responses output wire txcominit, // output wire // oob issues
input wire rxcominitdet_in, output wire txcomwake, // output wire // oob issues
input wire rxcomwakedet_in, output wire txelecidle, // output wire // oob issues
input wire rxelecidle_in, output wire txpcsreset_req, // output wire // partial tx reset
// oob issues input wire recal_tx_done, // input wire
output wire txcominit, output wire rxreset_req, // output wire // rx reset (after rxelecidle -> 0)
output wire txcomwake, input wire rxreset_ack, // input wire
output wire txelecidle, input wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_in, // output[31:0] wire // input data stream (if any data during OOB setting => ignored)
// partial tx reset input wire [DATA_BYTE_WIDTH - 1:0] txcharisk_in, // output[3:0] wire // input data stream (if any data during OOB setting => ignored)
output wire txpcsreset_req, output wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_out, // output[31:0] wire // output data stream to gtx
input wire recal_tx_done, output wire [DATA_BYTE_WIDTH - 1:0] txcharisk_out, // output[3:0] wire // output data stream to gtx
// rx reset (after rxelecidle -> 0) input wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_in, // input[31:0] wire // input data from gtx
output wire rxreset_req, input wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_in, // input[3:0] wire // input data from gtx
input wire rxreset_ack, output wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_out, // output[31:0] wire // bypassed data from gtx
output wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_out, // output[3:0] wire // bypassed data from gtx
// input data stream (if any data during OOB setting => ignored) input wire rxbyteisaligned,// input wire // obvious
input wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_in, output wire phy_ready, // output wire // shows if channel is ready
input wire [DATA_BYTE_WIDTH - 1:0] txcharisk_in, input set_offline, // input wire // electrically idle // From
// output data stream to gtx input comreset_send // input wire // Not possible yet? // From
output wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_out,
output wire [DATA_BYTE_WIDTH - 1:0] txcharisk_out,
// input data from gtx
input wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_in,
input wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_in,
// bypassed data from gtx
output wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_out,
output wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_out,
// obvious
input wire rxbyteisaligned,
// shows if channel is ready
output wire phy_ready,
// From
input set_offline, // electrically idle
input comreset_send // Not possible yet?
); );
// oob sequence needs to be issued // oob sequence needs to be issued
...@@ -145,62 +128,38 @@ oob #( ...@@ -145,62 +128,38 @@ oob #(
) )
oob oob
( (
.debug (debug), .debug (debug), // output [11:0] reg
// sata clk = usrclk2 .clk (clk), // input wire // sata clk = usrclk2
.clk (clk), .rst (rst), // input wire // reset oob
// reset oob .rxcominitdet_in (rxcominitdet_in), // input wire // oob responses
.rst (rst), .rxcomwakedet_in (rxcomwakedet_in), // input wire // oob responses
// oob responses .rxelecidle_in (rxelecidle_in), // input wire // oob responses
.rxcominitdet_in (rxcominitdet_in), .txcominit (txcominit), // output wire // oob issues
.rxcomwakedet_in (rxcomwakedet_in), .txcomwake (txcomwake), // output wire // oob issues
.rxelecidle_in (rxelecidle_in), .txelecidle (txelecidle_inner), // output wire // oob issues
// oob issues .txpcsreset_req (txpcsreset_req), // output wire
.txcominit (txcominit), .recal_tx_done (recal_tx_done), // input wire
.txcomwake (txcomwake), .rxreset_req (rxreset_req), // output wire
.txelecidle (txelecidle_inner), .rxreset_ack (rxreset_ack), // input wire
.txdata_in (txdata_in), // input [31:0] wire // input data stream (if any data during OOB setting => ignored)
.txpcsreset_req (txpcsreset_req), .txcharisk_in (txcharisk_in), // input [3:0] wire // input data stream (if any data during OOB setting => ignored)
.recal_tx_done (recal_tx_done), .txdata_out (txdata_out), // output [31:0] wire // output data stream to gtx
.txcharisk_out (txcharisk_out), // output [3:0] wire// output data stream to gtx
.rxreset_req (rxreset_req), .rxdata_in (rxdata_in), // input [31:0] wire // input data from gtx
.rxreset_ack (rxreset_ack), .rxcharisk_in (rxcharisk_in), // input [3:0] wire // input data from gtx
.rxdata_out (rxdata_out), // output [31:0] wire // bypassed data from gtx
// input data stream (if any data during OOB setting => ignored) .rxcharisk_out (rxcharisk_out), // output [3:0] wire // bypassed data from gtx
.txdata_in (txdata_in), .oob_start (oob_start), // input wire // oob sequence needs to be issued
.txcharisk_in (txcharisk_in), .oob_done (oob_done), // output wire // connection established, all further data is valid
// output data stream to gtx .oob_busy (oob_busy), // output wire // oob can't handle new start request
.txdata_out (txdata_out), .link_up (link_up), // output wire // doc p265, link is established after 3back-to-back non-ALIGNp
.txcharisk_out (txcharisk_out), .link_down (link_down), // output wire
// input data from gtx .cominit_req (cominit_req), // output wire // the device itself sends cominit
.rxdata_in (rxdata_in), .cominit_allow (cominit_allow), // input wire // allow to respond to cominit
.rxcharisk_in (rxcharisk_in), // status information to handle by a control block if any exists
// bypassed data from gtx .oob_incompatible (oob_incompatible),// output wire // incompatible host-device speed grades (host cannot lock to alignp)
.rxdata_out (rxdata_out), .oob_error (oob_error), // output wire // timeout in an unexpected place
.rxcharisk_out (rxcharisk_out), .oob_silence (oob_silence) // output wire // noone responds to our cominits
// oob sequence needs to be issued
.oob_start (oob_start),
// connection established, all further data is valid
.oob_done (oob_done),
// doc p265, link is established after 3back-to-back non-ALIGNp
.link_up (link_up),
.link_down (link_down),
// the device itself sends cominit
.cominit_req (cominit_req),
// allow to respond to cominit
.cominit_allow (cominit_allow),
// status information to handle by a control block if any exists
// incompatible host-device speed grades (host cannot lock to alignp)
.oob_incompatible (oob_incompatible),
// timeout in an unexpected place
.oob_error (oob_error),
// noone responds to our cominits
.oob_silence (oob_silence),
// oob can't handle new start request
.oob_busy (oob_busy)
); );
......
host/sata_phy.v
View file @ 17ebdc3d
...@@ -204,9 +204,10 @@ localparam RXISCANRESET_TIME = 5'h1; ...@@ -204,9 +204,10 @@ localparam RXISCANRESET_TIME = 5'h1;
localparam RXEYERESET_TIME = 7'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + RXCDRFREQRESET_TIME + RXDFELPMRESET_TIME + RXISCANRESET_TIME; localparam RXEYERESET_TIME = 7'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + RXCDRFREQRESET_TIME + RXDFELPMRESET_TIME + RXISCANRESET_TIME;
reg [6:0] rxeyereset_cnt; reg [6:0] rxeyereset_cnt;
assign rxeyereset_done = rxeyereset_cnt == RXEYERESET_TIME; assign rxeyereset_done = rxeyereset_cnt == RXEYERESET_TIME;
always @ (posedge gtrefclk) always @ (posedge gtrefclk) begin
rxeyereset_cnt <= rxreset ? 7'h0 : rxeyereset_done ? rxeyereset_cnt : rxeyereset_cnt + 1'b1; if (rxreset) rxeyereset_cnt <= 0;
else if (!rxeyereset_done) rxeyereset_cnt <= rxeyereset_cnt + 1;
end
/* /*
* Resets * Resets
*/ */
...@@ -221,8 +222,12 @@ reg rxreset_f_rr; ...@@ -221,8 +222,12 @@ reg rxreset_f_rr;
reg txreset_f_rr; reg txreset_f_rr;
always @ (posedge gtrefclk) always @ (posedge gtrefclk)
begin begin
rxreset_f <= ~cplllock | cpllreset | rxreset_oob & gtx_configured; // rxreset_f <= ~cplllock | cpllreset | rxreset_oob & gtx_configured;
txreset_f <= ~cplllock | cpllreset; // txreset_f <= ~cplllock | cpllreset;
rxreset_f <= ~cplllock | cpllreset | ~usrpll_locked | ~sata_reset_done | rxreset_oob & gtx_configured;
txreset_f <= ~cplllock | cpllreset | ~usrpll_locked;
txreset_f_r <= txreset_f; txreset_f_r <= txreset_f;
rxreset_f_r <= rxreset_f; rxreset_f_r <= rxreset_f;
txreset_f_rr <= txreset_f_r; txreset_f_rr <= txreset_f_r;
...@@ -283,8 +288,11 @@ always @ (posedge clk or posedge extrst) ...@@ -283,8 +288,11 @@ always @ (posedge clk or posedge extrst)
assign rst = rst_r; assign rst = rst_r;
always @ (posedge clk or posedge extrst) always @ (posedge clk or posedge extrst)
if (extrst) rst_r <= 1; if (extrst) rst_r <= 1;
else rst_r <= ~|rst_timer ? 1'b0 : sata_reset_done ? 1'b0 : 1'b1; else if (~|rst_timer) rst_r <= 0;
else rst_r <= !sata_reset_done;
// else rst_r <= ~|rst_timer ? 1'b0 : sata_reset_done ? 1'b0 : 1'b1;
assign sata_reset_done = rst_timer == RST_TIMER_LIMIT; assign sata_reset_done = rst_timer == RST_TIMER_LIMIT;
...@@ -389,44 +397,47 @@ gtx_wrap #( ...@@ -389,44 +397,47 @@ gtx_wrap #(
) )
gtx_wrap gtx_wrap
( (
.debug (debug_cnt[11]), .debug (debug_cnt[11]), // output reg
.cplllock (cplllock), .cplllock (cplllock), // output wire
.cplllockdetclk (cplllockdetclk), .cplllockdetclk (cplllockdetclk), // input wire
.cpllreset (cpllreset), .cpllreset (cpllreset), // input wire
.gtrefclk (gtrefclk), .gtrefclk (gtrefclk), // input wire
.drpclk (drpclk), .drpclk (drpclk), // input wire
.rxuserrdy (rxuserrdy), .rxuserrdy (rxuserrdy), // input wire
.txuserrdy (txuserrdy), .txuserrdy (txuserrdy), // input wire
.rxusrclk (rxusrclk), .rxusrclk (rxusrclk), // input wire
.rxusrclk2 (rxusrclk2), .rxusrclk2 (rxusrclk2), // input wire
.rxp (rxp), .rxp (rxp), // input wire
.rxn (rxn), .rxn (rxn), // input wire
.rxbyteisaligned (rxbyteisaligned), .rxbyteisaligned (rxbyteisaligned), // output wire
.rxreset (rxreset), .rxreset (rxreset), // input wire
.rxcomwakedet (rxcomwakedet), .rxcomwakedet (rxcomwakedet), // output wire
.rxcominitdet (rxcominitdet), .rxcominitdet (rxcominitdet), // output wire
.rxelecidle (rxelecidle), .rxelecidle (rxelecidle), // output wire
.rxresetdone (rxresetdone), .rxresetdone (rxresetdone), // output wire
.txreset (txreset), .txreset (txreset), // input wire
.txusrclk (txusrclk), .txusrclk (txusrclk), // input wire
.txusrclk2 (txusrclk2), .txusrclk2 (txusrclk2), // input wire
.txelecidle (txelecidle), .txelecidle (txelecidle), // input wire
.txp (txp), .txp (txp), // output wire
.txn (txn), .txn (txn), // output wire
.txoutclk (txoutclk), .txoutclk (txoutclk), // output wire
.txpcsreset (txpcsreset), .txpcsreset (txpcsreset), // input wire
.txresetdone (txresetdone), .txresetdone (txresetdone), // output wire
.txcominit (txcominit), .txcominit (txcominit), // input wire
.txcomwake (txcomwake), .txcomwake (txcomwake), // input wire
.rxelsfull (rxelsfull), .rxelsfull (rxelsfull), // output wire
.rxelsempty (rxelsempty), .rxelsempty (rxelsempty), // output wire
.txdata (txdata), .txdata (txdata), // input [31:0] wire
.txcharisk (txcharisk), .txcharisk (txcharisk), // input [3:0] wire
.rxdata (rxdata), .rxdata (rxdata), // output[31:0] wire
.rxcharisk (rxcharisk), .rxcharisk (rxcharisk), // output[3:0] wire
.rxdisperr (rxdisperr), .rxdisperr (rxdisperr), // output[3:0] wire
.rxnotintable (rxnotintable) .rxnotintable (rxnotintable) // output[3:0] wire
); );
/* /*
* Interfaces * Interfaces
*/ */
......
tb/tb_ahci.tf 0 → 100644
View file @ 17ebdc3d
/*******************************************************************************
* Module: tb_ahci
* Date: 2015-07-11
* Author: Alexey
* Description: testbench for ahci_top.v
*
* Copyright (c) 2015 Elphel, Inc.
* tb_ahci.tf is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* tb_ahci.tf file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
// global defines
`define IVERILOG
`define SIMULATION
`define OPEN_SOURCE_ONLY
`define PRELOAD_BRAMS
`define CHECKERS_ENABLED
`define use200Mhz 1
/*
* using x393_testbench01.tf style, contains a lot of copy-pasted code from there
*/
`timescale 1ns/1ps
//`include "top.v"
//`include "sata_device.v"
module tb_ahci #(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - partially used
`include "includes/x393_simulation_parameters.vh" // SuppressThisWarning VEditor - partially used
)
(
);
`ifdef IVERILOG
`include "IVERILOG_INCLUDE.v"
`else // IVERILOG
`ifdef CVC
`include "IVERILOG_INCLUDE.v"
`else
parameter fstname = "x393_sata.fst";
`endif // CVC
`endif // IVERILOG
reg [639:0] TESTBENCH_TITLE = "RESET"; // to show human-readable state in the GTKWave
reg [31:0] TESTBENCH_DATA;
reg [11:0] TESTBENCH_ID;
initial #1 $display("HI THERE");
initial
begin
$dumpfile(fstname);
$dumpvars(0, tb_ahci); // SuppressThisWarning VEditor - no idea why here was a warning
$dumpvars(0, glbl); // SuppressThisWarning VEditor - no idea why here was a warning
end
reg EXTCLK_P = 1'b1;
reg EXTCLK_N = 1'b0;
//reg serial_clk = 1'b1;
reg [11:0] ARID_IN_r;
reg [31:0] ARADDR_IN_r;
reg [3:0] ARLEN_IN_r;
reg [1:0] ARSIZE_IN_r;
reg [1:0] ARBURST_IN_r;
reg [11:0] AWID_IN_r;
reg [31:0] AWADDR_IN_r;
reg [3:0] AWLEN_IN_r;
reg [1:0] AWSIZE_IN_r;
reg [1:0] AWBURST_IN_r;
reg [11:0] WID_IN_r;
reg [31:0] WDATA_IN_r;
reg [3:0] WSTRB_IN_r;
reg WLAST_IN_r;
reg DEBUG1, DEBUG2, DEBUG3; // SuppressThisWarnings VEditor not used, just for simulation (inside included tasks)
reg [11:0] GLOBAL_WRITE_ID=0;
reg [11:0] GLOBAL_READ_ID=0;
reg [11:0] LAST_ARID; // last issued ARID
wire [SIMUL_AXI_READ_WIDTH-1:0] SIMUL_AXI_ADDR_W;
//wire SIMUL_AXI_MISMATCH;
// SuppressWarnings VEditor
reg [31:0] SIMUL_AXI_READ;
// SuppressWarnings VEditor
reg [SIMUL_AXI_READ_WIDTH-1:0] SIMUL_AXI_ADDR;
// SuppressWarnings VEditor
reg SIMUL_AXI_FULL; // some data available
wire SIMUL_AXI_EMPTY; // SuppressThisWarnings VEditor not used, just for simulation
reg [31:0] registered_rdata; // here read data from task SuppressThisWarnings VEditor not used, just for simulation
reg CLK;
//wire CLK;
//reg RST;
tri0 RST = glbl.GSR;
reg AR_SET_CMD_r;
wire AR_READY;
reg AW_SET_CMD_r;
wire AW_READY;
reg W_SET_CMD_r;
wire W_READY;
reg [3:0] RD_LAG; // ready signal lag in axi read channel (0 - RDY=1, 1..15 - RDY is asserted N cycles after valid)
reg [3:0] B_LAG; // ready signal lag in axi arete response channel (0 - RDY=1, 1..15 - RDY is asserted N cycles after valid)
// Simulation modules interconnection
wire [31:0] rdata;
wire [11:0] rid;
wire rlast;
wire [1:0] rresp; // SuppressThisWarnings VEditor not used, just for simulation
wire rvalid;
wire rready;
wire rstb=rvalid && rready;
wire [1:0] bresp; // SuppressThisWarnings VEditor not used, just for simulation
wire [11:0] bid; // SuppressThisWarnings VEditor not used, just for simulation
wire bvalid;
wire bready;
integer NUM_WORDS_READ;
integer NUM_WORDS_EXPECTED;
// integer SCANLINE_CUR_X;
// integer SCANLINE_CUR_Y;
wire AXI_RD_EMPTY=NUM_WORDS_READ==NUM_WORDS_EXPECTED; //SuppressThisWarning VEditor : may be unused, just for simulation
assign SIMUL_AXI_EMPTY= ~rvalid && rready && (rid==LAST_ARID); //SuppressThisWarning VEditor : may be unused, just for simulation // use it to wait for?
wire [11:0] #(AXI_TASK_HOLD) ARID_IN = ARID_IN_r;
wire [31:0] #(AXI_TASK_HOLD) ARADDR_IN = ARADDR_IN_r;
wire [3:0] #(AXI_TASK_HOLD) ARLEN_IN = ARLEN_IN_r;
wire [1:0] #(AXI_TASK_HOLD) ARSIZE_IN = ARSIZE_IN_r;
wire [1:0] #(AXI_TASK_HOLD) ARBURST_IN = ARBURST_IN_r;
wire [11:0] #(AXI_TASK_HOLD) AWID_IN = AWID_IN_r;
wire [31:0] #(AXI_TASK_HOLD) AWADDR_IN = AWADDR_IN_r;
wire [3:0] #(AXI_TASK_HOLD) AWLEN_IN = AWLEN_IN_r;
wire [1:0] #(AXI_TASK_HOLD) AWSIZE_IN = AWSIZE_IN_r;
wire [1:0] #(AXI_TASK_HOLD) AWBURST_IN = AWBURST_IN_r;
wire [11:0] #(AXI_TASK_HOLD) WID_IN = WID_IN_r;
wire [31:0] #(AXI_TASK_HOLD) WDATA_IN = WDATA_IN_r;
wire [ 3:0] #(AXI_TASK_HOLD) WSTRB_IN = WSTRB_IN_r;
wire #(AXI_TASK_HOLD) WLAST_IN = WLAST_IN_r;
wire #(AXI_TASK_HOLD) AR_SET_CMD = AR_SET_CMD_r;
wire #(AXI_TASK_HOLD) AW_SET_CMD = AW_SET_CMD_r;
wire #(AXI_TASK_HOLD) W_SET_CMD = W_SET_CMD_r;
/*
* connect axi ports to the dut
*/
assign dut.ps7_i.FCLKCLK= {4{CLK}};
assign dut.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST};
// Read data
assign rdata= dut.ps7_i.MAXIGP1RDATA;
assign rvalid= dut.ps7_i.MAXIGP1RVALID;
assign dut.ps7_i.MAXIGP1RREADY= rready;
assign rid= dut.ps7_i.MAXIGP1RID;
assign rlast= dut.ps7_i.MAXIGP1RLAST;
assign rresp= dut.ps7_i.MAXIGP1RRESP;
// Write response
assign bvalid= dut.ps7_i.MAXIGP1BVALID;
assign dut.ps7_i.MAXIGP1BREADY= bready;
assign bid= dut.ps7_i.MAXIGP1BID;
assign bresp= dut.ps7_i.MAXIGP1BRESP;
// Simulation modules
simul_axi_master_rdaddr
#(
.ID_WIDTH (12),
.ADDRESS_WIDTH (32),
.LATENCY (AXI_RDADDR_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH (8), // maximal number of commands in FIFO
.DATA_DELAY (3.5),
.VALID_DELAY (4.0)
) simul_axi_master_rdaddr_i (
.clk (CLK), // input
.reset (RST), // input
.arid_in (ARID_IN[11:0]), // input[11:0]
.araddr_in (ARADDR_IN[31:0]), // input[31:0]
.arlen_in (ARLEN_IN[3:0]), // input[3:0]
.arsize_in (ARSIZE_IN[1:0]), // input[1:0]
.arburst_in (ARBURST_IN[1:0]), // input[1:0]
.arcache_in (4'b0), // input[3:0]
.arprot_in (3'b0), // input[2:0]// .arprot_in(2'b0),
.arid (dut.ps7_i.MAXIGP1ARID[11:0]), // output[11:0]
.araddr (dut.ps7_i.MAXIGP1ARADDR[31:0]), // output[31:0]
.arlen (dut.ps7_i.MAXIGP1ARLEN[3:0]), // output[3:0]
.arsize (dut.ps7_i.MAXIGP1ARSIZE[1:0]), // output[1:0]
.arburst (dut.ps7_i.MAXIGP1ARBURST[1:0]), // output[1:0]
.arcache (dut.ps7_i.MAXIGP1ARCACHE[3:0]), // output3:0]
.arprot (dut.ps7_i.MAXIGP1ARPROT[2:0]), // output[2:0]
.arvalid (dut.ps7_i.MAXIGP1ARVALID), // output
.arready (dut.ps7_i.MAXIGP1ARREADY), // input
.set_cmd (AR_SET_CMD), // input// latch all other input data at posedge of clock
.ready (AR_READY) // command/data FIFO can accept command
);
simul_axi_master_wraddr
#(
.ID_WIDTH (12),
.ADDRESS_WIDTH (32),
.LATENCY (AXI_WRADDR_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH (8), // maximal number of commands in FIFO
.DATA_DELAY (3.5),
.VALID_DELAY (4.0)
) simul_axi_master_wraddr_i (
.clk (CLK), // input
.reset (RST), // input
.awid_in (AWID_IN[11:0]), // input[11:0]
.awaddr_in (AWADDR_IN[31:0]), // input[31:0]
.awlen_in (AWLEN_IN[3:0]), // input[3:0]
.awsize_in (AWSIZE_IN[1:0]), // input[2:0]
.awburst_in (AWBURST_IN[1:0]), // input[1:0]
.awcache_in (4'b0), // input[1:0]
.awprot_in (3'b0), // input[2:0]//.awprot_in(2'b0),
.awid (dut.ps7_i.MAXIGP1AWID[11:0]), // output[11:0]
.awaddr (dut.ps7_i.MAXIGP1AWADDR[31:0]), // output[31:0]
.awlen (dut.ps7_i.MAXIGP1AWLEN[3:0]), // output[31:0]
.awsize (dut.ps7_i.MAXIGP1AWSIZE[1:0]), // output[2:0]
.awburst (dut.ps7_i.MAXIGP1AWBURST[1:0]), // output[1:0]
.awcache (dut.ps7_i.MAXIGP1AWCACHE[3:0]), // output[3:0]
.awprot (dut.ps7_i.MAXIGP1AWPROT[2:0]), // output[2:0]
.awvalid (dut.ps7_i.MAXIGP1AWVALID), // output
.awready (dut.ps7_i.MAXIGP1AWREADY), // input
.set_cmd (AW_SET_CMD), // input // latch all other input data at posedge of clock
.ready (AW_READY) // output// command/data FIFO can accept command
);
simul_axi_master_wdata #(
.ID_WIDTH (12),
.DATA_WIDTH (32),
.WSTB_WIDTH (4),
.LATENCY (AXI_WRDATA_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH (8), // maximal number of commands in FIFO
.DATA_DELAY(3.2),
.VALID_DELAY(3.6)
) simul_axi_master_wdata_i (
.clk (CLK), // input
.reset (RST), // input
.wid_in (WID_IN[11:0]), // input[11:0]
.wdata_in (WDATA_IN[31:0]), // input[31:0]
.wstrb_in (WSTRB_IN[3:0]), // input[3:0]
.wlast_in (WLAST_IN), // input
.wid (dut.ps7_i.MAXIGP1WID[11:0]), // output[11:0]
.wdata (dut.ps7_i.MAXIGP1WDATA[31:0]), // output[31:0]
.wstrb (dut.ps7_i.MAXIGP1WSTRB[3:0]), // output[3:0]
.wlast (dut.ps7_i.MAXIGP1WLAST), // output
.wvalid (dut.ps7_i.MAXIGP1WVALID), // output
.wready (dut.ps7_i.MAXIGP1WREADY), // input
.set_cmd (W_SET_CMD), // input // latch all other input data at posedge of clock
.ready (W_READY) // output // command/data FIFO can accept command
);
simul_axi_read #(
.ADDRESS_WIDTH (SIMUL_AXI_READ_WIDTH)
) simul_axi_read_i(
.clk (CLK), // input
.reset (RST), // input
.last (rlast), // input
.data_stb (rstb), // input
.raddr (ARADDR_IN[SIMUL_AXI_READ_WIDTH+1:2]), // input[9:0]
.rlen (ARLEN_IN), // input[3:0]
.rcmd (AR_SET_CMD), // input
.addr_out (SIMUL_AXI_ADDR_W[SIMUL_AXI_READ_WIDTH-1:0]), // output[9:0]
.burst (), // output // burst in progress - just debug
.err_out ()); // output reg // data last does not match predicted or FIFO over/under run - just debug
simul_axi_slow_ready simul_axi_slow_ready_read_i(
.clk(CLK),
.reset(RST), //input reset,
.delay(RD_LAG), //input [3:0] delay,
.valid(rvalid), // input valid,
.ready(rready) //output ready
);
simul_axi_slow_ready simul_axi_slow_ready_write_resp_i(
.clk(CLK),
.reset(RST), //input reset,
.delay(B_LAG), //input [3:0] delay,
.valid(bvalid), // input ADDRESS_NUMBER+2:0 valid,
.ready(bready) //output ready
);
// device-under-test instance
wire rxn;
wire rxp;
wire txn;
wire txp;
wire device_rst;
top dut(
.RXN (rxn),
.RXP (rxp),
.TXN (txn),
.TXP (txp),
.EXTCLK_P (EXTCLK_P),
.EXTCLK_N (EXTCLK_N)
);
assign device_rst = dut.axi_rst;
sata_device dev(
.rst (device_rst),
.RXN (txn),
.RXP (txp),
.TXN (rxn),
.TXP (rxp),
.EXTCLK_P (EXTCLK_P),
.EXTCLK_N (EXTCLK_N)
);
// SAXI HP interface
// axi_hp simulation signals
wire HCLK;
wire [31:0] afi_sim_rd_address; // output[31:0]
wire [ 5:0] afi_sim_rid; // output[5:0] SuppressThisWarning VEditor - not used - just view
// reg afi_sim_rd_valid; // input
wire afi_sim_rd_valid; // input
wire afi_sim_rd_ready; // output
// reg [63:0] afi_sim_rd_data; // input[63:0]
wire [63:0] afi_sim_rd_data; // input[63:0]
wire [ 2:0] afi_sim_rd_cap; // output[2:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] afi_sim_rd_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view
wire [ 1:0] afi_sim_rd_resp; // input[1:0]
// reg [ 1:0] afi_sim_rd_resp; // input[1:0]
wire [31:0] afi_sim_wr_address; // output[31:0] SuppressThisWarning VEditor - not used - just view
wire [ 5:0] afi_sim_wid; // output[5:0] SuppressThisWarning VEditor - not used - just view
wire afi_sim_wr_valid; // output
wire afi_sim_wr_ready; // input
// reg afi_sim_wr_ready; // input
wire [63:0] afi_sim_wr_data; // output[63:0] SuppressThisWarning VEditor - not used - just view
wire [ 7:0] afi_sim_wr_stb; // output[7:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] afi_sim_bresp_latency; // input[3:0]
// reg [ 3:0] afi_sim_bresp_latency; // input[3:0]
wire [ 2:0] afi_sim_wr_cap; // output[2:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] afi_sim_wr_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view
assign HCLK = dut.ps7_i.SAXIHP3ACLK; // shortcut name
// afi loopback
assign #1 afi_sim_rd_data= afi_sim_rd_ready?{2'h0,afi_sim_rd_address[31:3],1'h1, 2'h0,afi_sim_rd_address[31:3],1'h0}:64'bx;
assign #1 afi_sim_rd_valid = afi_sim_rd_ready;
assign #1 afi_sim_rd_resp = afi_sim_rd_ready?2'b0:2'bx;
assign #1 afi_sim_wr_ready = afi_sim_wr_valid;
assign #1 afi_sim_bresp_latency=4'h5;
// axi_hp register access
// PS memory mapped registers to read/write over a separate simulation bus running at HCLK, no waits
reg [31:0] PS_REG_ADDR;
reg PS_REG_WR;
reg PS_REG_RD;
reg PS_REG_WR1;
reg PS_REG_RD1;
reg [31:0] PS_REG_DIN;
wire [31:0] PS_REG_DOUT;
wire [31:0] PS_REG_DOUT1;
reg [31:0] PS_RDATA; // SuppressThisWarning VEditor - not used - just view
/*
reg [31:0] afi_reg_addr;
reg afi_reg_wr;
reg afi_reg_rd;
reg [31:0] afi_reg_din;
wire [31:0] afi_reg_dout;
reg [31:0] AFI_REG_RD; // SuppressThisWarning VEditor - not used - just view
*/
initial begin
PS_REG_ADDR <= 'bx;
PS_REG_WR <= 0;
PS_REG_RD <= 0;
PS_REG_WR1 <= 0;
PS_REG_RD1 <= 0;
PS_REG_DIN <= 'bx;
PS_RDATA <= 'bx;
end
always @ (posedge HCLK) begin
if (PS_REG_RD) PS_RDATA <= PS_REG_DOUT;
else if (PS_REG_RD1) PS_RDATA <= PS_REG_DOUT1;
end
simul_axi_hp_rd #(
.HP_PORT(3)
) simul_axi_hp_rd_i (
.rst (RST), // input
.aclk (dut.ps7_i.SAXIHP3ACLK), // input
.aresetn (), // output
.araddr (dut.ps7_i.SAXIHP3ARADDR[31:0]), // input[31:0]
.arvalid (dut.ps7_i.SAXIHP3ARVALID), // input
.arready (dut.ps7_i.SAXIHP3ARREADY), // output
.arid (dut.ps7_i.SAXIHP3ARID), // input[5:0]
.arlock (dut.ps7_i.SAXIHP3ARLOCK), // input[1:0]
.arcache (dut.ps7_i.SAXIHP3ARCACHE), // input[3:0]
.arprot (dut.ps7_i.SAXIHP3ARPROT), // input[2:0]
.arlen (dut.ps7_i.SAXIHP3ARLEN), // input[3:0]
.arsize (dut.ps7_i.SAXIHP3ARSIZE), // input[2:0]
.arburst (dut.ps7_i.SAXIHP3ARBURST), // input[1:0]
.arqos (dut.ps7_i.SAXIHP3ARQOS), // input[3:0]
.rdata (dut.ps7_i.SAXIHP3RDATA), // output[63:0]
.rvalid (dut.ps7_i.SAXIHP3RVALID), // output
.rready (dut.ps7_i.SAXIHP3RREADY), // input
.rid (dut.ps7_i.SAXIHP3RID), // output[5:0]
.rlast (dut.ps7_i.SAXIHP3RLAST), // output
.rresp (dut.ps7_i.SAXIHP3RRESP), // output[1:0]
.rcount (dut.ps7_i.SAXIHP3RCOUNT), // output[7:0]
.racount (dut.ps7_i.SAXIHP3RACOUNT), // output[2:0]
.rdissuecap1en (dut.ps7_i.SAXIHP3RDISSUECAP1EN), // input
.sim_rd_address (afi_sim_rd_address), // output[31:0]
.sim_rid (afi_sim_rid), // output[5:0]
.sim_rd_valid (afi_sim_rd_valid), // input
.sim_rd_ready (afi_sim_rd_ready), // output
.sim_rd_data (afi_sim_rd_data), // input[63:0]
.sim_rd_cap (afi_sim_rd_cap), // output[2:0]
.sim_rd_qos (afi_sim_rd_qos), // output[3:0]
.sim_rd_resp (afi_sim_rd_resp), // input[1:0]
.reg_addr (PS_REG_ADDR), // input[31:0]
.reg_wr (PS_REG_WR), // input
.reg_rd (PS_REG_RD), // input
.reg_din (PS_REG_DIN), // input[31:0]
.reg_dout (PS_REG_DOUT) // output[31:0]
);
simul_axi_hp_wr #(
.HP_PORT(3)
) simul_axi_hp_wr_i (
.rst (RST), // input
.aclk (dut.ps7_i.SAXIHP3ACLK), // input
.aresetn (), // output
.awaddr (dut.ps7_i.SAXIHP3AWADDR), // input[31:0]
.awvalid (dut.ps7_i.SAXIHP3AWVALID), // input
.awready (dut.ps7_i.SAXIHP3AWREADY), // output
.awid (dut.ps7_i.SAXIHP3AWID), // input[5:0]
.awlock (dut.ps7_i.SAXIHP3AWLOCK), // input[1:0]
.awcache (dut.ps7_i.SAXIHP3AWCACHE), // input[3:0]
.awprot (dut.ps7_i.SAXIHP3AWPROT), // input[2:0]
.awlen (dut.ps7_i.SAXIHP3AWLEN), // input[3:0]
.awsize (dut.ps7_i.SAXIHP3AWSIZE), // input[2:0]
.awburst (dut.ps7_i.SAXIHP3AWBURST), // input[1:0]
.awqos (dut.ps7_i.SAXIHP3AWQOS), // input[3:0]
.wdata (dut.ps7_i.SAXIHP3WDATA), // input[63:0]
.wvalid (dut.ps7_i.SAXIHP3WVALID), // input
.wready (dut.ps7_i.SAXIHP3WREADY), // output
.wid (dut.ps7_i.SAXIHP3WID), // input[5:0]
.wlast (dut.ps7_i.SAXIHP3WLAST), // input
.wstrb (dut.ps7_i.SAXIHP3WSTRB), // input[7:0]
.bvalid (dut.ps7_i.SAXIHP3BVALID), // output
.bready (dut.ps7_i.SAXIHP3BREADY), // input
.bid (dut.ps7_i.SAXIHP3BID), // output[5:0]
.bresp (dut.ps7_i.SAXIHP3BRESP), // output[1:0]
.wcount (dut.ps7_i.SAXIHP3WCOUNT), // output[7:0]
.wacount (dut.ps7_i.SAXIHP3WACOUNT), // output[5:0]
.wrissuecap1en (dut.ps7_i.SAXIHP3WRISSUECAP1EN), // input
.sim_wr_address (afi_sim_wr_address), // output[31:0]
.sim_wid (afi_sim_wid), // output[5:0]
.sim_wr_valid (afi_sim_wr_valid), // output
.sim_wr_ready (afi_sim_wr_ready), // input
.sim_wr_data (afi_sim_wr_data), // output[63:0]
.sim_wr_stb (afi_sim_wr_stb), // output[7:0]
.sim_bresp_latency(afi_sim_bresp_latency), // input[3:0]
.sim_wr_cap (afi_sim_wr_cap), // output[2:0]
.sim_wr_qos (afi_sim_wr_qos), // output[3:0]
.reg_addr (PS_REG_ADDR), // input[31:0]
.reg_wr (PS_REG_WR1), // input
.reg_rd (PS_REG_RD1), // input
.reg_din (PS_REG_DIN), // input[31:0]
.reg_dout (PS_REG_DOUT1) // output[31:0]
);
// wire [ 3:0] SIMUL_ADD_ADDR;
always @ (posedge CLK) begin
if (RST) SIMUL_AXI_FULL <=0;
else if (rstb) SIMUL_AXI_FULL <=1;
if (RST) begin
NUM_WORDS_READ <= 0;
end else if (rstb) begin
NUM_WORDS_READ <= NUM_WORDS_READ + 1;
end
if (rstb) begin
SIMUL_AXI_ADDR <= SIMUL_AXI_ADDR_W;
SIMUL_AXI_READ <= rdata;
`ifdef DEBUG_RD_DATA
$display (" Read data (addr:data): 0x%x:0x%x @%t",SIMUL_AXI_ADDR_W,rdata,$time);
`endif
end
end
//tasks
`include "includes/x393_tasks01.vh" // SuppressThisWarning VEditor - partially used
//`include "includes/x393_tasks_afi.vh" // SuppressThisWarning VEditor - partially used
/*
* Monitor maxi bus read data.
* No burst assumed, so we're interested only in 3 signals to monitor on.
* Every time something is on a bus, data and id of a transaction are pushed into a fifo
* Fifo can be read by maxiMonitorPop function. Check if fifo is empty by calling maxiMonitorIsEmpty()
*/
// path to these signals
wire [31:0] maxi_monitor_rdata;
wire [11:0] maxi_monitor_rid;
wire maxi_monitor_rvalid;
assign maxi_monitor_rdata = dut.ps7_i.MAXIGP1RDATA;
assign maxi_monitor_rid = dut.ps7_i.MAXIGP1RID;
assign maxi_monitor_rvalid = dut.ps7_i.MAXIGP1RVALID;
localparam maxi_monitor_fifo_size = 2049;
reg [43:0] maxi_monitor_fifo [maxi_monitor_fifo_size - 1:0];
integer maxi_monitor_raddr = 0;
integer maxi_monitor_waddr = 0;
reg maxi_monitor_fifo_empty = 1;
function maxiMonitorIsEmpty( // SuppressThisWarning VEditor - it's ok
input dummy // SuppressThisWarning VEditor - it's ok
);
begin
maxiMonitorIsEmpty = maxi_monitor_fifo_empty;
end
endfunction
task maxiMonitorPop;
output reg [31:0] data;
output integer id;
begin
if ((maxi_monitor_waddr == maxi_monitor_raddr) && maxi_monitor_fifo_empty) begin
$display("[Testbench] maxiMonitorPop: Trying to pop from an empty fifo");
$finish;
end
data = maxi_monitor_fifo[maxi_monitor_raddr][31:0]; // RDATA
id = maxi_monitor_fifo[maxi_monitor_raddr][43:32]; // RID // SuppressThisWarning VEditor - it's ok
maxi_monitor_raddr = (maxi_monitor_raddr + 1) % maxi_monitor_fifo_size;
if (maxi_monitor_waddr == maxi_monitor_raddr) begin
maxi_monitor_fifo_empty = 1;
end
end
endtask
task maxiMonitorPush;
input [31:0] data;
input [11:0] id;
begin
if (maxi_monitor_raddr == (maxi_monitor_waddr + 1)) begin
$display("[Testbench] maxiMonitorPush: trying to push to a full fifo");
TESTBENCH_TITLE = "trying to push to a full fifo";
$display("[Testbench] maxiMonitorPush %s = %h, id = %h @%t", TESTBENCH_TITLE, $time);
$finish;
end
maxi_monitor_fifo[maxi_monitor_waddr][31:0] = data;
maxi_monitor_fifo[maxi_monitor_waddr][43:32] = id;
maxi_monitor_fifo_empty = 1'b0;
// $display("[Testbench] MAXI: Got data = %h, id = %h", data, id);
TESTBENCH_TITLE = "Got data";
TESTBENCH_DATA = data;
TESTBENCH_ID = id;
$display("[Testbench] MAXI %s = %h, id = %h @%t", TESTBENCH_TITLE, TESTBENCH_DATA, TESTBENCH_ID, $time);
//[Testbench] MAXI: %
maxi_monitor_waddr = (maxi_monitor_waddr + 1) % maxi_monitor_fifo_size;
end
endtask
initial forever @ (posedge CLK) begin
if (~RST) begin
if (maxi_monitor_rvalid) begin
maxiMonitorPush(maxi_monitor_rdata, maxi_monitor_rid);
end
end
end
always #3.333 begin
EXTCLK_P = ~EXTCLK_P;
EXTCLK_N = ~EXTCLK_N;
end
/*
// MAXI clock
always #10
begin
CLK = ~CLK;
end
*/
initial CLK = 0;
always #(CLKIN_PERIOD/2) CLK = ~CLK;
//always #(10) CLK = ~CLK;
// Simulation
`include "includes/ahci_localparams.vh" // SuppressThisWarning VEditor - many unused defines
localparam MAXIGP1 = 32'h80000000; // Start of the MAXIGP1 address range (use ahci_localparams.vh offsets)
task maxigp1_write_single; // address in bytes, not words
input [31:0] address;
input [31:0] data;
begin
axi_write_single(address + MAXIGP1, data);
end
endtask
task maxigp1_read;
input [31:0] address;
begin
read_and_wait (address + MAXIGP1);
end
endtask
task maxigp1_print;
input [31:0] address;
begin
read_and_wait (address + MAXIGP1);
$display ("%x -> %x @ %t",address + MAXIGP1, registered_rdata,$time);
end
endtask
initial begin
wait (!RST);
//reg [639:0] TESTBENCH_TITLE = "RESET"; // to show human-readable state in the GTKWave
TESTBENCH_TITLE = "NO_RESET";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
repeat (10) begin
@ (posedge CLK);
end
axi_set_rd_lag(0);
axi_set_b_lag(0);
maxigp1_print(PCI_Header__CAP__CAP__ADDR);
maxigp1_print(GHC__PI__PI__ADDR);
maxigp1_print(HBA_PORT__PxCMD__ICC__ADDR);
// $finish;
end
initial begin
// #30000;
#50000;
// #250000;
// #60000;
$display("finish testbench 2");
$finish;
end
// testing itself
//`include "test_top.v" // S uppressThisWarning VEditor - to avoid strange warnings
endmodule
//`include "x393/glbl.v" // SuppressThisWarning VEditor - duplicate module
tb/tb_top.v
View file @ 17ebdc3d
...@@ -88,12 +88,12 @@ reg EXTCLK_N = 1'b0; ...@@ -88,12 +88,12 @@ reg EXTCLK_N = 1'b0;
reg [11:0] ARID_IN_r; reg [11:0] ARID_IN_r;
reg [31:0] ARADDR_IN_r; reg [31:0] ARADDR_IN_r;
reg [3:0] ARLEN_IN_r; reg [3:0] ARLEN_IN_r;
reg [2:0] ARSIZE_IN_r; reg [1:0] ARSIZE_IN_r;
reg [1:0] ARBURST_IN_r; reg [1:0] ARBURST_IN_r;
reg [11:0] AWID_IN_r; reg [11:0] AWID_IN_r;
reg [31:0] AWADDR_IN_r; reg [31:0] AWADDR_IN_r;
reg [3:0] AWLEN_IN_r; reg [3:0] AWLEN_IN_r;
reg [2:0] AWSIZE_IN_r; reg [1:0] AWSIZE_IN_r;
reg [1:0] AWBURST_IN_r; reg [1:0] AWBURST_IN_r;
reg [11:0] WID_IN_r; reg [11:0] WID_IN_r;
...@@ -135,7 +135,7 @@ reg [3:0] B_LAG; // ready signal lag in axi arete response channel (0 - RDY=1 ...@@ -135,7 +135,7 @@ reg [3:0] B_LAG; // ready signal lag in axi arete response channel (0 - RDY=1
wire [11:0] arid; wire [11:0] arid;
wire [31:0] araddr; wire [31:0] araddr;
wire [3:0] arlen; wire [3:0] arlen;
wire [2:0] arsize; wire [1:0] arsize;
wire [1:0] arburst; wire [1:0] arburst;
// SuppressWarnings VEditor : assigned in $readmem(14) system task // SuppressWarnings VEditor : assigned in $readmem(14) system task
wire [3:0] arcache; wire [3:0] arcache;
...@@ -147,7 +147,7 @@ wire arready; ...@@ -147,7 +147,7 @@ wire arready;
wire [11:0] awid; wire [11:0] awid;
wire [31:0] awaddr; wire [31:0] awaddr;
wire [3:0] awlen; wire [3:0] awlen;
wire [2:0] awsize; wire [1:0] awsize;
wire [1:0] awburst; wire [1:0] awburst;
// SuppressWarnings VEditor : assigned in $readmem() system task // SuppressWarnings VEditor : assigned in $readmem() system task
wire [3:0] awcache; wire [3:0] awcache;
...@@ -190,12 +190,12 @@ assign SIMUL_AXI_EMPTY= ~rvalid && rready && (rid==LAST_ARID); //SuppressThisWa ...@@ -190,12 +190,12 @@ assign SIMUL_AXI_EMPTY= ~rvalid && rready && (rid==LAST_ARID); //SuppressThisWa
wire [11:0] #(AXI_TASK_HOLD) ARID_IN = ARID_IN_r; wire [11:0] #(AXI_TASK_HOLD) ARID_IN = ARID_IN_r;
wire [31:0] #(AXI_TASK_HOLD) ARADDR_IN = ARADDR_IN_r; wire [31:0] #(AXI_TASK_HOLD) ARADDR_IN = ARADDR_IN_r;
wire [3:0] #(AXI_TASK_HOLD) ARLEN_IN = ARLEN_IN_r; wire [3:0] #(AXI_TASK_HOLD) ARLEN_IN = ARLEN_IN_r;
wire [2:0] #(AXI_TASK_HOLD) ARSIZE_IN = ARSIZE_IN_r; wire [1:0] #(AXI_TASK_HOLD) ARSIZE_IN = ARSIZE_IN_r;
wire [1:0] #(AXI_TASK_HOLD) ARBURST_IN = ARBURST_IN_r; wire [1:0] #(AXI_TASK_HOLD) ARBURST_IN = ARBURST_IN_r;
wire [11:0] #(AXI_TASK_HOLD) AWID_IN = AWID_IN_r; wire [11:0] #(AXI_TASK_HOLD) AWID_IN = AWID_IN_r;
wire [31:0] #(AXI_TASK_HOLD) AWADDR_IN = AWADDR_IN_r; wire [31:0] #(AXI_TASK_HOLD) AWADDR_IN = AWADDR_IN_r;
wire [3:0] #(AXI_TASK_HOLD) AWLEN_IN = AWLEN_IN_r; wire [3:0] #(AXI_TASK_HOLD) AWLEN_IN = AWLEN_IN_r;
wire [2:0] #(AXI_TASK_HOLD) AWSIZE_IN = AWSIZE_IN_r; wire [1:0] #(AXI_TASK_HOLD) AWSIZE_IN = AWSIZE_IN_r;
wire [1:0] #(AXI_TASK_HOLD) AWBURST_IN = AWBURST_IN_r; wire [1:0] #(AXI_TASK_HOLD) AWBURST_IN = AWBURST_IN_r;
wire [11:0] #(AXI_TASK_HOLD) WID_IN = WID_IN_r; wire [11:0] #(AXI_TASK_HOLD) WID_IN = WID_IN_r;
wire [31:0] #(AXI_TASK_HOLD) WDATA_IN = WDATA_IN_r; wire [31:0] #(AXI_TASK_HOLD) WDATA_IN = WDATA_IN_r;
...@@ -277,14 +277,14 @@ simul_axi_master_rdaddr ...@@ -277,14 +277,14 @@ simul_axi_master_rdaddr
.arid_in(ARID_IN[11:0]), .arid_in(ARID_IN[11:0]),
.araddr_in(ARADDR_IN[31:0]), .araddr_in(ARADDR_IN[31:0]),
.arlen_in(ARLEN_IN[3:0]), .arlen_in(ARLEN_IN[3:0]),
.arsize_in(ARSIZE_IN[2:0]), .arsize_in(ARSIZE_IN[1:0]),
.arburst_in(ARBURST_IN[1:0]), .arburst_in(ARBURST_IN[1:0]),
.arcache_in(4'b0), .arcache_in(4'b0),
.arprot_in(3'b0), // .arprot_in(2'b0), .arprot_in(3'b0), // .arprot_in(2'b0),
.arid(arid[11:0]), .arid(arid[11:0]),
.araddr(araddr[31:0]), .araddr(araddr[31:0]),
.arlen(arlen[3:0]), .arlen(arlen[3:0]),
.arsize(arsize[2:0]), .arsize(arsize[1:0]),
.arburst(arburst[1:0]), .arburst(arburst[1:0]),
.arcache(arcache[3:0]), .arcache(arcache[3:0]),
.arprot(arprot[2:0]), .arprot(arprot[2:0]),
...@@ -308,14 +308,14 @@ simul_axi_master_wraddr ...@@ -308,14 +308,14 @@ simul_axi_master_wraddr
.awid_in(AWID_IN[11:0]), .awid_in(AWID_IN[11:0]),
.awaddr_in(AWADDR_IN[31:0]), .awaddr_in(AWADDR_IN[31:0]),
.awlen_in(AWLEN_IN[3:0]), .awlen_in(AWLEN_IN[3:0]),
.awsize_in(AWSIZE_IN[2:0]), .awsize_in(AWSIZE_IN[1:0]),
.awburst_in(AWBURST_IN[1:0]), .awburst_in(AWBURST_IN[1:0]),
.awcache_in(4'b0), .awcache_in(4'b0),
.awprot_in(3'b0), //.awprot_in(2'b0), .awprot_in(3'b0), //.awprot_in(2'b0),
.awid(awid[11:0]), .awid(awid[11:0]),
.awaddr(awaddr[31:0]), .awaddr(awaddr[31:0]),
.awlen(awlen[3:0]), .awlen(awlen[3:0]),
.awsize(awsize[2:0]), .awsize(awsize[1:0]),
.awburst(awburst[1:0]), .awburst(awburst[1:0]),
.awcache(awcache[3:0]), .awcache(awcache[3:0]),
.awprot(awprot[2:0]), .awprot(awprot[2:0]),
......
tb_ahci_01.sav 0 → 100644
View file @ 17ebdc3d
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sat Jan 23 07:05:52 2016
[*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160122235411900.fst"
[dumpfile_mtime] "Sat Jan 23 06:55:08 2016"
[dumpfile_size] 6269364
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 0
[size] 1823 1173
[pos] 1942 0
*-21.079729 6065536 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci.
[treeopen] tb_ahci.dut.
[treeopen] tb_ahci.dut.axi_hp_clk_i.
[treeopen] tb_ahci.dut.sata_top.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.
[sst_width] 402
[signals_width] 245
[sst_expanded] 1
[sst_vpaned_height] 621
@820
tb_ahci.TESTBENCH_TITLE[639:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0]
@28
tb_ahci.CLK
tb_ahci.RST
@22
tb_ahci.read_and_wait.address[31:0]
@28
tb_ahci.dut.TXN
tb_ahci.dut.RXN
@800200
-axi_ahci_regs
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.aclk
@c00200
-axibram_read
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.araddr[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.arvalid
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.arready
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.bram_raddr[9:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.dev_ready
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.start_burst
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.bram_ren
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.bram_regen
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.bram_rdata[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.rdata[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.rready
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.rvalid
tb_ahci.dut.sata_top.RREADY
tb_ahci.dut.ps7_i.MAXIGP1RREADY
tb_ahci.dut.ps7_i.MAXIGP1RVALID
tb_ahci.rready
tb_ahci.rvalid
tb_ahci.rstb
@200
-
@1401200
-axibram_read
@1000200
-axi_ahci_regs
@800200
-ahci_sata_layers
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.exrst
tb_ahci.dut.sata_top.ahci_sata_layers_i.reliable_clk
tb_ahci.dut.sata_top.ahci_sata_layers_i.extclk_n
tb_ahci.dut.sata_top.ahci_sata_layers_i.rst
tb_ahci.dut.sata_top.ahci_sata_layers_i.clk
@200
-
@1000200
-ahci_sata_layers
@800200
-ahci_top
@28
tb_ahci.dut.sata_top.ahci_top_i.port_arst
tb_ahci.dut.sata_top.ahci_top_i.hba_arst
tb_ahci.dut.sata_top.ahci_top_i.phy_ready[1:0]
@1000200
-ahci_top
@800200
-axi_ahci_regs
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_reset_cntr[8:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_arst
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.port_arst
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.port_arst_any
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.wait_first_access
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.any_access
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.set_port_rst
@1000200
-axi_ahci_regs
@800200
-ahci_fsm
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
@1401200
-group_end
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_preload
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_actions
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_transitions[1:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_next
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_wait_act_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_last_act_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.cond_met_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pre_jump_w
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_jump_addr[9:0]
@800028
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0]
@1001200
-group_end
@200
-
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pfsm_started
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pxci0_clear
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.clear_bsy_set_drq
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.set_sts_7f
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.set_update_sig
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.comreset_send
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.set_sts_80
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.ssts_det_dnp
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.sirq_PC
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.serr_diag_X
@200
-
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fis_first_vld
@200
-
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pcmd_st_cleared
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.cominit_got
@c00028
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
@1000200
-ahci_fsm
@800200
-link
@200
-
@1000200
-link
@800200
-phy
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.comreset_send
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtrefclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txoutclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.usrclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.usrclk2
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.usrpll_locked
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.cpllreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.cplllock
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxreset_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxreset_oob
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxreset_oob_stop
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxreset_oob
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_configured
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxreset_f
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtrefclk
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxeyereset_cnt[6:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxeyereset_done
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.clk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rst_r
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.sata_reset_done
@200
-
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.usrpll_locked
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.cplllock
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.cpllreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxuserrdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txuserrdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxresetdone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txresetdone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txreset
@1000200
-phy
@800200
-oob_ctrl
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.gtx_ready
@200
-
@800200
-oob
@200
-
@1000200
-oob
-oob_ctrl
@800200
-gtx
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cpllreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cplllock
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cplllockdetclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txelecidle_gtx
@200
-
@1000200
-gtx
[pattern_trace] 1
[pattern_trace] 0
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