started simulation (17ebdc3d) · Commits · Elphel / x393_sata

.settings/com.elphel.vdt.iverilog.prefs

+3 −2

Original line number	Diff line number	Diff line
		com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_122_IVerilogOther<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_119_GTKWaveSavFile<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->iverilog_122_GrepFindErrWarn<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->
		com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_122_IVerilogOther<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_119_GTKWaveSavFile<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->iverilog_122_GrepFindErrWarn<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->iverilog_95_IcarusTopFile<-@\#\#@->
		eclipse.preferences.version=1
		iverilog_101_TopModulesOther=glbl<-@\#\#@->
		iverilog_102_TopModulesOther=glbl<-@\#\#@->
		@@ -15,7 +15,7 @@ iverilog_113_SaveLogsPreprocessor=true
		iverilog_114_SaveLogsSimulator=true
		iverilog_115_SaveLogsSimulator=true
		iverilog_119_GTKWaveSavFile=tb_top_02.sav
		iverilog_120_GTKWaveSavFile=tb_top_02.sav
		iverilog_120_GTKWaveSavFile=tb_ahci_01.sav
		iverilog_122_GrepFindErrWarn=error\|warning\|sorry
		iverilog_77_Param_Exe=/usr/local/bin/iverilog
		iverilog_78_VVP_Exe=/usr/local/bin/vvp
		@@ -24,4 +24,5 @@ iverilog_81_TopModulesOther=glbl<-@\#\#@->
		iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
		iverilog_88_ShowNoProblem=true
		iverilog_89_ShowNoProblem=true
		iverilog_95_IcarusTopFile=tb/tb_ahci.tf
		iverilog_99_GrepFindErrWarn=error\|warning\|sorry

ahci/ahci_fsm.v

+2 −1

Original line number	Diff line number	Diff line
		@@ -316,7 +316,8 @@ module ahci_fsm

		always @ (posedge mclk) begin
		if (hba_rst) pgm_jump_addr <= (was_hba_rst \|\| was_port_rst) ? (was_hba_rst? LABEL_HBA_RST:LABEL_PORT_RST) : LABEL_POR;
		else if (async_pend_r[1]) pgm_jump_addr <= async_from_st? LABEL_ST_CLEARED : LABEL_COMINIT;
		// else if (async_pend_r[1]) pgm_jump_addr <= async_from_st? LABEL_ST_CLEARED : LABEL_COMINIT;
		else if (async_pend_r[0]) pgm_jump_addr <= async_from_st? LABEL_ST_CLEARED : LABEL_COMINIT;
		else if (fsm_transitions[0] && (!cond_met_w \|\| !fsm_transitions[1])) pgm_jump_addr <= pgm_data[9:0];

		was_rst <= hba_rst;

ahci/ahci_top.v

+12 −7

Original line number	Diff line number	Diff line
		@@ -24,7 +24,9 @@ module ahci_top#(
		parameter PREFETCH_ALWAYS = 0,
		parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
		parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen
		parameter ADDRESS_BITS = 10 // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
		parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
		parameter HBA_RESET_BITS = 9, // duration of HBA reset in aclk periods (9: ~10usec)
		parameter RESET_TO_FIRST_ACCESS = 1 // keep port reset until first R/W any register by software
		)(
		input aclk, // clock - should be buffered
		input arst, // @aclk sync reset, active high
		@@ -32,8 +34,8 @@ module ahci_top#(
		input mrst, // reset in mclk clock domain (after SATA PLL is on)
		// async reset for SATA (mrst will be response to it)
		output hba_arst, // hba async reset (currently does ~ the same as port reset)
		output port_arst, // port0 async reset by software

		output port_arst, // port0 async set by software (does not include arst)
		output port_arst_any, // port0 async set by software and by arst
		input hclk, // AXI HP interface clock for 64-bit DMA (current - 150MHz
		input hrst, // reset in hclk clock domain
		// MAXIGP1
		@@ -594,7 +596,9 @@ module ahci_top#(


		axi_ahci_regs #(
		.ADDRESS_BITS(10)
		.ADDRESS_BITS (ADDRESS_BITS),
		.HBA_RESET_BITS (HBA_RESET_BITS),
		.RESET_TO_FIRST_ACCESS (RESET_TO_FIRST_ACCESS)
		) axi_ahci_regs_i (
		.aclk (aclk), // input
		.arst (arst), // input
		@@ -632,6 +636,7 @@ module ahci_top#(
		.soft_write_data (soft_write_data), // output[31:0]
		.soft_write_en (soft_write_en), // output
		.hba_arst (hba_arst), // output // does not include arst
		.port_arst_any (port_arst_any), // async set by arst
		.port_arst (port_arst), // output // does not include arst
		.hba_clk (mclk), // input
		.hba_rst (mrst), // input // deasserted when mclk is stable

ahci/axi_ahci_regs.v

+30 −11

Original line number	Diff line number	Diff line
		@@ -40,7 +40,8 @@
		module axi_ahci_regs#(
		// parameter ADDRESS_BITS = 8 // number of memory address bits
		parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
		parameter HBA_RESET_BITS = 9 // duration of HBA reset in aclk periods (9: ~10usec)
		parameter HBA_RESET_BITS = 9, // duration of HBA reset in aclk periods (9: ~10usec)
		parameter RESET_TO_FIRST_ACCESS = 1 // keep port reset until first R/W any register by software
		)(
		input aclk, // clock - should be buffered
		input arst, // @aclk sync reset, active high
		@@ -89,6 +90,7 @@ module axi_ahci_regs#(
		// Apply next 2 resets and arst OR-ed to SATA.extrst
		output hba_arst, // hba async reset (currently does ~ the same as port reset)
		output port_arst, // port0 async reset by software
		output port_arst_any, // port0 async reset by POR or software

		// 2. HBA R/W registers, use hba clock
		input hba_clk, // SATA clock, now 75MHz
		@@ -161,9 +163,10 @@ module axi_ahci_regs#(
		wire [31:0] wmask = {{8{bram_wstb_r[3]}},{8{bram_wstb_r[2]}},{8{bram_wstb_r[1]}},{8{bram_wstb_r[0]}}};
		reg [ADDRESS_BITS-1:0] bram_waddr_r;

		reg [HBA_RESET_BITS-1:0] hba_reset_cntr = 1; // time to keep hba_reset_r active after writing to GHC.HR
		reg [HBA_RESET_BITS-1:0] hba_reset_cntr; // time to keep hba_reset_r active after writing to GHC.HR
		reg hba_rst_r; // hba _reset (currently does ~ the same as port reset)
		reg port_rst_r; // port _reset by software
		reg port_arst_any_r = 1; // port _reset by software or POR

		wire high_sel = bram_waddr_r[ADDRESS_BITS-1]; // high addresses - use single-cycle writes without read-modify-write
		wire afi_cache_set_w = bram_wen_r && !high_sel && (bram_addr == HBA_PORT__AFI_CACHE__WR_CM__ADDR);
		@@ -180,13 +183,15 @@ module axi_ahci_regs#(
		reg was_port_rst_aclk; // last reset was port reset
		reg [2:0] was_hba_rst_r; // last reset was hba reset (not counting system reset)
		reg [2:0] was_port_rst_r; // last reset was port reset

		reg [2:0] arst_r = ~0; // previous state of arst
		reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access
		wire any_access = bram_wen_r \|\| bram_ren[0];

		// assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen ? bram_waddr : pre_awaddr);
		assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
		assign hba_arst = hba_rst_r; // hba _reset (currently does ~ the same as port reset)
		assign port_arst = port_rst_r; // port _reset by software

		assign port_arst_any = port_arst_any_r;
		assign was_hba_rst = was_hba_rst_r[0];
		assign was_port_rst = was_port_rst_r[0];

		@@ -221,6 +226,17 @@ module axi_ahci_regs#(
		end
		endgenerate

		// always @ (posedge aclk or posedge arst) begin
		always @ (posedge aclk) begin
		if (arst) wait_first_access <= RESET_TO_FIRST_ACCESS;
		else if (any_access) wait_first_access <= 0;

		if (arst) port_arst_any_r <= 1;
		else if (set_port_rst) port_arst_any_r <= ahci_regs_di[0]; // write "1" - reset on, write 0 - reset off
		else if (wait_first_access && any_access) port_arst_any_r <= 0;
		else if (arst_r[2] && !arst_r[1]) port_arst_any_r <= wait_first_access;
		end

		always @(posedge aclk) begin
		if (arst) hba_reset_cntr <= 0; // 1; no HBA reset at arst
		else if (set_hba_rst) hba_reset_cntr <= {HBA_RESET_BITS{1'b1}};
		@@ -237,6 +253,9 @@ module axi_ahci_regs#(
		if (arst \|\| set_hba_rst) was_port_rst_aclk <= 0;
		else if (port_rst_on) was_port_rst_aclk <= 1;

		if (arst) arst_r <= ~0;
		else arst_r <= arst_r << 1;

		end

		always @ (hba_clk) begin

ahci/sata_ahci_top.v

+20 −9

Original line number	Diff line number	Diff line
		@@ -35,7 +35,14 @@
		/*
		* Takes commands from axi iface as a slave, transfers data with another axi iface as a master
		*/
		module sata_ahci_top(
		module sata_ahci_top#(
		parameter PREFETCH_ALWAYS = 0,
		// parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
		// parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen
		parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
		parameter HBA_RESET_BITS = 9, // duration of HBA reset in aclk periods (9: ~10usec)
		parameter RESET_TO_FIRST_ACCESS = 1 // keep port reset until first R/W any register by software
		)(
		output wire sata_clk,
		output wire sata_rst,
		input wire arst, // extrst,
		@@ -157,11 +164,11 @@
		// wire sata_clk;
		// wire sata_rst;

		wire hba_arst;
		wire hba_arst; // @SuppressThisWarning VEditor unused
		wire port_arst; // @SuppressThisWarning VEditor unused
		wire port_arst_any;
		wire exrst = port_arst_any; // now both hba_arst and port_arst are the same?

		wire port_arst;

		wire exrst = port_arst; // now both hba_arst and port_arst are the same?


		// Data/type FIFO, host -> device
		@@ -224,10 +231,12 @@


		ahci_top #(
		.PREFETCH_ALWAYS(0),
		.READ_REG_LATENCY(2),
		.READ_CT_LATENCY(1),
		.ADDRESS_BITS(10)
		.PREFETCH_ALWAYS (PREFETCH_ALWAYS),
		// .READ_REG_LATENCY (READ_REG_LATENCY),
		// .READ_CT_LATENCY (READ_CT_LATENCY),
		.ADDRESS_BITS (ADDRESS_BITS),
		.HBA_RESET_BITS (HBA_RESET_BITS),
		.RESET_TO_FIRST_ACCESS (RESET_TO_FIRST_ACCESS)
		) ahci_top_i (
		.aclk (ACLK), // input
		.arst (arst), // input
		@@ -235,6 +244,8 @@
		.mrst (sata_rst), // input
		.hba_arst (hba_arst), // output
		.port_arst (port_arst), // output
		.port_arst_any (port_arst_any), // port0 async set by software and by arst

		.hclk (hclk), // input
		.hrst (hrst), // input

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