testing hardware, found elastic buffer problems (0c64eabc) · Commits · Elphel / x393_sata

.project

+17 −17

Original line number	Original line	Diff line number	Diff line
	@@ -52,87 +52,87 @@
	<link>		<link>
	<name>vivado_logs/VivadoBitstream.log</name>		<name>vivado_logs/VivadoBitstream.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160202194431938.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160203212454764.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOpt.log</name>		<name>vivado_logs/VivadoOpt.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160202194431938.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160203212454764.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPhys.log</name>		<name>vivado_logs/VivadoOptPhys.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160202194431938.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160203212454764.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPower.log</name>		<name>vivado_logs/VivadoOptPower.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160202194431938.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160203212454764.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoPlace.log</name>		<name>vivado_logs/VivadoPlace.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160202194431938.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160203212454764.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoRoute.log</name>		<name>vivado_logs/VivadoRoute.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160202194431938.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160203212454764.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoSynthesis.log</name>		<name>vivado_logs/VivadoSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160202194431938.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160203212221686.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160202194431938.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160203212454764.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160202194431938.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160203212221686.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportImplemented.log</name>		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160202194431938.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160203212454764.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportSynthesis.log</name>		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160202194431938.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160203212221686.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-opt-phys.dcp</name>		<name>vivado_state/x393_sata-opt-phys.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160202194431938.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160203212454764.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-opt-power.dcp</name>		<name>vivado_state/x393_sata-opt-power.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160202194431938.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160203212454764.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-opt.dcp</name>		<name>vivado_state/x393_sata-opt.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160202194431938.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160203212454764.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-place.dcp</name>		<name>vivado_state/x393_sata-place.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160202194431938.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160203212454764.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-route.dcp</name>		<name>vivado_state/x393_sata-route.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160202194431938.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160203212454764.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-synth.dcp</name>		<name>vivado_state/x393_sata-synth.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160202194431938.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160203212221686.dcp</location>
	</link>		</link>
	</linkedResources>		</linkedResources>
	</projectDescription>		</projectDescription>

ahci/ahci_ctrl_stat.v

+19 −5

Original line number	Original line	Diff line number	Diff line
	@@ -168,13 +168,18 @@ module ahci_ctrl_stat #(
	reg [31:0] PxCMD_r;		reg [31:0] PxCMD_r;
	reg pxci0_r;		reg pxci0_r;

			reg cirq_PRC; // clear PRC bit when clearing PxSERR.DIAG.N
			reg cirq_PC; // clear PC bit when clearing PxSERR.DIAG.X
			wire [31:0] cirq ={32{cirq_PRC}} & HBA_PORT__PxIS__PRCS__MASK \| // 'h400000;
			{32{cirq_PC}} & HBA_PORT__PxIS__PCS__MASK; // 'h40;;};


	wire [31:0] sirq = {32{sirq_TFE}} & HBA_PORT__PxIS__TFES__MASK \| // 'h40000000;		wire [31:0] sirq = {32{sirq_TFE}} & HBA_PORT__PxIS__TFES__MASK \| // 'h40000000;
	{32{sirq_IF }} & HBA_PORT__PxIS__IFS__MASK \| // 'h8000000;		{32{sirq_IF }} & HBA_PORT__PxIS__IFS__MASK \| // 'h8000000;
	{32{sirq_INF}} & HBA_PORT__PxIS__INFS__MASK \| // 'h4000000;		{32{sirq_INF}} & HBA_PORT__PxIS__INFS__MASK \| // 'h4000000;
	{32{sirq_OF }} & HBA_PORT__PxIS__OFS__MASK \| // 'h1000000;		{32{sirq_OF }} & HBA_PORT__PxIS__OFS__MASK \| // 'h1000000;
	{32{sirq_PRC}} & HBA_PORT__PxIS__PRCS__MASK \| // 'h400000;		{32{sirq_PRC}} & HBA_PORT__PxIS__PRCS__MASK \| // 'h400000;
	{32{sirq_PC}} & HBA_PORT__PxIS__PCS__MASK \| // 'h40;;		{32{sirq_PC}} & HBA_PORT__PxIS__PCS__MASK \| // 'h40;
	{32{sirq_DP}} & HBA_PORT__PxIS__DPS__MASK \| // 'h20;		{32{sirq_DP}} & HBA_PORT__PxIS__DPS__MASK \| // 'h20;
	{32{sirq_UF }} & HBA_PORT__PxIS__UFS__MASK \| // 'h10;		{32{sirq_UF }} & HBA_PORT__PxIS__UFS__MASK \| // 'h10;
	{32{sirq_SDB}} & HBA_PORT__PxIS__SDBS__MASK \| // 'h8;		{32{sirq_SDB}} & HBA_PORT__PxIS__SDBS__MASK \| // 'h8;
	@@ -259,6 +264,10 @@ module ahci_ctrl_stat #(
	assign serr_diag_X = \|(HBA_PORT__PxSERR__DIAG__X__MASK & PxSERR_r);		assign serr_diag_X = \|(HBA_PORT__PxSERR__DIAG__X__MASK & PxSERR_r);
	assign ssts_det = PxSSTS_r[3:0];		assign ssts_det = PxSSTS_r[3:0];

			// assign cirq_PRC = swr_HBA_PORT__PxSERR && \|(soft_write_data & HBA_PORT__PxSERR__DIAG__N__MASK);
			// assign cirq_PC = swr_HBA_PORT__PxSERR && \|(soft_write_data & HBA_PORT__PxSERR__DIAG__X__MASK);


	localparam PxIE_MASK = HBA_PORT__PxIE__TFEE__MASK \| // 'h40000000;		localparam PxIE_MASK = HBA_PORT__PxIE__TFEE__MASK \| // 'h40000000;
	HBA_PORT__PxIE__IFE__MASK \| // 'h8000000;		HBA_PORT__PxIE__IFE__MASK \| // 'h8000000;
	HBA_PORT__PxIE__INFE__MASK \| // 'h4000000;		HBA_PORT__PxIE__INFE__MASK \| // 'h4000000;
	@@ -355,6 +364,11 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK \| // 'hf0000000;
	assign pcmd_clo = PxCMD_r[3]; // causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit		assign pcmd_clo = PxCMD_r[3]; // causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit
	assign pcmd_st = PxCMD_r[0]; // current value		assign pcmd_st = PxCMD_r[0]; // current value

			always @(posedge mclk) begin // Here we do not have data written by soft, only the result (cleared). If bit is 0, it is
			// either cleared, or was 0. If it was 0, then IS bit was also 0, so clearing will not hurt.
			cirq_PRC <= swr_HBA_PORT__PxSERR && \|(~soft_write_data & HBA_PORT__PxSERR__DIAG__N__MASK);
			cirq_PC <= swr_HBA_PORT__PxSERR && \|(~soft_write_data & HBA_PORT__PxSERR__DIAG__X__MASK);
			end

	always @(posedge mclk) begin		always @(posedge mclk) begin
	if (mrst) irq <= 0;		if (mrst) irq <= 0;
	@@ -392,7 +406,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK \| // 'hf0000000;
	// HBA_PORT__PxIS register		// HBA_PORT__PxIS register
	always @(posedge mclk) begin		always @(posedge mclk) begin
	if (rst_por) PxIS_r <= 0;		if (rst_por) PxIS_r <= 0;
	else PxIS_r <= PxIS_MASK & ((swr_HBA_PORT__PxIS ? soft_write_data : PxIS_r) \| sirq);		else PxIS_r <= PxIS_MASK & ((swr_HBA_PORT__PxIS ? soft_write_data : (PxIS_r & ~cirq)) \| sirq);
	end		end

	// HBA_PORT__PxIE register		// HBA_PORT__PxIE register
	@@ -485,11 +499,11 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK \| // 'hf0000000;
	else if (update_HBA_PORT__PxSSTS) ssts_changed <= 0;		else if (update_HBA_PORT__PxSSTS) ssts_changed <= 0;

	if (mrst) serr_changed <= 1; //0;		if (mrst) serr_changed <= 1; //0;
	else if (serr) serr_changed <= 1;		else if (\|serr) serr_changed <= 1;
	else if (update_HBA_PORT__PxSERR) serr_changed <= 0;		else if (update_HBA_PORT__PxSERR) serr_changed <= 0;

	if (mrst) sirq_changed <= 1; //0;		if (mrst) sirq_changed <= 1; //0;
	else if (sirq) sirq_changed <= 1;		else if ((\|sirq) \|\| (\|cirq)) sirq_changed <= 1;
	else if (update_HBA_PORT__PxIS) sirq_changed <= 0;		else if (update_HBA_PORT__PxIS) sirq_changed <= 0;

	if (mrst) pxcmd_changed <= 1; //0;		if (mrst) pxcmd_changed <= 1; //0;

ahci/ahci_sata_layers.v

+13 −4

Original line number	Original line	Diff line number	Diff line
	@@ -172,13 +172,18 @@ module ahci_sata_layers #(
	wire [31:0] debug_phy;		wire [31:0] debug_phy;
	wire [31:0] debug_link;		wire [31:0] debug_link;

			wire rxelsfull;
			wire rxelsempty;

	wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer		wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer


	// assign debug_sata = {link_established, phy_ready, debug_phy[29:16],debug_link[15:0]}; //		// assign debug_sata = {link_established, phy_ready, debug_phy[29:16],debug_link[15:0]}; //
	assign debug_sata = debug_link[31:0]; //		// assign debug_sata = debug_link[31:0]; //
	/// assign debug_sata = debug_phy;		/// assign debug_sata = debug_phy;

			// assign debug_sata = {debug_link[31:4],debug_phy[3:0]} ; //
			assign debug_sata = {debug_link[31:8],debug_phy[7:0]} ; //

	assign ll_h2d_last = (h2d_type_out == H2D_TYPE_FIS_LAST);		assign ll_h2d_last = (h2d_type_out == H2D_TYPE_FIS_LAST);
	assign d2h_valid = d2h_nempty;		assign d2h_valid = d2h_nempty;
	@@ -206,8 +211,8 @@ module ahci_sata_layers #(
	assign serr_DS = phy_ready && (0); // RWC: Link sequence error		assign serr_DS = phy_ready && (0); // RWC: Link sequence error
	assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer		assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
	// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error		// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
	assign serr_DI = phy_ready && (0); // RWC: PHY Internal Error		assign serr_DI = phy_ready && (rxelsfull); // RWC: PHY Internal Error // just debugging
	assign serr_EP = phy_ready && (0); // RWC: Protocol Error - a violation of SATA protocol detected		assign serr_EP = phy_ready && (rxelsempty); // RWC: Protocol Error - a violation of SATA protocol detected // just debugging
	assign serr_EC = phy_ready && (0); // RWC: Persistent Communication or Data Integrity Error		assign serr_EC = phy_ready && (0); // RWC: Persistent Communication or Data Integrity Error
	assign serr_ET = phy_ready && (0); // RWC: Transient Data Integrity Error (error not recovered by the interface)		assign serr_ET = phy_ready && (0); // RWC: Transient Data Integrity Error (error not recovered by the interface)
	assign serr_EM = phy_ready && (0); // RWC: Communication between the device and host was lost but re-established		assign serr_EM = phy_ready && (0); // RWC: Communication between the device and host was lost but re-established
	@@ -320,8 +325,12 @@ module ahci_sata_layers #(
	.comreset_send (comreset_send), // input		.comreset_send (comreset_send), // input
	.cominit_got (cominit_got), // output wire		.cominit_got (cominit_got), // output wire
	.comwake_got (serr_DW), // output wire		.comwake_got (serr_DW), // output wire
			.rxelsfull (rxelsfull), // output wire
			.rxelsempty (rxelsempty), // output wire

	.cplllock_debug (),		.cplllock_debug (),
	.usrpll_locked_debug(),		.usrpll_locked_debug(),

	.debug_sata (debug_phy)		.debug_sata (debug_phy)
	,.debug_detected_alignp(debug_detected_alignp)		,.debug_detected_alignp(debug_detected_alignp)
	);		);

ahci/ahci_top.v

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -690,8 +690,8 @@ module ahci_top#(
	.afi_cache_set (set_axi_cache_mode), // output		.afi_cache_set (set_axi_cache_mode), // output
	.was_hba_rst (was_hba_rst), // output		.was_hba_rst (was_hba_rst), // output
	.was_port_rst (was_port_rst), // output		.was_port_rst (was_port_rst), // output
	// .debug_in ({2'b0, last_jump_addr[9:0], debug_in[19:0]})		.debug_in ({2'b0, last_jump_addr[9:0], debug_in[19:0]})
	.debug_in (debug_in[31:0])		/// .debug_in (debug_in[31:0])
	);		);
	ahci_ctrl_stat #(		ahci_ctrl_stat #(
	.ADDRESS_BITS (ADDRESS_BITS)		.ADDRESS_BITS (ADDRESS_BITS)

host/gtx_elastic.v

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -32,8 +32,8 @@
	* with at least one of the Free Software programs.		* with at least one of the Free Software programs.
	*******************************************************************************/		*******************************************************************************/
	module gtx_elastic #(		module gtx_elastic #(
	parameter DEPTH_LOG2 = 3, // => 8 total rows		parameter DEPTH_LOG2 = 4, // 3, // => 8 total rows
	parameter OFFSET = 4 // distance between read and write pointers, = wr_ptr - rd_ptr		parameter OFFSET = 8 // 4 // distance between read and write pointers, = wr_ptr - rd_ptr
	)		)
	(		(
	input wire rst,		input wire rst,

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