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Commit 0c64eabc authored by Andrey Filippov's avatar Andrey Filippov
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testing hardware, found elastic buffer problems

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.project
View file @ 0c64eabc
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160202194431938.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160203212454764.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160202194431938.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160203212454764.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160202194431938.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160203212454764.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160202194431938.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160203212454764.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160202194431938.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160203212454764.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160202194431938.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160203212221686.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
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</link> </link>
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<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160202194431938.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160203212221686.log</location>
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<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160202194431938.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160203212454764.log</location>
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<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160202194431938.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160203212221686.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-phys.dcp</name> <name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160202194431938.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160203212454764.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-power.dcp</name> <name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160202194431938.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160203212454764.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt.dcp</name> <name>vivado_state/x393_sata-opt.dcp</name>
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<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160202194431938.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160203212454764.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-place.dcp</name> <name>vivado_state/x393_sata-place.dcp</name>
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<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160202194431938.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160203212454764.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-route.dcp</name> <name>vivado_state/x393_sata-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160202194431938.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160203212454764.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-synth.dcp</name> <name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160202194431938.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160203212221686.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
ahci/ahci_ctrl_stat.v
View file @ 0c64eabc
...@@ -168,13 +168,18 @@ module ahci_ctrl_stat #( ...@@ -168,13 +168,18 @@ module ahci_ctrl_stat #(
reg [31:0] PxCMD_r; reg [31:0] PxCMD_r;
reg pxci0_r; reg pxci0_r;
reg cirq_PRC; // clear PRC bit when clearing PxSERR.DIAG.N
reg cirq_PC; // clear PC bit when clearing PxSERR.DIAG.X
wire [31:0] cirq ={32{cirq_PRC}} & HBA_PORT__PxIS__PRCS__MASK | // 'h400000;
{32{cirq_PC}} & HBA_PORT__PxIS__PCS__MASK; // 'h40;;};
wire [31:0] sirq = {32{sirq_TFE}} & HBA_PORT__PxIS__TFES__MASK | // 'h40000000; wire [31:0] sirq = {32{sirq_TFE}} & HBA_PORT__PxIS__TFES__MASK | // 'h40000000;
{32{sirq_IF }} & HBA_PORT__PxIS__IFS__MASK | // 'h8000000; {32{sirq_IF }} & HBA_PORT__PxIS__IFS__MASK | // 'h8000000;
{32{sirq_INF}} & HBA_PORT__PxIS__INFS__MASK | // 'h4000000; {32{sirq_INF}} & HBA_PORT__PxIS__INFS__MASK | // 'h4000000;
{32{sirq_OF }} & HBA_PORT__PxIS__OFS__MASK | // 'h1000000; {32{sirq_OF }} & HBA_PORT__PxIS__OFS__MASK | // 'h1000000;
{32{sirq_PRC}} & HBA_PORT__PxIS__PRCS__MASK | // 'h400000; {32{sirq_PRC}} & HBA_PORT__PxIS__PRCS__MASK | // 'h400000;
{32{sirq_PC}} & HBA_PORT__PxIS__PCS__MASK | // 'h40;; {32{sirq_PC}} & HBA_PORT__PxIS__PCS__MASK | // 'h40;
{32{sirq_DP}} & HBA_PORT__PxIS__DPS__MASK | // 'h20; {32{sirq_DP}} & HBA_PORT__PxIS__DPS__MASK | // 'h20;
{32{sirq_UF }} & HBA_PORT__PxIS__UFS__MASK | // 'h10; {32{sirq_UF }} & HBA_PORT__PxIS__UFS__MASK | // 'h10;
{32{sirq_SDB}} & HBA_PORT__PxIS__SDBS__MASK | // 'h8; {32{sirq_SDB}} & HBA_PORT__PxIS__SDBS__MASK | // 'h8;
...@@ -257,7 +262,11 @@ module ahci_ctrl_stat #( ...@@ -257,7 +262,11 @@ module ahci_ctrl_stat #(
assign update_pending = | regs_changed; assign update_pending = | regs_changed;
assign pcmd_fre = |(HBA_PORT__PxCMD__FRE__MASK & PxCMD_r); assign pcmd_fre = |(HBA_PORT__PxCMD__FRE__MASK & PxCMD_r);
assign serr_diag_X = |(HBA_PORT__PxSERR__DIAG__X__MASK & PxSERR_r); assign serr_diag_X = |(HBA_PORT__PxSERR__DIAG__X__MASK & PxSERR_r);
assign ssts_det = PxSSTS_r[3:0]; assign ssts_det = PxSSTS_r[3:0];
// assign cirq_PRC = swr_HBA_PORT__PxSERR && |(soft_write_data & HBA_PORT__PxSERR__DIAG__N__MASK);
// assign cirq_PC = swr_HBA_PORT__PxSERR && |(soft_write_data & HBA_PORT__PxSERR__DIAG__X__MASK);
localparam PxIE_MASK = HBA_PORT__PxIE__TFEE__MASK | // 'h40000000; localparam PxIE_MASK = HBA_PORT__PxIE__TFEE__MASK | // 'h40000000;
HBA_PORT__PxIE__IFE__MASK | // 'h8000000; HBA_PORT__PxIE__IFE__MASK | // 'h8000000;
...@@ -355,6 +364,11 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000; ...@@ -355,6 +364,11 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000;
assign pcmd_clo = PxCMD_r[3]; // causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit assign pcmd_clo = PxCMD_r[3]; // causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit
assign pcmd_st = PxCMD_r[0]; // current value assign pcmd_st = PxCMD_r[0]; // current value
always @(posedge mclk) begin // Here we do not have data written by soft, only the result (cleared). If bit is 0, it is
// either cleared, or was 0. If it was 0, then IS bit was also 0, so clearing will not hurt.
cirq_PRC <= swr_HBA_PORT__PxSERR && |(~soft_write_data & HBA_PORT__PxSERR__DIAG__N__MASK);
cirq_PC <= swr_HBA_PORT__PxSERR && |(~soft_write_data & HBA_PORT__PxSERR__DIAG__X__MASK);
end
always @(posedge mclk) begin always @(posedge mclk) begin
if (mrst) irq <= 0; if (mrst) irq <= 0;
...@@ -392,7 +406,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000; ...@@ -392,7 +406,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000;
// HBA_PORT__PxIS register // HBA_PORT__PxIS register
always @(posedge mclk) begin always @(posedge mclk) begin
if (rst_por) PxIS_r <= 0; if (rst_por) PxIS_r <= 0;
else PxIS_r <= PxIS_MASK & ((swr_HBA_PORT__PxIS ? soft_write_data : PxIS_r) | sirq); else PxIS_r <= PxIS_MASK & ((swr_HBA_PORT__PxIS ? soft_write_data : (PxIS_r & ~cirq)) | sirq);
end end
// HBA_PORT__PxIE register // HBA_PORT__PxIE register
...@@ -485,11 +499,11 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000; ...@@ -485,11 +499,11 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000;
else if (update_HBA_PORT__PxSSTS) ssts_changed <= 0; else if (update_HBA_PORT__PxSSTS) ssts_changed <= 0;
if (mrst) serr_changed <= 1; //0; if (mrst) serr_changed <= 1; //0;
else if (serr) serr_changed <= 1; else if (|serr) serr_changed <= 1;
else if (update_HBA_PORT__PxSERR) serr_changed <= 0; else if (update_HBA_PORT__PxSERR) serr_changed <= 0;
if (mrst) sirq_changed <= 1; //0; if (mrst) sirq_changed <= 1; //0;
else if (sirq) sirq_changed <= 1; else if ((|sirq) || (|cirq)) sirq_changed <= 1;
else if (update_HBA_PORT__PxIS) sirq_changed <= 0; else if (update_HBA_PORT__PxIS) sirq_changed <= 0;
if (mrst) pxcmd_changed <= 1; //0; if (mrst) pxcmd_changed <= 1; //0;
......
ahci/ahci_sata_layers.v
View file @ 0c64eabc
...@@ -171,14 +171,19 @@ module ahci_sata_layers #( ...@@ -171,14 +171,19 @@ module ahci_sata_layers #(
wire [31:0] debug_phy; wire [31:0] debug_phy;
wire [31:0] debug_link; wire [31:0] debug_link;
wire rxelsfull;
wire rxelsempty;
wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer
// assign debug_sata = {link_established, phy_ready, debug_phy[29:16],debug_link[15:0]}; // // assign debug_sata = {link_established, phy_ready, debug_phy[29:16],debug_link[15:0]}; //
assign debug_sata = debug_link[31:0]; // // assign debug_sata = debug_link[31:0]; //
/// assign debug_sata = debug_phy; /// assign debug_sata = debug_phy;
// assign debug_sata = {debug_link[31:4],debug_phy[3:0]} ; //
assign debug_sata = {debug_link[31:8],debug_phy[7:0]} ; //
assign ll_h2d_last = (h2d_type_out == H2D_TYPE_FIS_LAST); assign ll_h2d_last = (h2d_type_out == H2D_TYPE_FIS_LAST);
assign d2h_valid = d2h_nempty; assign d2h_valid = d2h_nempty;
...@@ -206,8 +211,8 @@ module ahci_sata_layers #( ...@@ -206,8 +211,8 @@ module ahci_sata_layers #(
assign serr_DS = phy_ready && (0); // RWC: Link sequence error assign serr_DS = phy_ready && (0); // RWC: Link sequence error
assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error // assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
assign serr_DI = phy_ready && (0); // RWC: PHY Internal Error assign serr_DI = phy_ready && (rxelsfull); // RWC: PHY Internal Error // just debugging
assign serr_EP = phy_ready && (0); // RWC: Protocol Error - a violation of SATA protocol detected assign serr_EP = phy_ready && (rxelsempty); // RWC: Protocol Error - a violation of SATA protocol detected // just debugging
assign serr_EC = phy_ready && (0); // RWC: Persistent Communication or Data Integrity Error assign serr_EC = phy_ready && (0); // RWC: Persistent Communication or Data Integrity Error
assign serr_ET = phy_ready && (0); // RWC: Transient Data Integrity Error (error not recovered by the interface) assign serr_ET = phy_ready && (0); // RWC: Transient Data Integrity Error (error not recovered by the interface)
assign serr_EM = phy_ready && (0); // RWC: Communication between the device and host was lost but re-established assign serr_EM = phy_ready && (0); // RWC: Communication between the device and host was lost but re-established
...@@ -319,9 +324,13 @@ module ahci_sata_layers #( ...@@ -319,9 +324,13 @@ module ahci_sata_layers #(
.set_offline (set_offline), // input .set_offline (set_offline), // input
.comreset_send (comreset_send), // input .comreset_send (comreset_send), // input
.cominit_got (cominit_got), // output wire .cominit_got (cominit_got), // output wire
.comwake_got (serr_DW), // output wire .comwake_got (serr_DW), // output wire
.rxelsfull (rxelsfull), // output wire
.rxelsempty (rxelsempty), // output wire
.cplllock_debug (), .cplllock_debug (),
.usrpll_locked_debug(), .usrpll_locked_debug(),
.debug_sata (debug_phy) .debug_sata (debug_phy)
,.debug_detected_alignp(debug_detected_alignp) ,.debug_detected_alignp(debug_detected_alignp)
); );
......
ahci/ahci_top.v
View file @ 0c64eabc
...@@ -690,8 +690,8 @@ module ahci_top#( ...@@ -690,8 +690,8 @@ module ahci_top#(
.afi_cache_set (set_axi_cache_mode), // output .afi_cache_set (set_axi_cache_mode), // output
.was_hba_rst (was_hba_rst), // output .was_hba_rst (was_hba_rst), // output
.was_port_rst (was_port_rst), // output .was_port_rst (was_port_rst), // output
// .debug_in ({2'b0, last_jump_addr[9:0], debug_in[19:0]}) .debug_in ({2'b0, last_jump_addr[9:0], debug_in[19:0]})
.debug_in (debug_in[31:0]) /// .debug_in (debug_in[31:0])
); );
ahci_ctrl_stat #( ahci_ctrl_stat #(
.ADDRESS_BITS (ADDRESS_BITS) .ADDRESS_BITS (ADDRESS_BITS)
......
host/gtx_elastic.v
View file @ 0c64eabc
...@@ -32,8 +32,8 @@ ...@@ -32,8 +32,8 @@
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*******************************************************************************/ *******************************************************************************/
module gtx_elastic #( module gtx_elastic #(
parameter DEPTH_LOG2 = 3, // => 8 total rows parameter DEPTH_LOG2 = 4, // 3, // => 8 total rows
parameter OFFSET = 4 // distance between read and write pointers, = wr_ptr - rd_ptr parameter OFFSET = 8 // 4 // distance between read and write pointers, = wr_ptr - rd_ptr
) )
( (
input wire rst, input wire rst,
......
host/gtx_wrap.v
View file @ 0c64eabc
...@@ -84,7 +84,12 @@ module gtx_wrap #( ...@@ -84,7 +84,12 @@ module gtx_wrap #(
output wire [DATA_BYTE_WIDTH * 8 - 1:0] rxdata, output wire [DATA_BYTE_WIDTH * 8 - 1:0] rxdata,
output wire [DATA_BYTE_WIDTH - 1:0] rxcharisk, output wire [DATA_BYTE_WIDTH - 1:0] rxcharisk,
output wire [DATA_BYTE_WIDTH - 1:0] rxnotintable, output wire [DATA_BYTE_WIDTH - 1:0] rxnotintable,
output wire [DATA_BYTE_WIDTH - 1:0] rxdisperr output wire [DATA_BYTE_WIDTH - 1:0] rxdisperr,
output wire dbg_rxphaligndone,
output wire dbg_rx_clocks_aligned,
output wire dbg_rxcdrlock,
output wire dbg_rxdlysresetdone
); );
wire rxresetdone_gtx; wire rxresetdone_gtx;
...@@ -293,6 +298,39 @@ gtx_8x10enc gtx_8x10enc( ...@@ -293,6 +298,39 @@ gtx_8x10enc gtx_8x10enc(
.outdata (txdata_enc_out) .outdata (txdata_enc_out)
); );
// Adjust RXOUTCLK so RXUSRCLK (==xclk) matches SIPO output data
wire rxcdrlock; // Marked as "reserved" - maybe not use it, only rxelecidle?
reg rxdlysreset = 0;
wire rxphaligndone;
wire rxdlysresetdone;
reg rx_clocks_aligned = 0;
reg [2:0] rxdlysreset_cntr = 7;
reg rxdlysresetdone_r;
assign dbg_rxphaligndone = rxphaligndone; // never gets up?
assign dbg_rx_clocks_aligned = rx_clocks_aligned;
assign dbg_rxcdrlock = rxcdrlock; //goes in/out (because of the SS ?
assign dbg_rxdlysresetdone = rxdlysresetdone_r;
always @ (posedge xclk) begin
// if (rxelecidle || !rxcdrlock) rxdlysreset_cntr <= 5;
if (rxelecidle) rxdlysreset_cntr <= 5;
else if (|rxdlysreset_cntr) rxdlysreset_cntr <= rxdlysreset_cntr - 1;
// if (rxelecidle || !rxcdrlock) rxdlysreset <= 0;
if (rxelecidle) rxdlysreset <= 0;
else rxdlysreset <= |rxdlysreset_cntr;
// if (rxelecidle || !rxcdrlock || rxdlysreset || |rxdlysreset_cntr) rx_clocks_aligned <= 0;
// if (rxelecidle || rxdlysreset || |rxdlysreset_cntr) rx_clocks_aligned <= 0;
if (rxelecidle) rx_clocks_aligned <= 0;
// else if (rxphaligndone) rx_clocks_aligned <= 1;
else if (rxphaligndone) rx_clocks_aligned <= 1;
if (rxelecidle || rxdlysreset || |rxdlysreset_cntr) rxdlysresetdone_r <= 0;
else if (rxdlysresetdone) rxdlysresetdone_r <= 1;
end
/* /*
* RX PCS part: comma detect + align module, 10/8 decoder, elastic buffer, interface resynchronisation * RX PCS part: comma detect + align module, 10/8 decoder, elastic buffer, interface resynchronisation
* all modules before elastic buffer shall work on a restored clock - xclk * all modules before elastic buffer shall work on a restored clock - xclk
...@@ -331,7 +369,9 @@ begin ...@@ -331,7 +369,9 @@ begin
end end
gtx_comma_align gtx_comma_align( gtx_comma_align gtx_comma_align(
// .rst (~rx_clocks_aligned), // ~wrap_rxreset_),
.rst (~wrap_rxreset_), .rst (~wrap_rxreset_),
.clk (xclk), .clk (xclk),
.indata (rxdata_comma_in), .indata (rxdata_comma_in),
.outdata (rxdata_comma_out), .outdata (rxdata_comma_out),
...@@ -348,6 +388,7 @@ wire [1:0] rxnotintable_dec_out; ...@@ -348,6 +388,7 @@ wire [1:0] rxnotintable_dec_out;
wire [1:0] rxdisperr_dec_out; wire [1:0] rxdisperr_dec_out;
gtx_10x8dec gtx_10x8dec( gtx_10x8dec gtx_10x8dec(
// .rst (~rx_clocks_aligned), // ~wrap_rxreset_),
.rst (~wrap_rxreset_), .rst (~wrap_rxreset_),
.clk (xclk), .clk (xclk),
.indata (rxdata_comma_out), .indata (rxdata_comma_out),
...@@ -372,11 +413,13 @@ gtx_elastic #( ...@@ -372,11 +413,13 @@ gtx_elastic #(
.OFFSET (4) .OFFSET (4)
) )
gtx_elastic( gtx_elastic(
// .rst (~rx_clocks_aligned), // ~wrap_rxreset_),
.rst (~wrap_rxreset_), .rst (~wrap_rxreset_),
.wclk (xclk), .wclk (xclk),
.rclk (rxusrclk), .rclk (rxusrclk),
.isaligned_in (state_aligned), /// .isaligned_in (state_aligned),
.isaligned_in (state_aligned && rxdlysresetdone_r), // rx_clocks_aligned), //Allow to align early, but do not tell it is aligned until xclk is aligned to SIPO par. clock
.charisk_in (rxcharisk_dec_out), .charisk_in (rxcharisk_dec_out),
.notintable_in (rxnotintable_dec_out), .notintable_in (rxnotintable_dec_out),
.disperror_in (rxdisperr_dec_out), .disperror_in (rxdisperr_dec_out),
...@@ -623,7 +666,7 @@ gtxe2_channel_wrapper #( ...@@ -623,7 +666,7 @@ gtxe2_channel_wrapper #(
.RXPH_CFG (24'h000000), .RXPH_CFG (24'h000000),
.RXPHDLY_CFG (24'h084020), .RXPHDLY_CFG (24'h084020),
.RXPH_MONITOR_SEL (5'b00000), .RXPH_MONITOR_SEL (5'b00000),
.RX_XCLK_SEL ("RXREC"), .RX_XCLK_SEL ("RXUSR"), // ("RXREC"), // Andrey: Now they are the same, just using p.247 "Using RX Buffer Bypass..."
.RX_DDI_SEL (6'b000000), .RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"), .RX_DEFER_RESET_BUF_EN ("TRUE"),
/// .RXCDR_CFG (72'h03000023ff10200020),// 1.6G - 6.25G, No SS, RXOUT_DIV=2 /// .RXCDR_CFG (72'h03000023ff10200020),// 1.6G - 6.25G, No SS, RXOUT_DIV=2
...@@ -773,7 +816,7 @@ gtxe2_channel_wrapper( ...@@ -773,7 +816,7 @@ gtxe2_channel_wrapper(
.EYESCANTRIGGER (1'b0), .EYESCANTRIGGER (1'b0),
.RXCDRFREQRESET (1'b0), .RXCDRFREQRESET (1'b0),
.RXCDRHOLD (1'b0), .RXCDRHOLD (1'b0),
.RXCDRLOCK (), .RXCDRLOCK (rxcdrlock),
.RXCDROVRDEN (1'b0), .RXCDROVRDEN (1'b0),
.RXCDRRESET (1'b0), .RXCDRRESET (1'b0),
.RXCDRRESETRSV (1'b0), .RXCDRRESETRSV (1'b0),
...@@ -799,14 +842,16 @@ gtxe2_channel_wrapper( ...@@ -799,14 +842,16 @@ gtxe2_channel_wrapper(
.GTXRXN (rxn), .GTXRXN (rxn),
.RXBUFRESET (1'b0), .RXBUFRESET (1'b0),
.RXBUFSTATUS (), .RXBUFSTATUS (),
.RXDDIEN (1'b0), // .RXDDIEN (1'b0),
.RXDLYBYPASS (1'b1), .RXDDIEN (1'b1), // Andrey: p.243: "Set high in RX buffer bypass mode"
// .RXDLYBYPASS (1'b1),
.RXDLYBYPASS (1'b0), // Andrey: p.243: "0: Uses the RX delay alignment circuit."
.RXDLYEN (1'b0), .RXDLYEN (1'b0),
.RXDLYOVRDEN (1'b0), .RXDLYOVRDEN (1'b0),
.RXDLYSRESET (1'b0), .RXDLYSRESET (rxdlysreset),
.RXDLYSRESETDONE (), .RXDLYSRESETDONE (rxdlysresetdone),
.RXPHALIGN (1'b0), .RXPHALIGN (1'b0),
.RXPHALIGNDONE (), .RXPHALIGNDONE (rxphaligndone),
.RXPHALIGNEN (1'b0), .RXPHALIGNEN (1'b0),
.RXPHDLYPD (1'b0), .RXPHDLYPD (1'b0),
.RXPHDLYRESET (1'b0), .RXPHDLYRESET (1'b0),
......
host/link.v
View file @ 0c64eabc
...@@ -874,6 +874,7 @@ always @ (posedge clk) ...@@ -874,6 +874,7 @@ always @ (posedge clk)
if (~|rcvd_dword & phy_ready) if (~|rcvd_dword & phy_ready)
begin begin
$display("%m: invalid primitive received : %h, conrol : %h, err : %h", phy_data_in_r, phy_isk_in_r, phy_err_in_r); $display("%m: invalid primitive received : %h, conrol : %h, err : %h", phy_data_in_r, phy_isk_in_r, phy_err_in_r);
#500;
$finish; $finish;
end end
// States checker // States checker
......
host/oob.v
View file @ 0c64eabc
...@@ -154,9 +154,11 @@ reg [DATA_BYTE_WIDTH - 1:0] rxcharisk; ...@@ -154,9 +154,11 @@ reg [DATA_BYTE_WIDTH - 1:0] rxcharisk;
// primitives detection // primitives detection
wire detected_alignp; wire detected_alignp;
localparam NUM_CON_ALIGNS = 1024; localparam NUM_CON_ALIGNS = 2; // just for debugging 1024;
reg [1:0] detected_alignp_cntr; // count detected ALIGNp - do not respond yet
///localparam NUM_CON_ALIGNS = 1024; // just for debugging 1024;
///reg [12:0] detected_alignp_cntr; // count detected ALIGNp - do not respond yet
reg detected_alignp_r; // debugging - N-th ALIGNp primitive reg detected_alignp_r; // debugging - N-th ALIGNp primitive
reg [12:0] detected_alignp_cntr; // count detected ALIGNp - do not respond yet
wire detected_syncp; wire detected_syncp;
// wait until device's cominit is done // wait until device's cominit is done
......
host/sata_phy.v
View file @ 0c64eabc
...@@ -75,6 +75,11 @@ module sata_phy #( ...@@ -75,6 +75,11 @@ module sata_phy #(
input comreset_send, // Not possible yet? input comreset_send, // Not possible yet?
output wire cominit_got, output wire cominit_got,
output wire comwake_got, output wire comwake_got,
// elastic buffer status
output wire rxelsfull,
output wire rxelsempty,
output cplllock_debug, output cplllock_debug,
output usrpll_locked_debug, output usrpll_locked_debug,
output [31:0] debug_sata output [31:0] debug_sata
...@@ -116,8 +121,13 @@ wire rxreset_req; ...@@ -116,8 +121,13 @@ wire rxreset_req;
wire rxreset_ack; wire rxreset_ack;
wire rxreset_oob; wire rxreset_oob;
// elastic buffer status signals TODO // elastic buffer status signals TODO
wire rxelsfull; //wire rxelsfull;
wire rxelsempty; //wire rxelsempty;
wire dbg_rxphaligndone;
wire dbg_rx_clocks_aligned;
wire dbg_rxcdrlock;
wire dbg_rxdlysresetdone;
//wire gtx_ready; //wire gtx_ready;
assign cominit_got = rxcominitdet; // For AHCI assign cominit_got = rxcominitdet; // For AHCI
...@@ -467,7 +477,11 @@ gtx_wrap ...@@ -467,7 +477,11 @@ gtx_wrap
.rxdata (rxdata), // output[31:0] wire .rxdata (rxdata), // output[31:0] wire
.rxcharisk (rxcharisk), // output[3:0] wire .rxcharisk (rxcharisk), // output[3:0] wire
.rxdisperr (rxdisperr), // output[3:0] wire .rxdisperr (rxdisperr), // output[3:0] wire
.rxnotintable (rxnotintable) // output[3:0] wire .rxnotintable (rxnotintable), // output[3:0] wire
.dbg_rxphaligndone (dbg_rxphaligndone),
.dbg_rx_clocks_aligned(dbg_rx_clocks_aligned),
.dbg_rxcdrlock (dbg_rxcdrlock) ,
.dbg_rxdlysresetdone(dbg_rxdlysresetdone)
); );
...@@ -543,6 +557,7 @@ assign debug_sata[19] = txelecidle; ...@@ -543,6 +557,7 @@ assign debug_sata[19] = txelecidle;
assign debug_sata[23:20] = debug_cntr4; assign debug_sata[23:20] = debug_cntr4;
*/ */
//assign phy_ready = link_state & gtx_ready & rxbyteisaligned; //assign phy_ready = link_state & gtx_ready & rxbyteisaligned;
assign debug_sata = {debug_cntr6,debug_cntr5}; //assign debug_sata = {debug_cntr6,debug_cntr5};
assign debug_sata = {25'b0, dbg_rxdlysresetdone, rxelecidle, dbg_rxcdrlock, rxelsfull, rxelsempty, dbg_rxphaligndone, dbg_rx_clocks_aligned};
endmodule endmodule
includes/ahci_localparams.vh
View file @ 0c64eabc
...@@ -402,7 +402,7 @@ ...@@ -402,7 +402,7 @@
localparam HBA_PORT__PxIS__PRCS__ADDR = 'h44; localparam HBA_PORT__PxIS__PRCS__ADDR = 'h44;
localparam HBA_PORT__PxIS__PRCS__MASK = 'h400000; localparam HBA_PORT__PxIS__PRCS__MASK = 'h400000;
localparam HBA_PORT__PxIS__PRCS__DFLT = 'h0; localparam HBA_PORT__PxIS__PRCS__DFLT = 'h0;
// RO: Device Mechanical Presence Status // RWC: Device Mechanical Presence Status
localparam HBA_PORT__PxIS__DMPS__ADDR = 'h44; localparam HBA_PORT__PxIS__DMPS__ADDR = 'h44;
localparam HBA_PORT__PxIS__DMPS__MASK = 'h80; localparam HBA_PORT__PxIS__DMPS__MASK = 'h80;
localparam HBA_PORT__PxIS__DMPS__DFLT = 'h0; localparam HBA_PORT__PxIS__DMPS__DFLT = 'h0;
......
includes/ahci_types.vh
View file @ 0c64eabc
, .INIT_00 (256'h0000000000000000AAAAAAAAAAAAAAAA00000000000000070000000000000000) , .INIT_00 (256'h0000000000000000AAAAAAAAAAAAAAAA00000000000000070000000000000000)
, .INIT_10 (256'h0000000000000000555555555555000000000000000000005555555555500000) , .INIT_10 (256'h0000000000000000555555555555000000000000000000005555555555500000)
, .INIT_11 (256'h000000000000000055054004000001C15551500000001555AAA28000000008AA) , .INIT_11 (256'h000000000000000055054004000001C15551500000001555AAA28000000088AA)
, .INIT_12 (256'h0000000000555555000000000000000000000000000000000000000000000000) , .INIT_12 (256'h0000000000555555000000000000000000000000000000000000000000000000)
, .INIT_13 (256'h00000000AAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF002AAAAA00AA000A) , .INIT_13 (256'h00000000AAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF002AAAAA00AA000A)
, .INIT_14 (256'h000000000000000000000000000000000001555555555550000000000055000D) , .INIT_14 (256'h000000000000000000000000000000000001555555555550000000000055000D)
......
includes/x393_tasks01.vh
View file @ 0c64eabc
...@@ -228,14 +228,17 @@ ...@@ -228,14 +228,17 @@
input [ 3:0] len; input [ 3:0] len;
input [ 1:0] burst; input [ 1:0] burst;
begin begin
wait (!CLK && AR_READY); @ (negedge CLK);
while (!AR_READY) @ (negedge CLK);
// wait (!CLK && AR_READY);
ARID_IN_r <= id; ARID_IN_r <= id;
ARADDR_IN_r <= addr; ARADDR_IN_r <= addr;
ARLEN_IN_r <= len; ARLEN_IN_r <= len;
ARSIZE_IN_r <= 3'b010; ARSIZE_IN_r <= 3'b010;
ARBURST_IN_r <= burst; ARBURST_IN_r <= burst;
AR_SET_CMD_r <= 1'b1; AR_SET_CMD_r <= 1'b1;
wait (CLK); @(posedge CLK);
// wait (CLK);
ARID_IN_r <= 12'hz; ARID_IN_r <= 12'hz;
ARADDR_IN_r <= 'hz; ARADDR_IN_r <= 'hz;
ARLEN_IN_r <= 4'hz; ARLEN_IN_r <= 4'hz;
......
py393sata/x393sata.py
View file @ 0c64eabc
...@@ -34,6 +34,7 @@ __status__ = "Development" ...@@ -34,6 +34,7 @@ __status__ = "Development"
import os import os
from x393_mem import X393Mem from x393_mem import X393Mem
from x393_vsc3304 import x393_vsc3304 from x393_vsc3304 import x393_vsc3304
import create_ahci_registers as registers
from time import sleep from time import sleep
import shutil import shutil
DEFAULT_BITFILE="/usr/local/verilog/x393_sata.bit" DEFAULT_BITFILE="/usr/local/verilog/x393_sata.bit"
...@@ -42,11 +43,13 @@ FPGA_RST_CTRL= 0xf8000240 ...@@ -42,11 +43,13 @@ FPGA_RST_CTRL= 0xf8000240
FPGA0_THR_CTRL=0xf8000178 FPGA0_THR_CTRL=0xf8000178
FPGA_LOAD_BITSTREAM="/dev/xdevcfg" FPGA_LOAD_BITSTREAM="/dev/xdevcfg"
INT_STS= 0xf800700c INT_STS= 0xf800700c
MAXI1_ADDR = 0x80000000
class x393sata(object): class x393sata(object):
DRY_MODE= True # True DRY_MODE= True # True
DEBUG_MODE=1 DEBUG_MODE=1
x393_mem=None x393_mem=None
vsc3304 = None vsc3304 = None
register_defines=None
def __init__(self, debug_mode=1,dry_mode=False, pcb_rev = "10389"): def __init__(self, debug_mode=1,dry_mode=False, pcb_rev = "10389"):
self.DEBUG_MODE=debug_mode self.DEBUG_MODE=debug_mode
if not dry_mode: if not dry_mode:
...@@ -56,6 +59,7 @@ class x393sata(object): ...@@ -56,6 +59,7 @@ class x393sata(object):
self.DRY_MODE=dry_mode self.DRY_MODE=dry_mode
self.x393_mem=X393Mem(debug_mode,dry_mode, 1) self.x393_mem=X393Mem(debug_mode,dry_mode, 1)
self.vsc3304= x393_vsc3304(debug_mode, dry_mode, pcb_rev) self.vsc3304= x393_vsc3304(debug_mode, dry_mode, pcb_rev)
self.register_defines = registers.process_data(False)['field_defines']
def reset_get(self): def reset_get(self):
""" """
Get current reset state Get current reset state
...@@ -173,6 +177,102 @@ class x393sata(object): ...@@ -173,6 +177,102 @@ class x393sata(object):
for i in range(4): for i in range(4):
c.append (byte_to_code((dword >> (8*i)) & 0xff)) c.append (byte_to_code((dword >> (8*i)) & 0xff))
return "D%d.%d D%d.%d D%d.%d K%d.%d "%(c[3][0],c[3][1],c[2][0],c[2][1],c[1][0],c[1][1],c[0][0],c[0][1]) return "D%d.%d D%d.%d D%d.%d K%d.%d "%(c[3][0],c[3][1],c[2][0],c[2][1],c[1][0],c[1][1],c[0][0],c[0][1])
def reg_status(self, skip0 =True):
important = ['HBA_PORT__PxIS',
'HBA_PORT__PxCMD',
'HBA_PORT__PxTFD',
'HBA_PORT__PxSIG',
'HBA_PORT__PxSSTS',
'HBA_PORT__PxSERR',
'HBA_PORT__PxCI'
]
self.parse_register(group_range = important,
skip0 = skip0,
dword = None)
def reset_ie(self):
"""
reset all interrupt and error bits
"""
self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__PxIS'), 0xffffffff)
self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__PxSERR'),0xffffffff)
def reset_device(self):
"""
reset device by initiating COMRESET sequence
"""
self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__PxSCTL'), 0x1)
sleep(0.1)
self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__PxSCTL'), 0x0)
def get_reg_address(self,group_range):
"""
Get absoulte byte address for symbolic group/range name
@param group_range - group name +'__'+ range name, i.e. 'HBA_PORT__PxIS'
@return memory address or None
"""
try:
return 4 * self.register_defines[group_range][0]['dword_address'] + MAXI1_ADDR
except:
print ("failed to find address for %s"%(group_range))
self.parse_register()
return None
def parse_register(self, group_range=None, skip0 =True, dword=None):
"""
Read register and print field values
@param group_name: group name +'__'+ range name, i.e. 'HBA_PORT__PxIS'
@param skip0 - skip fields that are 0
@param dword - provide register value instead of reading the hardware
"""
if isinstance(group_range,(tuple,list)):
for gr in group_range:
if (gr in self.register_defines) and len(self.register_defines[gr]):
self.parse_register(group_range = gr,
skip0 = skip0,
dword = dword)
return
cached_addr=None
cached_data=None
try:
range_defines = self.register_defines[group_range]
_ = range_defines[0] # to treat empty as non-existing
except:
if group_range:
print ("Group/range %s is undefined"%(group_range))
print ("Valid group/range combinations:")
descr={}
for k in self.register_defines:
try:
descr[k] = "%s / %s"%(self.register_defines[k][0]['group_decription'],self.register_defines[k][0]['range_decription'])
except:
pass
for k in sorted(descr.keys()):
print("%s: %s"%(k,descr[k]))
# for k in self.register_defines:
# try:
# print("%s: %s / %s"%(k,self.register_defines[k][0]['group_decription'],self.register_defines[k][0]['range_decription']))
# except:
# pass
return
first_line = True
for fld in range_defines:
byte_addr = 4 * fld['dword_address'] + MAXI1_ADDR
if dword is None:
if byte_addr != cached_addr:
cached_addr = byte_addr
cached_data = self.x393_mem.read_mem(cached_addr)
data = cached_data
else:
data = dword
fld_value = (data >> fld['start_bit']) & ((1 << fld['num_bits']) - 1)
if first_line:
print("%s: 0x%08x [%08x]"%(group_range, data, byte_addr))
first_line = False
if fld_value or not skip0:
print("%8x : %s (%s)"%(fld_value, fld['name'], fld['description'] ))
#hex(mem.read_mem(0x80000ff0)) #hex(mem.read_mem(0x80000ff0))
def exp_gpio (self, def exp_gpio (self,
...@@ -258,6 +358,8 @@ sata = x393sata.x393sata() ...@@ -258,6 +358,8 @@ sata = x393sata.x393sata()
sata.bitstream() sata.bitstream()
sata.vsc3304.connection_status() sata.vsc3304.connection_status()
sata.reg_status()
mem.write_mem(0x8000012c,1) mem.write_mem(0x8000012c,1)
hex(mem.read_mem(0x8000012c)) hex(mem.read_mem(0x8000012c))
mem.write_mem(0x8000012c,0) mem.write_mem(0x8000012c,0)
...@@ -356,6 +458,41 @@ _=mem.mem_dump (0x80000000, 0x100,4) ...@@ -356,6 +458,41 @@ _=mem.mem_dump (0x80000000, 0x100,4)
0x80000380:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0x80000380:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800003c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0x800003c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000000:00240020 80000000 00000000 00000001 00010301 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000040:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000080:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800000c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000100:80000800 00000000 80000c00 00000000 00400040 00000000 0004c006 00000000 00000080 00000000 00000123 00000000 040d0000 00000000 00000000 00000000
0x80000140:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000033 00000003 00000000 00000000
0x80000180:0001fffe 00100000 01010002 00000000 00000000 00000000 00000000 00000000 00000000 80000000 00000000 0001fffe 00000000 00000040 00000000 00000100
0x800001c0:40000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000200:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000240:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000280:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800002c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000300:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000340:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000380:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800003c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000000:00240020 80000000 00000000 00000001 00010301 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000040:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000080:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800000c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000100:80000800 00000000 80000c00 00000000 00400040 00000000 00040006 00000000 00000150 00000101 00000123 00000000 040d0000 00000000 00000000 00000000
0x80000140:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000033 00000003 00000000 00000000
0x80000180:0001fffe 00100000 01010002 00000000 00000000 00000000 00000000 00000000 00000000 80000000 00000000 0001fffe 00000000 00000040 00000000 00000100
0x800001c0:40000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000200:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000240:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000280:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800002c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000300:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000340:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80000380:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x800003c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
mem.write_mem(0x8000012c,1) mem.write_mem(0x8000012c,1)
hex(mem.read_mem(0x8000012c)) hex(mem.read_mem(0x8000012c))
mem.write_mem(0x8000012c,0) mem.write_mem(0x8000012c,0)
......
tb/tb_ahci.tf
View file @ 0c64eabc
...@@ -63,6 +63,10 @@ module tb_ahci #( ...@@ -63,6 +63,10 @@ module tb_ahci #(
`endif // CVC `endif // CVC
`endif // IVERILOG `endif // IVERILOG
parameter HOST_CLK_PERIOD = 6.666; //nsec
//parameter DEVICE_CLK_PERIOD = 6.653; //nsec
parameter DEVICE_CLK_PERIOD = 6.666; //nsec TODO: Implement actual CDR
reg [639:0] TESTBENCH_TITLE = 'bz; // to show human-readable state in the GTKWave reg [639:0] TESTBENCH_TITLE = 'bz; // to show human-readable state in the GTKWave
reg [31:0] TESTBENCH_DATA; reg [31:0] TESTBENCH_DATA;
reg [11:0] TESTBENCH_ID; reg [11:0] TESTBENCH_ID;
...@@ -81,6 +85,8 @@ end ...@@ -81,6 +85,8 @@ end
reg EXTCLK_P = 1'b1; reg EXTCLK_P = 1'b1;
reg EXTCLK_N = 1'b0; reg EXTCLK_N = 1'b0;
reg DEV_EXTCLK_P = 1'b1;
reg DEV_EXTCLK_N = 1'b0;
//reg serial_clk = 1'b1; //reg serial_clk = 1'b1;
reg [11:0] ARID_IN_r; reg [11:0] ARID_IN_r;
...@@ -335,8 +341,8 @@ sata_device dev( ...@@ -335,8 +341,8 @@ sata_device dev(
.RXP (txp), .RXP (txp),
.TXN (rxn), .TXN (rxn),
.TXP (rxp), .TXP (rxp),
.EXTCLK_P (EXTCLK_P), .EXTCLK_P (DEV_EXTCLK_P),
.EXTCLK_N (EXTCLK_N) .EXTCLK_N (DEV_EXTCLK_N)
); );
// SAXI HP interface // SAXI HP interface
...@@ -603,11 +609,16 @@ initial forever @ (posedge CLK) begin ...@@ -603,11 +609,16 @@ initial forever @ (posedge CLK) begin
end end
end end
always #3.333 begin //always #3.333 begin
always #(DEVICE_CLK_PERIOD/2) begin
EXTCLK_P = ~EXTCLK_P; EXTCLK_P = ~EXTCLK_P;
EXTCLK_N = ~EXTCLK_N; EXTCLK_N = ~EXTCLK_N;
end end
always #(HOST_CLK_PERIOD/2) begin
DEV_EXTCLK_P = ~DEV_EXTCLK_P;
DEV_EXTCLK_N = ~DEV_EXTCLK_N;
end
/* /*
// MAXI clock // MAXI clock
always #10 always #10
...@@ -889,6 +900,7 @@ localparam ATA_WDMA = 'hca; // Identify command ...@@ -889,6 +900,7 @@ localparam ATA_WDMA = 'hca; // Identify command
initial begin //Host initial begin //Host
NUM_WORDS_EXPECTED =0;
wait (!RST); wait (!RST);
//reg [639:0] TESTBENCH_TITLE = "RESET"; // to show human-readable state in the GTKWave //reg [639:0] TESTBENCH_TITLE = "RESET"; // to show human-readable state in the GTKWave
TESTBENCH_TITLE = "NO_RESET"; TESTBENCH_TITLE = "NO_RESET";
...@@ -936,8 +948,18 @@ initial begin //Host ...@@ -936,8 +948,18 @@ initial begin //Host
maxigp1_print (GHC__IS__IPS__ADDR << 2,"GHC__IS__IPS__ADDR"); // Now it should be 0 maxigp1_print (GHC__IS__IPS__ADDR << 2,"GHC__IS__IPS__ADDR"); // Now it should be 0
maxigp1_print (HBA_PORT__PxIS__DHRS__ADDR << 2,"HBA_PORT__PxIS__DHRS__ADDR"); // It should be 400041 - DHR inerrupt (and others) maxigp1_print (HBA_PORT__PxIS__DHRS__ADDR << 2,"HBA_PORT__PxIS__DHRS__ADDR"); // It should be 400041 - DHR inerrupt (and others)
maxigp1_writep (HBA_PORT__PxIS__DHRS__ADDR << 2, HBA_PORT__PxIS__DHRS__MASK); // clear that interrupt // maxigp1_writep (HBA_PORT__PxIS__DHRS__ADDR << 2, HBA_PORT__PxIS__DHRS__MASK); // clear that interrupt
maxigp1_writep (HBA_PORT__PxIS__DHRS__ADDR << 2, ~0); // clear all interrupt
maxigp1_print (HBA_PORT__PxIS__DHRS__ADDR << 2,"HBA_PORT__PxIS__DHRS__ADDR"); // Now it should be 0400040 (DHR cleared) maxigp1_print (HBA_PORT__PxIS__DHRS__ADDR << 2,"HBA_PORT__PxIS__DHRS__ADDR"); // Now it should be 0400040 (DHR cleared)
maxigp1_print (HBA_PORT__PxSERR__DIAG__X__ADDR << 2,"HBA_PORT__PxSERR"); //
maxigp1_writep (HBA_PORT__PxSERR__DIAG__X__ADDR << 2, ~0); // clear all errors
maxigp1_print (HBA_PORT__PxIS__DHRS__ADDR << 2, "cleared all i/e: HBA_PORT__PxIS__DHRS__ADDR"); //
maxigp1_print (HBA_PORT__PxSERR__DIAG__X__ADDR << 2,"cleared all i/e: HBA_PORT__PxSERR"); //
maxigp1_print (HBA_PORT__PxIS__DHRS__ADDR << 2, "re-read: HBA_PORT__PxIS__DHRS__ADDR"); //
maxigp1_print (HBA_PORT__PxSERR__DIAG__X__ADDR << 2,"re-read: HBA_PORT__PxSERR"); //
maxigp1_print (HBA_PORT__PxIS__DHRS__ADDR << 2, "re-read: HBA_PORT__PxIS__DHRS__ADDR"); //
maxigp1_print (HBA_PORT__PxSERR__DIAG__X__ADDR << 2,"re-read: HBA_PORT__PxSERR"); //
//HBA_PORT__PxIS__DHRS__ADDR //HBA_PORT__PxIS__DHRS__ADDR
maxigp1_print (PXSIG_OFFS32 << 2,"PXSIG_OFFS32"); maxigp1_print (PXSIG_OFFS32 << 2,"PXSIG_OFFS32");
......
tb_ahci_01.sav
View file @ 0c64eabc
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Tue Feb 2 18:17:45 2016 [*] Thu Feb 4 04:54:31 2016
[*] [*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160202111528174.fst" [dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160203212010340.fst"
[dumpfile_mtime] "Tue Feb 2 18:16:38 2016" [dumpfile_mtime] "Thu Feb 4 04:21:22 2016"
[dumpfile_size] 8331332 [dumpfile_size] 8311364
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav" [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 0 [timestart] 13492600
[size] 1823 1180 [size] 1823 1180
[pos] 1997 0 [pos] 1959 27
*-23.459948 25150000 35135962 430000 1192690 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-14.313643 13551454 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci. [treeopen] tb_ahci.
[treeopen] tb_ahci.dev.
[treeopen] tb_ahci.dev.linkMonitorFIS. [treeopen] tb_ahci.dev.linkMonitorFIS.
[treeopen] tb_ahci.dev.phy. [treeopen] tb_ahci.dev.phy.
[treeopen] tb_ahci.dev.phy.gtx_wrapper. [treeopen] tb_ahci.dev.phy.gtx_wrapper.
...@@ -30,6 +29,9 @@ ...@@ -30,6 +29,9 @@
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk5.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_elastic.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.
...@@ -53,10 +55,11 @@ ...@@ -53,10 +55,11 @@
[treeopen] tb_ahci.simul_axi_hp_wr_i. [treeopen] tb_ahci.simul_axi_hp_wr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i. [treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i. [treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.
[sst_width] 438 [treeopen] tb_ahci.simul_axi_read_i.
[signals_width] 411 [sst_width] 317
[signals_width] 307
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 565 [sst_vpaned_height] 568
@820 @820
tb_ahci.TESTBENCH_TITLE[639:0] tb_ahci.TESTBENCH_TITLE[639:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0]
...@@ -65,13 +68,47 @@ tb_ahci.dev.DEV_TITLE[639:0] ...@@ -65,13 +68,47 @@ tb_ahci.dev.DEV_TITLE[639:0]
@28 @28
tb_ahci.CLK tb_ahci.CLK
tb_ahci.RST tb_ahci.RST
@22 tb_ahci.AR_SET_CMD_r
tb_ahci.read_and_wait.address[31:0]
@28
tb_ahci.dut.TXN tb_ahci.dut.TXN
tb_ahci.dut.RXN tb_ahci.dut.RXN
tb_ahci.dut.irq tb_ahci.dut.irq
@c00200 @c00200
-axi_read
@28
tb_ahci.AR_SET_CMD_r
tb_ahci.AR_SET_CMD
@22
tb_ahci.NUM_WORDS_EXPECTED
tb_ahci.NUM_WORDS_READ
tb_ahci.axi_read_addr.addr[31:0]
@28
tb_ahci.axi_read_addr.burst[1:0]
@22
tb_ahci.axi_read_addr.id[11:0]
tb_ahci.axi_read_addr.len[3:0]
@28
tb_ahci.maxi_monitor_rvalid
@22
tb_ahci.maxi_monitor_rdata[31:0]
tb_ahci.registered_rdata[31:0]
@28
tb_ahci.simul_axi_slow_ready_read_i.valid
tb_ahci.simul_axi_slow_ready_read_i.ready
@200
-
@22
tb_ahci.simul_axi_master_rdaddr_i.araddr_in[31:0]
@28
tb_ahci.simul_axi_master_rdaddr_i.arvalid
@22
tb_ahci.simul_axi_master_rdaddr_i.araddr[31:0]
tb_ahci.simul_axi_master_rdaddr_i.araddr_out[31:0]
@28
tb_ahci.simul_axi_master_rdaddr_i.arvalid
tb_ahci.simul_axi_master_rdaddr_i.arvalid_out
@1401200
-axi_read
@c00200
-axi_ahci_regs -axi_ahci_regs
@800022 @800022
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
...@@ -765,10 +802,54 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0] ...@@ -765,10 +802,54 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0] (31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
@1401200 @1401200
-group_end -group_end
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.cirq[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.cirq_PC
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.cirq_PRC
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.swr_HBA_PORT__PxSERR
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.soft_write_data[31:0]
@1401200
-group_end
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.set_ghc_is_r tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.set_ghc_is_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ghc_ie_r tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ghc_ie_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ghc_is_r tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ghc_is_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq_changed
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.irq tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.irq
@c00200 @c00200
-ssts -ssts
...@@ -2420,9 +2501,9 @@ tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full ...@@ -2420,9 +2501,9 @@ tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full
- -
@1401200 @1401200
-ahci_dma -ahci_dma
@800200 @c00200
-link -link
@c00023 @c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
@28 @28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0] (0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
...@@ -2457,7 +2538,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0] ...@@ -2457,7 +2538,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(29)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0] (29)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(30)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0] (30)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(31)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0] (31)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
@1401201 @1401200
-group_end -group_end
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rst tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rst
...@@ -2567,7 +2648,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_synp ...@@ -2567,7 +2648,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_synp
@1000200 @1000200
-states -states
-oob -oob
@800200 @c00200
-states -states
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_align tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_align
...@@ -2593,7 +2674,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_shold ...@@ -2593,7 +2674,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_shold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_sof tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_sof
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_sync_esc tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_sync_esc
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_wait tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_wait
@1000200 @1401200
-states -states
@800200 @800200
-crc -crc
...@@ -2760,7 +2841,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair ...@@ -2760,7 +2841,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_req tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_ack tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_ack
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_busy tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_busy
@1000200 @1401200
-link -link
@c00200 @c00200
-phy -phy
...@@ -2915,10 +2996,57 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g ...@@ -2915,10 +2996,57 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g
@1401200 @1401200
-GTXE2_GPL -GTXE2_GPL
-phy -phy
@800200
-comma
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.indata[19:0]
@23
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.outdata[19:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma_detected
@200
-
@1000200
-comma
@c00200
-elastic
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_elastic.rst
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_elastic.rclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_elastic.wclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_elastic.charisk_in[1:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_elastic.charisk_out[1:0]
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_elastic.data_in[15:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_elastic.data_out[15:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_elastic.lword_strobe
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_elastic.fword_strobe
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_elastic.fword_strobe_correction
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_elastic.align_1st
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_elastic.align_2nd
@1401200
-elastic
@c00200
-rx_resynchro
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk5.rxdata_resynchro.rclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk5.rxdata_resynchro.wclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk5.rxdata_resynchro.we
@200
-
@1401200
-rx_resynchro
@c00200 @c00200
-oob_ctrl -oob_ctrl
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.gtx_ready tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.gtx_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxcominitdet_in
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxcominitdet
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxcominit_done
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxcominitdet_l
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.gtx_ready
@200 @200
- -
@800200 @800200
...@@ -2929,9 +3057,72 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.gtx_ready ...@@ -2929,9 +3057,72 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.gtx_ready
-oob -oob
@1401200 @1401200
-oob_ctrl -oob_ctrl
@800200 @820
tb_ahci.maxigp1_print.msg[319:0]
@22
tb_ahci.read_and_wait.address[31:0]
tb_ahci.axi_read_addr.addr[31:0]
@28
tb_ahci.axi_read_addr.burst[1:0]
@22
tb_ahci.axi_read_addr.id[11:0]
tb_ahci.axi_read_addr.len[3:0]
@28
tb_ahci.CLK
tb_ahci.rvalid
tb_ahci.rready
tb_ahci.simul_axi_read_i.reset
tb_ahci.simul_axi_read_i.start_burst
@22
tb_ahci.simul_axi_read_i.addr_out[15:0]
@200
-
@c00200
-gtx -gtx
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rx_clocks_aligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.state_triggered
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.state_aligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.set_aligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.set_triggered
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.clr_triggered
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxcominitdet
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.isaligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.rx_oob.reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.xclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxcominitdet_gtx
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxcominitdet_gtx_r
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxcominitdet
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxphaligndone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.rxcdrlock
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.rxdlysresetdone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.rxphaligndone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.RXPHALIGNDONE
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.RXPHALIGN
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.RXDLYSRESET
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.RXDLYSRESETDONE
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.RXELECIDLE
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.RXCDRLOCK
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset_cntr[2:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset_cntr[2:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset_cntr[2:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset_cntr[2:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.comma
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.wrap_rxreset_
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxbyteisaligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxresetdone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxresetdone_gtx
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.xclk tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.xclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.state_aligned tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.state_aligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.state_triggered tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.state_triggered
...@@ -2961,9 +3152,8 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0] ...@@ -2961,9 +3152,8 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
- -
@1401200 @1401200
-gtx8x10enc -gtx8x10enc
@1000200
-gtx -gtx
@800200 @c00200
-device -device
@820 @820
tb_ahci.dev.linkMonitorFIS.rprim[111:0] tb_ahci.dev.linkMonitorFIS.rprim[111:0]
...@@ -3014,7 +3204,7 @@ tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.TXN ...@@ -3014,7 +3204,7 @@ tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.TXN
-dev_phy -dev_phy
@820 @820
tb_ahci.dev.linkSendPrim.type[111:0] tb_ahci.dev.linkSendPrim.type[111:0]
@1000200 @1401200
-device -device
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0
wrapper/GTXE2_GPL.v
View file @ 0c64eabc
...@@ -2961,7 +2961,8 @@ parameter RX_CLK25_DIV = 6; ...@@ -2961,7 +2961,8 @@ parameter RX_CLK25_DIV = 6;
parameter TX_CLK25_DIV = 6; parameter TX_CLK25_DIV = 6;
// clocking reset ( + TX PMA) // clocking reset ( + TX PMA)
wire clk_reset = EYESCANRESET | RXCDRFREQRESET | RXCDRRESET | RXCDRRESETRSV | RXPRBSCNTRESET | RXBUFRESET | RXDLYSRESET | RXPHDLYRESET | RXDFELPMRESET | GTRXRESET | RXOOBRESET | RXPCSRESET | RXPMARESET | CFGRESET | GTTXRESET | GTRESETSEL | RESETOVRD | TXDLYSRESET | TXPHDLYRESET | TXPCSRESET | TXPMARESET; //wire clk_reset = EYESCANRESET | RXCDRFREQRESET | RXCDRRESET | RXCDRRESETRSV | RXPRBSCNTRESET | RXBUFRESET | RXDLYSRESET | RXPHDLYRESET | RXDFELPMRESET | GTRXRESET | RXOOBRESET | RXPCSRESET | RXPMARESET | CFGRESET | GTTXRESET | GTRESETSEL | RESETOVRD | TXDLYSRESET | TXPHDLYRESET | TXPCSRESET | TXPMARESET;
wire clk_reset = EYESCANRESET | RXCDRFREQRESET | RXCDRRESET | RXCDRRESETRSV | RXPRBSCNTRESET | RXBUFRESET | RXPHDLYRESET | RXDFELPMRESET | GTRXRESET | RXOOBRESET | RXPCSRESET | RXPMARESET | CFGRESET | GTTXRESET | GTRESETSEL | RESETOVRD | TXDLYSRESET | TXPHDLYRESET | TXPCSRESET | TXPMARESET;
// have to wait before an external pll (mmcm) locks with usrclk, after that PCS can be resetted. Actually, we reset PMA also, because why not // have to wait before an external pll (mmcm) locks with usrclk, after that PCS can be resetted. Actually, we reset PMA also, because why not
reg reset; reg reset;
reg [31:0] reset_timer = 0; reg [31:0] reset_timer = 0;
...@@ -2974,8 +2975,17 @@ always @ (posedge TXUSRCLK) ...@@ -2974,8 +2975,17 @@ always @ (posedge TXUSRCLK)
reg rx_rst_done = 1'b0; reg rx_rst_done = 1'b0;
reg tx_rst_done = 1'b0; reg tx_rst_done = 1'b0;
reg rxcdrlock = 1'b0;
reg rxdlysresetdone = 1'b0;
reg rxphaligndone = 1'b0;
assign RXRESETDONE = rx_rst_done; assign RXRESETDONE = rx_rst_done;
assign TXRESETDONE = tx_rst_done; assign TXRESETDONE = tx_rst_done;
assign RXCDRLOCK = rxcdrlock;
assign RXDLYSRESETDONE = rxdlysresetdone;
assign RXPHALIGNDONE = rxphaligndone;
initial initial
forever @ (posedge reset) forever @ (posedge reset)
begin begin
...@@ -2994,7 +3004,46 @@ begin ...@@ -2994,7 +3004,46 @@ begin
@ (posedge GTREFCLK0); @ (posedge GTREFCLK0);
rx_rst_done <= 1'b1; rx_rst_done <= 1'b1;
end end
localparam RXCDRLOCK_DELAY = 10; // Refclk periods
localparam RXDLYSRESET_MIN_DURATION = 50; // ns
localparam RXDLYSRESETDONE_DELAY = 10;
localparam RXDLYSRESETDONE_DURATION = 7; // 100ns
localparam RXPHALIGNDONE_DELAY1 = 15;
localparam RXPHALIGNDONE_DURATION1 = 7;
localparam RXPHALIGNDONE_DELAY2 = 10;
initial forever @ (posedge (reset || RXELECIDLE)) begin
rxcdrlock <= 1'b0;
@ (negedge (reset || RXELECIDLE));
repeat (RXCDRLOCK_DELAY) @ (posedge GTREFCLK0);
rxcdrlock <= 1'b1;
end
initial forever @ (posedge RXDLYSRESET) begin
rxdlysresetdone <= 1'b0;
rxphaligndone <= 1'b0;
# (RXDLYSRESET_MIN_DURATION);
if (!RXDLYSRESET) begin
$display ("%m: RXDLYSRESET is too short - minimal duration is 50 nsec");
end else begin
@ (negedge RXDLYSRESET);
// if (!RXELECIDLE && rxcdrlock) begin
if (!RXELECIDLE) begin // removed that condition - rxcdrlock seems to go up/down (SS?)
repeat (RXDLYSRESETDONE_DELAY) @ (posedge GTREFCLK0);
rxdlysresetdone <= 1'b1;
repeat (RXDLYSRESETDONE_DURATION) @ (posedge GTREFCLK0);
rxdlysresetdone <= 1'b0;
repeat (RXPHALIGNDONE_DELAY1) @ (posedge GTREFCLK0);
rxphaligndone <= 1'b1;
repeat (RXPHALIGNDONE_DURATION1) @ (posedge GTREFCLK0);
rxphaligndone <= 1'b0;
repeat (RXPHALIGNDONE_DELAY2) @ (posedge GTREFCLK0);
rxphaligndone <= 1'b1;
end else $display ("%m: RXELECIDLE in active or rxcdrlock is inactive when applying RXDLYSRESET");
end
end
//RXELECIDLE
gtxe2_chnl #( gtxe2_chnl #(
.CPLL_CFG (CPLL_CFG), .CPLL_CFG (CPLL_CFG),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
......
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