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Commit 09c87c41 authored by Andrey Filippov's avatar Andrey Filippov
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v13: tolerating elidle from device during comreset/cominit (when device changes data rate)

parent 2d285422
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.settings/com.elphel.vdt.iverilog.prefs
View file @ 09c87c41
...@@ -2,7 +2,7 @@ com.elphel.store.context.iverilog=iverilog_@_TopModulesOther<-@\#\#@->iverilog_@ ...@@ -2,7 +2,7 @@ com.elphel.store.context.iverilog=iverilog_@_TopModulesOther<-@\#\#@->iverilog_@
com.elphel.store.version.iverilog=1.1 com.elphel.store.version.iverilog=1.1
eclipse.preferences.version=1 eclipse.preferences.version=1
iverilog_@_ExtraFiles=x393/glbl.v<-@\#\#@-> iverilog_@_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_@_GTKWaveSavFile=tb_ahci_01.sav iverilog_@_GTKWaveSavFile=tb_ahci_06.sav
iverilog_@_GrepFindErrWarn=error|warning|sorry iverilog_@_GrepFindErrWarn=error|warning|sorry
iverilog_@_IcarusTopFile=tb/tb_ahci.tf iverilog_@_IcarusTopFile=tb/tb_ahci.tf
iverilog_@_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@-> iverilog_@_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
......
device/oob_dev.v
View file @ 09c87c41
...@@ -44,7 +44,10 @@ ...@@ -44,7 +44,10 @@
// All references to doc = to SerialATA_Revision_2_6_Gold.pdf // All references to doc = to SerialATA_Revision_2_6_Gold.pdf
module oob_dev #( module oob_dev #(
parameter DATA_BYTE_WIDTH = 4, parameter DATA_BYTE_WIDTH = 4,
parameter CLK_SPEED_GRADE = 2 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz parameter CLK_SPEED_GRADE = 2, // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
parameter TEST_ELIDLE = 2, // test transmitting eidle between data rates (number of times)
parameter ELIDLE_DELAY = 'h28, // 80, // counter cycles
parameter ELIDLE_DURATION = 'h80 // counter cycles
) )
( (
// sata clk = usrclk2 // sata clk = usrclk2
...@@ -83,15 +86,21 @@ localparam STATE_CALIBRATE = 4; ...@@ -83,15 +86,21 @@ localparam STATE_CALIBRATE = 4;
localparam STATE_COMWAKE = 5; localparam STATE_COMWAKE = 5;
localparam STATE_RECAL = 55; localparam STATE_RECAL = 55;
localparam STATE_SENDALIGN = 6; localparam STATE_SENDALIGN = 6;
localparam STATE_EIDLE_RATE = 65;
localparam STATE_READY = 7; localparam STATE_READY = 7;
localparam STATE_PARTIAL = 8; localparam STATE_PARTIAL = 8;
localparam STATE_SLUMBER = 9; localparam STATE_SLUMBER = 9;
localparam STATE_REDUCESPEED = 10; localparam STATE_REDUCESPEED = 10;
localparam STATE_ERROR = 11; localparam STATE_ERROR = 11;
reg [31:0] rate_change_cntr;
reg was_txelecidle;
reg [9:0] state; reg [9:0] state;
wire retry_interval_elapsed; wire retry_interval_elapsed;
wire wait_interval_elapsed; wire wait_interval_elapsed;
wire elidle_rate_delay_elapsed;
wire elidle_rate_duration_elapsed;
wire nocomwake; wire nocomwake;
wire [31:0] align; wire [31:0] align;
wire [31:0] sync; wire [31:0] sync;
...@@ -110,9 +119,21 @@ always @ (posedge clk) ...@@ -110,9 +119,21 @@ always @ (posedge clk)
retry_timer <= rst | ~(state == STATE_AWAITCOMWAKE) ? 32'h0 : retry_timer + 1'b1; retry_timer <= rst | ~(state == STATE_AWAITCOMWAKE) ? 32'h0 : retry_timer + 1'b1;
reg [31:0] wait_timer; reg [31:0] wait_timer;
assign wait_interval_elapsed = wait_timer == 32'd4096; assign wait_interval_elapsed = wait_timer == 32'd4096;
assign elidle_rate_delay_elapsed = wait_timer == ELIDLE_DELAY;
always @ (posedge clk) always @ (posedge clk)
wait_timer <= rst | ~(state == STATE_SENDALIGN) ? 32'h0 : wait_timer + 1'b1; wait_timer <= rst | ~(state == STATE_SENDALIGN) ? 32'h0 : wait_timer + 1'b1;
reg [31:0] elidle_timer;
assign elidle_rate_duration_elapsed = elidle_timer == ELIDLE_DURATION;
always @ (posedge clk)
elidle_timer <= rst | ~(state == STATE_EIDLE_RATE) ? 32'h0 : elidle_timer + 1'b1;
always @ (posedge clk) begin
was_txelecidle <= txelecidle;
if (rst) rate_change_cntr <= 0;
else if (txelecidle && !was_txelecidle) rate_change_cntr <= rate_change_cntr + 1;
end
reg [31:0] data; reg [31:0] data;
reg [3:0] isk; reg [3:0] isk;
...@@ -218,6 +239,7 @@ always @ (posedge clk) ...@@ -218,6 +239,7 @@ always @ (posedge clk)
end end
STATE_SENDALIGN: STATE_SENDALIGN:
begin begin
txelecidle <= 1'b0;
data <= align; data <= align;
isk <= 4'h1; isk <= 4'h1;
if (aligndet) if (aligndet)
...@@ -225,9 +247,21 @@ always @ (posedge clk) ...@@ -225,9 +247,21 @@ always @ (posedge clk)
else else
if (wait_interval_elapsed) if (wait_interval_elapsed)
state <= STATE_ERROR; state <= STATE_ERROR;
else else if ((rate_change_cntr < TEST_ELIDLE) && elidle_rate_delay_elapsed)
state <= STATE_EIDLE_RATE;
else
state <= STATE_SENDALIGN; state <= STATE_SENDALIGN;
end end
STATE_EIDLE_RATE:
begin
txelecidle <= 1'b1;
data <= 0; // align; // 'bz;
isk <= 4'h1;
if (elidle_rate_duration_elapsed)
state <= STATE_SENDALIGN;
end
STATE_READY: STATE_READY:
begin begin
txelecidle <= 1'b0; txelecidle <= 1'b0;
......
host/oob.v
View file @ 09c87c41
...@@ -223,7 +223,11 @@ always @ (posedge clk) begin ...@@ -223,7 +223,11 @@ always @ (posedge clk) begin
else rxdlysreset_r <= rxdlysreset_r << 1; else rxdlysreset_r <= rxdlysreset_r << 1;
end end
reg was_rxelecidle_waiting_reset;
always @ (posedge clk) begin
if (rst || set_wait_eidle) was_rxelecidle_waiting_reset <= 0;
else if (state_wait_rxrst && rxelecidle) was_rxelecidle_waiting_reset <= 1;
end
assign state_idle = ~state_wait_cominit & assign state_idle = ~state_wait_cominit &
~state_wait_comwake & ~state_wait_comwake &
~state_wait_align & ~state_wait_align &
...@@ -253,11 +257,17 @@ end ...@@ -253,11 +257,17 @@ end
assign set_wait_cominit = state_idle & oob_start & ~cominit_req; assign set_wait_cominit = state_idle & oob_start & ~cominit_req;
assign set_wait_comwake = state_idle & cominit_req_l & cominit_allow & rxcominit_done | state_wait_cominit & rxcominitdet_l & rxcominit_done; assign set_wait_comwake = state_idle & cominit_req_l & cominit_allow & rxcominit_done | state_wait_cominit & rxcominitdet_l & rxcominit_done;
assign set_recal_tx = state_wait_comwake & rxcomwakedet_l & rxcomwake_done; assign set_recal_tx = state_wait_comwake & rxcomwakedet_l & rxcomwake_done;
assign set_wait_eidle = state_recal_tx & recal_tx_done; ///assign set_wait_eidle = state_recal_tx & recal_tx_done;
assign set_wait_eidle = (state_recal_tx & recal_tx_done) |
(rxelecidle &
(state_wait_align | state_wait_clk_align | state_wait_align2 | (state_wait_rxrst & rxreset_ack & was_rxelecidle_waiting_reset) ));
assign set_wait_rxrst = state_wait_eidle & eidle_timer_done; assign set_wait_rxrst = state_wait_eidle & eidle_timer_done;
assign set_wait_align = state_wait_rxrst & rxreset_ack; ///assign set_wait_align = state_wait_rxrst & rxreset_ack;
assign set_wait_clk_align = state_wait_align & (detected_alignp_r); ///assign set_wait_clk_align = state_wait_align & (detected_alignp_r);
assign set_wait_align2 = state_wait_clk_align & clk_phase_align_ack; ///assign set_wait_align2 = state_wait_clk_align & clk_phase_align_ack;
assign set_wait_align = state_wait_rxrst & rxreset_ack & ~rxelecidle;
assign set_wait_clk_align = state_wait_align & (detected_alignp_r) & ~rxelecidle;
assign set_wait_align2 = state_wait_clk_align & clk_phase_align_ack & ~rxelecidle;
...@@ -278,10 +288,18 @@ assign clr_wait_cominit = set_wait_comwake | set_error; ...@@ -278,10 +288,18 @@ assign clr_wait_cominit = set_wait_comwake | set_error;
assign clr_wait_comwake = set_recal_tx | set_error; assign clr_wait_comwake = set_recal_tx | set_error;
assign clr_recal_tx = set_wait_eidle | set_error; assign clr_recal_tx = set_wait_eidle | set_error;
assign clr_wait_eidle = set_wait_rxrst | set_error; assign clr_wait_eidle = set_wait_rxrst | set_error;
assign clr_wait_rxrst = set_wait_align | set_error; ///assign clr_wait_rxrst = set_wait_align | set_error;
assign clr_wait_align = set_wait_clk_align | set_error; assign clr_wait_rxrst = state_wait_rxrst & rxreset_ack;
assign clr_wait_clk_align = set_wait_align2 | set_error;
assign clr_wait_align2 = set_wait_synp | set_error; ///assign clr_wait_align = set_wait_clk_align | set_error;
///assign clr_wait_clk_align = set_wait_align2 | set_error;
///assign clr_wait_align2 = set_wait_synp | set_error;
assign clr_wait_align = set_wait_clk_align | set_error | rxelecidle;
assign clr_wait_clk_align = set_wait_align2 | set_error | rxelecidle;
assign clr_wait_align2 = set_wait_synp | set_error | rxelecidle;
assign clr_wait_synp = set_wait_linkup | set_error; assign clr_wait_synp = set_wait_linkup | set_error;
assign clr_wait_linkup = state_wait_linkup; //TODO not so important, but still have to trace 3 back-to-back non alignp primitives assign clr_wait_linkup = state_wait_linkup; //TODO not so important, but still have to trace 3 back-to-back non alignp primitives
assign clr_error = state_error; assign clr_error = state_error;
......
includes/ahci_defaults.vh
View file @ 09c87c41
...@@ -2,6 +2,6 @@ ...@@ -2,6 +2,6 @@
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800) , .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000) , .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000) , .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
, .INIT_0C (256'h000000000000000000000000000000000000000001010012001000000001FFFE) , .INIT_0C (256'h000000000000000000000000000000000000000001010013001000000001FFFE)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000) , .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001) , .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
includes/ahci_localparams.vh
View file @ 09c87c41
...@@ -97,7 +97,7 @@ ...@@ -97,7 +97,7 @@
// RO: HBA Revision ID // RO: HBA Revision ID
localparam PCI_Header__RID__RID__ADDR = 'h62; localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__MASK = 'hff; localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__DFLT = 'h12; localparam PCI_Header__RID__RID__DFLT = 'h13;
// RO: Base Class Code: 1 - Mass Storage Device // RO: Base Class Code: 1 - Mass Storage Device
localparam PCI_Header__CC__BCC__ADDR = 'h62; localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__MASK = 'hff000000; localparam PCI_Header__CC__BCC__MASK = 'hff000000;
......
includes/x393_parameters.vh
View file @ 09c87c41
...@@ -537,6 +537,8 @@ ...@@ -537,6 +537,8 @@
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW" parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter CMPRS_CHN_MASK = 4'hf, // specify wich compressor channels to use (disable some/all to make room for processing)
parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60 parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
parameter CMPRS_BASE_INC = 'h10, parameter CMPRS_BASE_INC = 'h10,
......
py393sata/create_ahci_registers.py
View file @ 09c87c41
...@@ -32,7 +32,8 @@ __status__ = "Development" ...@@ -32,7 +32,8 @@ __status__ = "Development"
**** Modify next value for new file versions, re-run this file ***** **** Modify next value for new file versions, re-run this file *****
""" """
# Revision ID # Revision ID
RID = 0x012 # Revision ID: registering irq on/off in datascope, as if tag = 6/7 RID = 0x013 # Revision ID: tolerating elidle during OOB sequence (when device changes data rate)
#RID = 0x012 # Revision ID: registering irq on/off in datascope, as if tag = 6/7
#RID = 0x011 # Revision ID #RID = 0x011 # Revision ID
VID = 0xfffe # What to use for non-PCI "vendorID"? VID = 0xfffe # What to use for non-PCI "vendorID"?
DID = 0x0001 DID = 0x0001
......
py393sata/x393sata.py
View file @ 09c87c41
...@@ -694,6 +694,7 @@ class x393sata(object): ...@@ -694,6 +694,7 @@ class x393sata(object):
if do_not_start: if do_not_start:
print ('Run the following command to start the comand:') print ('Run the following command to start the comand:')
print("mem.write_mem(sata.get_reg_address('HBA_PORT__PxCI'), 1)") print("mem.write_mem(sata.get_reg_address('HBA_PORT__PxCI'), 1)")
return
else: else:
self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__PxCI'), 1) self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__PxCI'), 1)
print("Command table data:") print("Command table data:")
......
tb_ahci_01.sav
View file @ 09c87c41
[*] [*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Sun Dec 11 04:31:36 2016 [*] Mon Dec 12 06:19:44 2016
[*] [*]
[dumpfile] "/home/eyesis/git/elphel393/fpga-elphel/x393_sata/simulation/tb_ahci-20161210212639118.fst" [dumpfile] "/home/eyesis/git/elphel393/fpga-elphel/x393_sata/simulation/tb_ahci-20161210213129200.fst"
[dumpfile_mtime] "Sun Dec 11 04:27:34 2016" [dumpfile_mtime] "Sun Dec 11 04:32:24 2016"
[dumpfile_size] 13299181 [dumpfile_size] 13299182
[savefile] "/home/eyesis/git/elphel393/fpga-elphel/x393_sata/tb_ahci_01.sav" [savefile] "/home/eyesis/git/elphel393/fpga-elphel/x393_sata/tb_ahci_01.sav"
[timestart] 0 [timestart] 35400000
[size] 1814 1171 [size] 1814 1167
[pos] 68 0 [pos] 85 51
*-24.068264 37475728 32882854 55953880 57700372 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-21.899609 46000000 42208588 49301212 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci. [treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr. [treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev.
[treeopen] tb_ahci.dev.linkMonitorFIS. [treeopen] tb_ahci.dev.linkMonitorFIS.
[treeopen] tb_ahci.dev.linkTransmitFIS. [treeopen] tb_ahci.dev.linkTransmitFIS.
[treeopen] tb_ahci.dev.phy.gtx_wrapper. [treeopen] tb_ahci.dev.phy.gtx_wrapper.
...@@ -61,10 +60,10 @@ ...@@ -61,10 +60,10 @@
[treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i. [treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i. [treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.
[treeopen] tb_ahci.simul_axi_read_i. [treeopen] tb_ahci.simul_axi_read_i.
[sst_width] 311 [sst_width] 466
[signals_width] 312 [signals_width] 459
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 485 [sst_vpaned_height] 483
@820 @820
tb_ahci.TESTBENCH_TITLE[639:0] tb_ahci.TESTBENCH_TITLE[639:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0]
...@@ -1709,7 +1708,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g ...@@ -1709,7 +1708,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g
-drp -drp
@1401200 @1401200
-axi_ahci_regs -axi_ahci_regs
@c00200 @800200
-ahci_fsm -ahci_fsm
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.hba_arst tb_ahci.dut.sata_top.ahci_top_i.hba_arst
...@@ -2002,9 +2001,130 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0] ...@@ -2002,9 +2001,130 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
@1401200 @1000200
-ahci_fsm -ahci_fsm
@800200 @800200
-missing_irq
@28
tb_ahci.dut.irq
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ghc_ie
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ghc_is_r
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
@1401200
-group_end
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
@1401200
-group_end
@c00023
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
@1401201
-group_end
@200
-
@1000200
-missing_irq
@800200
-ahci_fis_receive -ahci_fis_receive
@22 @22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in[31:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in[31:0]
...@@ -5379,12 +5499,49 @@ tb_ahci.dev.linkSendPrim.type[111:0] ...@@ -5379,12 +5499,49 @@ tb_ahci.dev.linkSendPrim.type[111:0]
@800200 @800200
-datascope -datascope
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.datascope_we
@c00022
tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.irq tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.irq
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.irq_r tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.irq_r
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.irq_was tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.irq_was
@29
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.we_irq tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.we_irq
@28
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.we_r tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.we_r
@22 @22
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.h2d_nready_cntr[7:0] tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.h2d_nready_cntr[7:0]
......
tb_ahci_06.sav 0 → 100644
View file @ 09c87c41
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Thu Apr 13 20:11:17 2017
[*]
[dumpfile] "/home/eyesis/git/elphel393/fpga-elphel/x393_sata/simulation/tb_ahci-20170413140803914.fst"
[dumpfile_mtime] "Thu Apr 13 20:08:56 2017"
[dumpfile_size] 13252819
[savefile] "/home/eyesis/git/elphel393/fpga-elphel/x393_sata/tb_ahci_06.sav"
[timestart] 0
[size] 1814 1171
[pos] 0 51
*-23.996487 12744868 42208588 49301212 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev.
[treeopen] tb_ahci.dev.linkMonitorFIS.
[treeopen] tb_ahci.dev.linkTransmitFIS.
[treeopen] tb_ahci.dev.phy.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.dataiface.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.ser.
[treeopen] tb_ahci.dev.phy.oob_dev.
[treeopen] tb_ahci.dut.
[treeopen] tb_ahci.dut.axi_hp_clk_i.
[treeopen] tb_ahci.dut.sata_top.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.crc.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.dataiface.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.tx.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.ahci_dma_rd_stuff_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.
[treeopen] tb_ahci.elastic1632_fast_i.
[treeopen] tb_ahci.elastic1632_slow_i.
[treeopen] tb_ahci.read_sipo_meas.
[treeopen] tb_ahci.simul_axi_hp_rd_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.
[treeopen] tb_ahci.simul_axi_read_i.
[sst_width] 289
[signals_width] 276
[sst_expanded] 1
[sst_vpaned_height] 608
@820
tb_ahci.TESTBENCH_TITLE[639:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0]
tb_ahci.DEVICE_TITLE[639:0]
@c00820
tb_ahci.dev.DEV_TITLE[639:0]
@28
(0)tb_ahci.dev.DEV_TITLE[639:0]
(1)tb_ahci.dev.DEV_TITLE[639:0]
(2)tb_ahci.dev.DEV_TITLE[639:0]
(3)tb_ahci.dev.DEV_TITLE[639:0]
(4)tb_ahci.dev.DEV_TITLE[639:0]
(5)tb_ahci.dev.DEV_TITLE[639:0]
(6)tb_ahci.dev.DEV_TITLE[639:0]
(7)tb_ahci.dev.DEV_TITLE[639:0]
(8)tb_ahci.dev.DEV_TITLE[639:0]
(9)tb_ahci.dev.DEV_TITLE[639:0]
(10)tb_ahci.dev.DEV_TITLE[639:0]
(11)tb_ahci.dev.DEV_TITLE[639:0]
(12)tb_ahci.dev.DEV_TITLE[639:0]
(13)tb_ahci.dev.DEV_TITLE[639:0]
(14)tb_ahci.dev.DEV_TITLE[639:0]
(15)tb_ahci.dev.DEV_TITLE[639:0]
(16)tb_ahci.dev.DEV_TITLE[639:0]
(17)tb_ahci.dev.DEV_TITLE[639:0]
(18)tb_ahci.dev.DEV_TITLE[639:0]
(19)tb_ahci.dev.DEV_TITLE[639:0]
(20)tb_ahci.dev.DEV_TITLE[639:0]
(21)tb_ahci.dev.DEV_TITLE[639:0]
(22)tb_ahci.dev.DEV_TITLE[639:0]
(23)tb_ahci.dev.DEV_TITLE[639:0]
(24)tb_ahci.dev.DEV_TITLE[639:0]
(25)tb_ahci.dev.DEV_TITLE[639:0]
(26)tb_ahci.dev.DEV_TITLE[639:0]
(27)tb_ahci.dev.DEV_TITLE[639:0]
(28)tb_ahci.dev.DEV_TITLE[639:0]
(29)tb_ahci.dev.DEV_TITLE[639:0]
(30)tb_ahci.dev.DEV_TITLE[639:0]
(31)tb_ahci.dev.DEV_TITLE[639:0]
(32)tb_ahci.dev.DEV_TITLE[639:0]
(33)tb_ahci.dev.DEV_TITLE[639:0]
(34)tb_ahci.dev.DEV_TITLE[639:0]
(35)tb_ahci.dev.DEV_TITLE[639:0]
(36)tb_ahci.dev.DEV_TITLE[639:0]
(37)tb_ahci.dev.DEV_TITLE[639:0]
(38)tb_ahci.dev.DEV_TITLE[639:0]
(39)tb_ahci.dev.DEV_TITLE[639:0]
(40)tb_ahci.dev.DEV_TITLE[639:0]
(41)tb_ahci.dev.DEV_TITLE[639:0]
(42)tb_ahci.dev.DEV_TITLE[639:0]
(43)tb_ahci.dev.DEV_TITLE[639:0]
(44)tb_ahci.dev.DEV_TITLE[639:0]
(45)tb_ahci.dev.DEV_TITLE[639:0]
(46)tb_ahci.dev.DEV_TITLE[639:0]
(47)tb_ahci.dev.DEV_TITLE[639:0]
(48)tb_ahci.dev.DEV_TITLE[639:0]
(49)tb_ahci.dev.DEV_TITLE[639:0]
(50)tb_ahci.dev.DEV_TITLE[639:0]
(51)tb_ahci.dev.DEV_TITLE[639:0]
(52)tb_ahci.dev.DEV_TITLE[639:0]
(53)tb_ahci.dev.DEV_TITLE[639:0]
(54)tb_ahci.dev.DEV_TITLE[639:0]
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(639)tb_ahci.dev.DEV_TITLE[639:0]
@1401200
-group_end
@28
tb_ahci.CLK
tb_ahci.RST
tb_ahci.AR_SET_CMD_r
tb_ahci.dut.TXN
tb_ahci.dut.RXN
tb_ahci.dut.irq
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
@c00200
-ahci_sata_layers
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.exrst
tb_ahci.dut.sata_top.ahci_sata_layers_i.reliable_clk
tb_ahci.dut.sata_top.ahci_sata_layers_i.extclk_n
tb_ahci.dut.sata_top.ahci_sata_layers_i.rst
tb_ahci.dut.sata_top.ahci_sata_layers_i.clk
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_d2h_valid
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_d2h_almost_full
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_fill[9:0]
@c00028
tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_fifo_re_regen[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_fifo_re_regen[1:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_fifo_re_regen[1:0]
@1401200
-group_end
@800200
-fifo_d2h_control
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.rst
tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.rd
tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.wr
tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.ramo_full
tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.mem_re
tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.mem_regen
@200
-
@1000200
-fifo_d2h_control
@1401200
-ahci_sata_layers
@c00200
-ahci_top
@28
tb_ahci.dut.sata_top.ahci_top_i.xmit_ok
tb_ahci.dut.sata_top.ahci_top_i.datascope_we
@22
tb_ahci.dut.sata_top.ahci_top_i.regs_waddr[9:0]
tb_ahci.dut.sata_top.ahci_top_i.regs_raddr[9:0]
@c00022
tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.regs_we_freceive
tb_ahci.dut.sata_top.ahci_top_i.regs_we_acs
tb_ahci.dut.sata_top.ahci_top_i.regs_we
tb_ahci.dut.sata_top.ahci_top_i.regs_re[1:0]
@22
tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_acs[31:0]
@c00022
tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.port_arst
tb_ahci.dut.sata_top.ahci_top_i.hba_arst
tb_ahci.dut.sata_top.ahci_top_i.phy_ready[1:0]
tb_ahci.dut.sata_top.ahci_top_i.irq
@c00022
tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_i
@1401200
-group_end
@800200
-ahci_fis_receive
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
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tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_rcvr_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_rcvr_shold
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tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_data_in[31:0]
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tb_ahci.dut.sata_top.ahci_top_i.datascope_we
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(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(18)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(19)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(20)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(21)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(22)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(23)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(24)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(25)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(26)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(27)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(28)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(29)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(30)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(31)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.got_escape
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.clr_rcvr_goodend
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.link_reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_align
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_nocommerr
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.link_established
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_align
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
@1401200
-group_end
@c00200
-oob
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.link_state
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.rxbyteisaligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.gtx_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.set_wait_synp
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.detected_alignp
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.alignp[63:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxdata[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxcharisk[3:0]
@200
---- same in link
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.clk
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_isk_in[3:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_isk_in_r[3:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_data_in_r[31:0]
@200
-
@c00200
-states
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rst
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_error
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_idle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_recal_tx
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_align
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_cominit
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_comwake
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_eidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_linkup
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_rxrst
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_synp
@1401200
-states
-oob
@800200
-dev_dbg
@28
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.dataiface.reset
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.dataiface.full_wr
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.dataiface.val_wr
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.dataiface.val_rd
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.des.need_reset
@22
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
@200
-
@1000200
-dev_dbg
@800200
-dev_crc
@22
tb_ahci.dev.phy.ll_data_out[31:0]
tb_ahci.dev.linkMonitorFIS.cnt
tb_ahci.dev.linkMonitorFIS.crc[31:0]
@28
tb_ahci.dev.linkMonitorFIS.crc_match
@22
tb_ahci.dev.DEV_DATA
tb_ahci.dev.linkMonitorFIS.descrambled_data[31:0]
@200
-CRC_dev_xmit
@22
tb_ahci.dev.linkTransmitFIS.cnt
tb_ahci.dev.linkTransmitFIS.crc
@200
-
@1000200
-dev_crc
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.inc_is_data
@800200
-scrambler
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler.data_in[31:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler.val_in
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler.data_out[31:0]
@200
-
@1000200
-scrambler
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.clk
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_val_in
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_strobe_out
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_in[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_type[1:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_type_out[1:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_frame_req
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_h2d_data_in[31:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_h2d_last
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_in[31:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_val_in
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_strobe_out
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_txing
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_last_in
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_last_out
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair_0
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair
@c08022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
@1401200
-group_end
@20000
-
@200
-
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy_speed[1:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.link_reset
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_data_in[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_isk_in[3:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.dword_val
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_busy_in
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_data_out[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_isk_out[3:0]
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.clk
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_ack
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_busy
@1401200
-link
@c00200
-phy
@800200
-gtx_8x10enc
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_8x10enc.inisk[1:0]
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_8x10enc.indata[15:0]
@200
-
@1000200
-gtx_8x10enc
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txdata[31:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txresetdone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txuserrdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txpcsreset_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txpcsreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txoutclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txreset
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(18)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(19)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(20)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(21)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(22)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(23)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(24)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(25)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(26)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(27)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(28)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(29)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(30)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
(31)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.clk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.extrst
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rst
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.comreset_send
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.cominit_got
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.comwake_got
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.cplllock
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.usrpll_locked
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxresetdone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.cpllreset
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtrefclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txoutclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.usrclk2
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.usrpll_locked
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.cpllreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.cplllock
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxreset_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxreset_oob
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxreset_oob_stop
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxreset_oob
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_configured
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxreset_f
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtrefclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxeyereset_cnt[6:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxeyereset_done
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.clk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.sata_reset_done
@200
-
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.usrpll_locked
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.cplllock
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.cpllreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxuserrdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txuserrdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxresetdone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txresetdone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txreset
@200
-
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxdata[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.ll_data_out[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.ll_charisk_out[3:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txdata[31:0]
@c00200
-GTXE2_GPL
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.CFGRESET
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.CPLLRESET
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.reset
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(18)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(19)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(20)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(21)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(22)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(23)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(24)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(25)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(26)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(27)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(28)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(29)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(30)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
(31)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
@1401200
-group_end
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.outdata[19:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.des.outclk
@200
-
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.dataiface.wordcounter[31:0]
@1401200
-GTXE2_GPL
-phy
@c00200
-comma
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.indata[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.outdata[19:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma_detected
@200
-
@1401200
-comma
@c00200
-elastic_phy
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(18)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(19)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(20)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(21)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(22)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(23)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(24)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(25)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(26)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(27)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(28)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(29)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(30)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
(31)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
@1401200
-group_end
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in1[31:0]
@200
-
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.is_alignp_w
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.isaligned_in
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.msb_in_r
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.inc_waddr
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.waddr[4:0]
@200
-
@1401200
-elastic_phy
@c00200
-elastic_slow
@200
-
@28
tb_ahci.elastic1632_slow_i.wclk
tb_ahci.elastic1632_slow_i.rclk
[color] 3
tb_ahci.elastic1632_fast_i.rclk
tb_ahci.elastic1632_slow_i.is_alignp_w
tb_ahci.elastic1632_slow_i.charisk_in[1:0]
tb_ahci.elastic1632_slow_i.isaligned_in
tb_ahci.elastic1632_slow_i.aligned32_in_r
@22
[color] 3
tb_ahci.elastic1632_slow_i.dbg_di[31:0]
tb_ahci.elastic1632_slow_i.data_out[31:0]
tb_ahci.elastic1632_slow_i.charisk_out[3:0]
@28
tb_ahci.elastic1632_slow_i.isaligned_out
tb_ahci.elastic1632_slow_i.empty
tb_ahci.elastic1632_slow_i.full
tb_ahci.elastic1632_slow_i.msb_in_r
@c00022
tb_ahci.elastic1632_slow_i.fill_out[15:0]
@28
(0)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(1)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(2)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(3)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(4)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(5)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(6)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(7)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(8)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(9)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(10)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(11)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(12)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(13)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(14)tb_ahci.elastic1632_slow_i.fill_out[15:0]
(15)tb_ahci.elastic1632_slow_i.fill_out[15:0]
@1401200
-group_end
@c00022
tb_ahci.elastic1632_slow_i.fill[15:0]
@28
(0)tb_ahci.elastic1632_slow_i.fill[15:0]
(1)tb_ahci.elastic1632_slow_i.fill[15:0]
(2)tb_ahci.elastic1632_slow_i.fill[15:0]
(3)tb_ahci.elastic1632_slow_i.fill[15:0]
(4)tb_ahci.elastic1632_slow_i.fill[15:0]
(5)tb_ahci.elastic1632_slow_i.fill[15:0]
(6)tb_ahci.elastic1632_slow_i.fill[15:0]
(7)tb_ahci.elastic1632_slow_i.fill[15:0]
(8)tb_ahci.elastic1632_slow_i.fill[15:0]
(9)tb_ahci.elastic1632_slow_i.fill[15:0]
(10)tb_ahci.elastic1632_slow_i.fill[15:0]
(11)tb_ahci.elastic1632_slow_i.fill[15:0]
(12)tb_ahci.elastic1632_slow_i.fill[15:0]
(13)tb_ahci.elastic1632_slow_i.fill[15:0]
(14)tb_ahci.elastic1632_slow_i.fill[15:0]
(15)tb_ahci.elastic1632_slow_i.fill[15:0]
@1401200
-group_end
@28
tb_ahci.elastic1632_slow_i.dbg_dav1
@800022
tb_ahci.elastic1632_slow_i.aligned_rclk[2:0]
@28
(0)tb_ahci.elastic1632_slow_i.aligned_rclk[2:0]
(1)tb_ahci.elastic1632_slow_i.aligned_rclk[2:0]
(2)tb_ahci.elastic1632_slow_i.aligned_rclk[2:0]
@1001200
-group_end
@800022
tb_ahci.elastic1632_slow_i.dav_rclk[1:0]
@28
(0)tb_ahci.elastic1632_slow_i.dav_rclk[1:0]
(1)tb_ahci.elastic1632_slow_i.dav_rclk[1:0]
@1001200
-group_end
@22
tb_ahci.elastic1632_slow_i.full_0[1:0]
tb_ahci.elastic1632_slow_i.full_1[1:0]
@28
tb_ahci.elastic1632_slow_i.align_out
tb_ahci.elastic1632_slow_i.correct
@800028
tb_ahci.elastic1632_slow_i.correct_r[2:0]
@28
(0)tb_ahci.elastic1632_slow_i.correct_r[2:0]
(1)tb_ahci.elastic1632_slow_i.correct_r[2:0]
(2)tb_ahci.elastic1632_slow_i.correct_r[2:0]
@1001200
-group_end
@28
tb_ahci.elastic1632_slow_i.skip_rclk
tb_ahci.elastic1632_slow_i.skip_rclk2
@8022
tb_ahci.elastic1632_slow_i.waddr[4:0]
tb_ahci.elastic1632_slow_i.raddr_r[4:0]
tb_ahci.elastic1632_slow_i.dbg_diff[4:0]
@1401200
-elastic_slow
@c00200
-elastic_fast
@200
-
@28
tb_ahci.elastic1632_fast_i.wclk
tb_ahci.elastic1632_fast_i.rclk
tb_ahci.elastic1632_fast_i.is_alignp_w
@22
tb_ahci.elastic1632_fast_i.data_in[15:0]
tb_ahci.elastic1632_fast_i.charisk_in[1:0]
@c00022
tb_ahci.elastic1632_fast_i.charisk_in_r[1:0]
@28
(0)tb_ahci.elastic1632_fast_i.charisk_in_r[1:0]
(1)tb_ahci.elastic1632_fast_i.charisk_in_r[1:0]
@1401200
-group_end
@28
tb_ahci.elastic1632_fast_i.isaligned_in
@22
[color] 3
tb_ahci.elastic1632_fast_i.dbg_di[31:0]
tb_ahci.elastic1632_fast_i.data_out[31:0]
tb_ahci.elastic1632_fast_i.charisk_out[3:0]
@28
tb_ahci.elastic1632_fast_i.isaligned_out
tb_ahci.elastic1632_fast_i.empty
tb_ahci.elastic1632_fast_i.full
tb_ahci.elastic1632_fast_i.msb_in_r
@22
tb_ahci.elastic1632_fast_i.aligned_rclk[2:0]
@c00022
tb_ahci.elastic1632_fast_i.dav_rclk[1:0]
@28
(0)tb_ahci.elastic1632_fast_i.dav_rclk[1:0]
(1)tb_ahci.elastic1632_fast_i.dav_rclk[1:0]
@1401200
-group_end
@22
tb_ahci.elastic1632_fast_i.full_0[1:0]
tb_ahci.elastic1632_fast_i.full_1[1:0]
@28
tb_ahci.elastic1632_fast_i.align_out
tb_ahci.elastic1632_fast_i.correct
tb_ahci.elastic1632_fast_i.skip_rclk
tb_ahci.elastic1632_fast_i.skip_rclk2
@800028
tb_ahci.elastic1632_fast_i.add_rclk_r[1:0]
@28
(0)tb_ahci.elastic1632_fast_i.add_rclk_r[1:0]
(1)tb_ahci.elastic1632_fast_i.add_rclk_r[1:0]
@1001200
-group_end
@c00028
tb_ahci.elastic1632_fast_i.correct_r[2:0]
@28
(0)tb_ahci.elastic1632_fast_i.correct_r[2:0]
(1)tb_ahci.elastic1632_fast_i.correct_r[2:0]
(2)tb_ahci.elastic1632_fast_i.correct_r[2:0]
@1401200
-group_end
@8022
tb_ahci.elastic1632_fast_i.waddr[4:0]
tb_ahci.elastic1632_fast_i.raddr_r[4:0]
tb_ahci.elastic1632_fast_i.dbg_diff[4:0]
@1401200
-elastic_fast
@c00200
-comma_align
@200
-
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.aligned_data[19:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.clk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma_detected
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma_match[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma_match_p[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma_match_prev[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma_n[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma_p[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.indata[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.indata_r[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.outdata[19:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.realign
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.rst
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.shifted_window[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.window[38:0]
@1401200
-comma_align
@c00200
-debug_cominit
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.TXCOMINIT
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.TXCOMFINISH
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.txcominit
@200
-
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSSTS_r[11:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.cominit_got
tb_ahci.dut.sata_top.ahci_top_i.comreset_send
@1401200
-debug_cominit
@c00200
-debug_hba_reset
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.RXOOBRESET
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.GTRXRESET
@200
-
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.clk_reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.RXRESETDONE
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxuserrdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txresetdone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxresetdone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txuserrdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.sata_reset_done
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxeyereset_done
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txpmareset_done
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.usrpll_locked
@200
-
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxresetdone_gtx
@1401200
-debug_hba_reset
@800200
-oob_ctrl
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.gtx_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxcominitdet_in
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxcominitdet
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxcominit_done
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxcominitdet_l
@200
-
@800200
-oob
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.txelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.txcominit
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.txcomwake
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxelecidle_in
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxelecidle
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.eidle_timer[7:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.eidle_timer_done
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxreset_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rxreset_ack
@29
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.was_rxelecidle_waiting_reset
@800200
-states
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_idle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_cominit
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_comwake
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_recal_tx
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_eidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_rxrst
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_align
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_clk_align
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_align2
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_synp
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_linkup
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.dbg_clk_align_wait
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.clk_phase_align_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.clk_phase_align_ack
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.dbg_rx_clocks_aligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.dbg_rxphaligndone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.phy_ready
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.dbg_clk_align_cntr[15:0]
@1000200
-states
@200
-
@1000200
-oob
-oob_ctrl
@c00200
-sipo_meas
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.RXDATA[63:0]
tb_ahci.read_sipo_meas.duration[15:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.clocking.RXOUTCLK
@22
tb_ahci.read_sipo_meas.mask[31:0]
@28
tb_ahci.read_sipo_meas.running
@22
tb_ahci.read_sipo_meas.early_count[14:0]
tb_ahci.read_sipo_meas.late_count[14:0]
tb_ahci.drp_read.addr[14:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_addr[14:0]
@c00028
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_en_w[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_en_w[1:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_en_w[1:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_en
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_rdy_gtx
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_rdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_sel[1:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.RXOUTCLK
@c00200
-tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control
@1401200
-group_end
@200
-
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxreset
@1401200
-sipo_meas
@c00200
-gtx
-elastic
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.dbg_di[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.data_out[31:0]
@8022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.dbg_diff[4:0]
@200
-
@1401200
-elastic
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_we
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_en
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_en
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_we
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPCLK
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPEN
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPWE
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPDI[15:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPDO[15:0]
@200
-
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.clk_phase_align_ack
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.clk_phase_align_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rx_clocks_aligned
@200
-
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxphaligndone1_r
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxphaligndone2_r
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxphaligndone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysresetdone
@c00200
-ttxdata_resynchro
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.arst
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_out[38:0]
@8028
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.waddr[2:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.raddr[2:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.rclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.re
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.rrst[1:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.srst
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.valid
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.wclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.we
@1401200
-ttxdata_resynchro
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resync_strobe
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resync_valid
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txuserrdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txpcsreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rx_clocks_aligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.state_triggered
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.state_aligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.set_aligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.set_triggered
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.clr_triggered
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxcominitdet
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.rx_oob.reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.xclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxcominitdet_gtx
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxcomwakedet_gtx
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxcominitdet
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxphaligndone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.rxcdrlock
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.rxdlysresetdone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.rxphaligndone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.RXPHALIGNDONE
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.RXPHALIGN
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.RXDLYSRESET
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.RXDLYSRESETDONE
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.RXELECIDLE
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.RXCDRLOCK
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.comma
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.wrap_rxreset_
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxbyteisaligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxresetdone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxresetdone_gtx
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.xclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.state_aligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.state_triggered
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdata_comma_in[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdata_comma_out[19:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.comma
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.realign
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cpllreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cplllock
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cplllockdetclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txelecidle_gtx
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resync_strobe
@200
-
@800200
-txdata_path
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.ll_data_in[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.to_phy_data[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.txdata_in[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.txdata_out[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txdata[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata[31:0]
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(18)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(19)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(20)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(21)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(22)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(23)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(24)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(25)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(26)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(27)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(28)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(29)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(30)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(31)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(32)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(33)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(34)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(35)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(36)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(37)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
(38)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
@1401200
-group_end
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resync_out[38:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_enc_in_r[15:0]
@1000200
-txdata_path
@800200
-gtx8x10enc
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.wrap_txreset_
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_8x10enc.rst
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_in[15:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txcharisk_enc_in[1:0]
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(18)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
(19)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
@1401200
-group_end
@1000200
-gtx8x10enc
@1401200
-gtx
@800200
-device
@820
tb_ahci.dev.DEV_TITLE[639:0]
@800200
-linkTransmitFIS
@22
tb_ahci.dev.dev2phy_data[31:0]
tb_ahci.dev.linkTransmitFIS.scrambler_value[31:0]
@820
tb_ahci.dev.linkTransmitFIS.rprim[111:0]
@22
tb_ahci.dev.linkTransmitFIS.cnt
tb_ahci.dev.DEV_DATA
@1000200
-linkTransmitFIS
@200
-
@820
tb_ahci.dev.linkMonitorFIS.rprim[111:0]
tb_ahci.dev.linkSendPrim.type[111:0]
@22
tb_ahci.dev.linkMonitorFIS.scrambler_value[31:0]
@200
-
@22
tb_ahci.dev.linkMonitorFIS.cnt
tb_ahci.dev.receive_id
tb_ahci.dev.receive_lock
tb_ahci.dev.receive_status
@28
tb_ahci.dev.phy_ready
@22
tb_ahci.dev.phy2dev_err[3:0]
tb_ahci.dev.linkMonitorFIS.rcv_ignore
tb_ahci.dev.linkMonitorFIS.rcv_stop
@800200
-dev_phy
@28
tb_ahci.dev.phy.rst_r
@22
tb_ahci.dev.phy.txdata[31:0]
tb_ahci.dev.phy.ll_data_out[31:0]
tb_ahci.dev.phy.ll_charisk_out[3:0]
tb_ahci.dev.phy.ll_data_in[31:0]
tb_ahci.dev.phy.ll_charisk_in[3:0]
tb_ahci.dev.phy.oob_dev.rxdata[31:0]
@800200
-dev_oob
@8022
tb_ahci.dev.phy.oob_dev.wait_timer[31:0]
@28
tb_ahci.dev.phy.oob_dev.aligndet
tb_ahci.dev.phy.oob_dev.recal_tx_done
@800024
tb_ahci.dev.phy.oob_dev.state[9:0]
@28
(0)tb_ahci.dev.phy.oob_dev.state[9:0]
(1)tb_ahci.dev.phy.oob_dev.state[9:0]
(2)tb_ahci.dev.phy.oob_dev.state[9:0]
(3)tb_ahci.dev.phy.oob_dev.state[9:0]
(4)tb_ahci.dev.phy.oob_dev.state[9:0]
(5)tb_ahci.dev.phy.oob_dev.state[9:0]
(6)tb_ahci.dev.phy.oob_dev.state[9:0]
(7)tb_ahci.dev.phy.oob_dev.state[9:0]
(8)tb_ahci.dev.phy.oob_dev.state[9:0]
(9)tb_ahci.dev.phy.oob_dev.state[9:0]
@1001200
-group_end
@28
tb_ahci.dev.phy.oob_dev.aligndet
tb_ahci.dev.phy.oob_dev.syncdet
@22
tb_ahci.dev.phy.oob_dev.txdata_out[31:0]
@28
tb_ahci.dev.phy.oob_dev.txelecidle
tb_ahci.dev.phy.oob_dev.elidle_rate_delay_elapsed
@200
-
@1000200
-dev_oob
@28
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.TXUSRCLK2
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.TXUSRCLK
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.serial_clk
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.serial_data
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.TXP
tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.TXN
@1000200
-dev_phy
@820
tb_ahci.dev.linkSendPrim.type[111:0]
@1000200
-device
[pattern_trace] 1
[pattern_trace] 0
x393_sata.bit
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