Commit 09c87c41 authored by Andrey Filippov's avatar Andrey Filippov

v13: tolerating elidle from device during comreset/cominit (when device changes data rate)

parent 2d285422
......@@ -2,7 +2,7 @@ com.elphel.store.context.iverilog=iverilog_@_TopModulesOther<-@\#\#@->iverilog_@
com.elphel.store.version.iverilog=1.1
eclipse.preferences.version=1
iverilog_@_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_@_GTKWaveSavFile=tb_ahci_01.sav
iverilog_@_GTKWaveSavFile=tb_ahci_06.sav
iverilog_@_GrepFindErrWarn=error|warning|sorry
iverilog_@_IcarusTopFile=tb/tb_ahci.tf
iverilog_@_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
......
......@@ -44,7 +44,10 @@
// All references to doc = to SerialATA_Revision_2_6_Gold.pdf
module oob_dev #(
parameter DATA_BYTE_WIDTH = 4,
parameter CLK_SPEED_GRADE = 2 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
parameter CLK_SPEED_GRADE = 2, // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
parameter TEST_ELIDLE = 2, // test transmitting eidle between data rates (number of times)
parameter ELIDLE_DELAY = 'h28, // 80, // counter cycles
parameter ELIDLE_DURATION = 'h80 // counter cycles
)
(
// sata clk = usrclk2
......@@ -83,15 +86,21 @@ localparam STATE_CALIBRATE = 4;
localparam STATE_COMWAKE = 5;
localparam STATE_RECAL = 55;
localparam STATE_SENDALIGN = 6;
localparam STATE_EIDLE_RATE = 65;
localparam STATE_READY = 7;
localparam STATE_PARTIAL = 8;
localparam STATE_SLUMBER = 9;
localparam STATE_REDUCESPEED = 10;
localparam STATE_ERROR = 11;
reg [31:0] rate_change_cntr;
reg was_txelecidle;
reg [9:0] state;
wire retry_interval_elapsed;
wire wait_interval_elapsed;
wire elidle_rate_delay_elapsed;
wire elidle_rate_duration_elapsed;
wire nocomwake;
wire [31:0] align;
wire [31:0] sync;
......@@ -110,9 +119,21 @@ always @ (posedge clk)
retry_timer <= rst | ~(state == STATE_AWAITCOMWAKE) ? 32'h0 : retry_timer + 1'b1;
reg [31:0] wait_timer;
assign wait_interval_elapsed = wait_timer == 32'd4096;
assign wait_interval_elapsed = wait_timer == 32'd4096;
assign elidle_rate_delay_elapsed = wait_timer == ELIDLE_DELAY;
always @ (posedge clk)
wait_timer <= rst | ~(state == STATE_SENDALIGN) ? 32'h0 : wait_timer + 1'b1;
reg [31:0] elidle_timer;
assign elidle_rate_duration_elapsed = elidle_timer == ELIDLE_DURATION;
always @ (posedge clk)
elidle_timer <= rst | ~(state == STATE_EIDLE_RATE) ? 32'h0 : elidle_timer + 1'b1;
always @ (posedge clk) begin
was_txelecidle <= txelecidle;
if (rst) rate_change_cntr <= 0;
else if (txelecidle && !was_txelecidle) rate_change_cntr <= rate_change_cntr + 1;
end
reg [31:0] data;
reg [3:0] isk;
......@@ -218,6 +239,7 @@ always @ (posedge clk)
end
STATE_SENDALIGN:
begin
txelecidle <= 1'b0;
data <= align;
isk <= 4'h1;
if (aligndet)
......@@ -225,9 +247,21 @@ always @ (posedge clk)
else
if (wait_interval_elapsed)
state <= STATE_ERROR;
else
else if ((rate_change_cntr < TEST_ELIDLE) && elidle_rate_delay_elapsed)
state <= STATE_EIDLE_RATE;
else
state <= STATE_SENDALIGN;
end
STATE_EIDLE_RATE:
begin
txelecidle <= 1'b1;
data <= 0; // align; // 'bz;
isk <= 4'h1;
if (elidle_rate_duration_elapsed)
state <= STATE_SENDALIGN;
end
STATE_READY:
begin
txelecidle <= 1'b0;
......
......@@ -223,7 +223,11 @@ always @ (posedge clk) begin
else rxdlysreset_r <= rxdlysreset_r << 1;
end
reg was_rxelecidle_waiting_reset;
always @ (posedge clk) begin
if (rst || set_wait_eidle) was_rxelecidle_waiting_reset <= 0;
else if (state_wait_rxrst && rxelecidle) was_rxelecidle_waiting_reset <= 1;
end
assign state_idle = ~state_wait_cominit &
~state_wait_comwake &
~state_wait_align &
......@@ -253,11 +257,17 @@ end
assign set_wait_cominit = state_idle & oob_start & ~cominit_req;
assign set_wait_comwake = state_idle & cominit_req_l & cominit_allow & rxcominit_done | state_wait_cominit & rxcominitdet_l & rxcominit_done;
assign set_recal_tx = state_wait_comwake & rxcomwakedet_l & rxcomwake_done;
assign set_wait_eidle = state_recal_tx & recal_tx_done;
///assign set_wait_eidle = state_recal_tx & recal_tx_done;
assign set_wait_eidle = (state_recal_tx & recal_tx_done) |
(rxelecidle &
(state_wait_align | state_wait_clk_align | state_wait_align2 | (state_wait_rxrst & rxreset_ack & was_rxelecidle_waiting_reset) ));
assign set_wait_rxrst = state_wait_eidle & eidle_timer_done;
assign set_wait_align = state_wait_rxrst & rxreset_ack;
assign set_wait_clk_align = state_wait_align & (detected_alignp_r);
assign set_wait_align2 = state_wait_clk_align & clk_phase_align_ack;
///assign set_wait_align = state_wait_rxrst & rxreset_ack;
///assign set_wait_clk_align = state_wait_align & (detected_alignp_r);
///assign set_wait_align2 = state_wait_clk_align & clk_phase_align_ack;
assign set_wait_align = state_wait_rxrst & rxreset_ack & ~rxelecidle;
assign set_wait_clk_align = state_wait_align & (detected_alignp_r) & ~rxelecidle;
assign set_wait_align2 = state_wait_clk_align & clk_phase_align_ack & ~rxelecidle;
......@@ -278,10 +288,18 @@ assign clr_wait_cominit = set_wait_comwake | set_error;
assign clr_wait_comwake = set_recal_tx | set_error;
assign clr_recal_tx = set_wait_eidle | set_error;
assign clr_wait_eidle = set_wait_rxrst | set_error;
assign clr_wait_rxrst = set_wait_align | set_error;
assign clr_wait_align = set_wait_clk_align | set_error;
assign clr_wait_clk_align = set_wait_align2 | set_error;
assign clr_wait_align2 = set_wait_synp | set_error;
///assign clr_wait_rxrst = set_wait_align | set_error;
assign clr_wait_rxrst = state_wait_rxrst & rxreset_ack;
///assign clr_wait_align = set_wait_clk_align | set_error;
///assign clr_wait_clk_align = set_wait_align2 | set_error;
///assign clr_wait_align2 = set_wait_synp | set_error;
assign clr_wait_align = set_wait_clk_align | set_error | rxelecidle;
assign clr_wait_clk_align = set_wait_align2 | set_error | rxelecidle;
assign clr_wait_align2 = set_wait_synp | set_error | rxelecidle;
assign clr_wait_synp = set_wait_linkup | set_error;
assign clr_wait_linkup = state_wait_linkup; //TODO not so important, but still have to trace 3 back-to-back non alignp primitives
assign clr_error = state_error;
......
......@@ -2,6 +2,6 @@
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
, .INIT_0C (256'h000000000000000000000000000000000000000001010012001000000001FFFE)
, .INIT_0C (256'h000000000000000000000000000000000000000001010013001000000001FFFE)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
......@@ -97,7 +97,7 @@
// RO: HBA Revision ID
localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__DFLT = 'h12;
localparam PCI_Header__RID__RID__DFLT = 'h13;
// RO: Base Class Code: 1 - Mass Storage Device
localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__MASK = 'hff000000;
......
......@@ -537,6 +537,8 @@
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter CMPRS_CHN_MASK = 4'hf, // specify wich compressor channels to use (disable some/all to make room for processing)
parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
parameter CMPRS_BASE_INC = 'h10,
......
......@@ -32,7 +32,8 @@ __status__ = "Development"
**** Modify next value for new file versions, re-run this file *****
"""
# Revision ID
RID = 0x012 # Revision ID: registering irq on/off in datascope, as if tag = 6/7
RID = 0x013 # Revision ID: tolerating elidle during OOB sequence (when device changes data rate)
#RID = 0x012 # Revision ID: registering irq on/off in datascope, as if tag = 6/7
#RID = 0x011 # Revision ID
VID = 0xfffe # What to use for non-PCI "vendorID"?
DID = 0x0001
......
......@@ -694,6 +694,7 @@ class x393sata(object):
if do_not_start:
print ('Run the following command to start the comand:')
print("mem.write_mem(sata.get_reg_address('HBA_PORT__PxCI'), 1)")
return
else:
self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__PxCI'), 1)
print("Command table data:")
......
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Sun Dec 11 04:31:36 2016
[*] Mon Dec 12 06:19:44 2016
[*]
[dumpfile] "/home/eyesis/git/elphel393/fpga-elphel/x393_sata/simulation/tb_ahci-20161210212639118.fst"
[dumpfile_mtime] "Sun Dec 11 04:27:34 2016"
[dumpfile_size] 13299181
[dumpfile] "/home/eyesis/git/elphel393/fpga-elphel/x393_sata/simulation/tb_ahci-20161210213129200.fst"
[dumpfile_mtime] "Sun Dec 11 04:32:24 2016"
[dumpfile_size] 13299182
[savefile] "/home/eyesis/git/elphel393/fpga-elphel/x393_sata/tb_ahci_01.sav"
[timestart] 0
[size] 1814 1171
[pos] 68 0
*-24.068264 37475728 32882854 55953880 57700372 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 35400000
[size] 1814 1167
[pos] 85 51
*-21.899609 46000000 42208588 49301212 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev.
[treeopen] tb_ahci.dev.linkMonitorFIS.
[treeopen] tb_ahci.dev.linkTransmitFIS.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.
......@@ -61,10 +60,10 @@
[treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.
[treeopen] tb_ahci.simul_axi_read_i.
[sst_width] 311
[signals_width] 312
[sst_width] 466
[signals_width] 459
[sst_expanded] 1
[sst_vpaned_height] 485
[sst_vpaned_height] 483
@820
tb_ahci.TESTBENCH_TITLE[639:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0]
......@@ -1709,7 +1708,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g
-drp
@1401200
-axi_ahci_regs
@c00200
@800200
-ahci_fsm
@28
tb_ahci.dut.sata_top.ahci_top_i.hba_arst
......@@ -2002,9 +2001,130 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
@1401200
@1000200
-ahci_fsm
@800200
-missing_irq
@28
tb_ahci.dut.irq
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ghc_ie
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ghc_is_r
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
@28
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(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq[31:0]
@1401200
-group_end
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
@1401200
-group_end
@c00023
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
@1401201
-group_end
@200
-
@1000200
-missing_irq
@800200
-ahci_fis_receive
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in[31:0]
......@@ -5379,12 +5499,49 @@ tb_ahci.dev.linkSendPrim.type[111:0]
@800200
-datascope
@28
tb_ahci.dut.sata_top.ahci_top_i.datascope_we
@c00022
tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.irq
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.irq_r
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.irq_was
@29
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.we_irq
@28
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.we_r
@22
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.h2d_nready_cntr[7:0]
......
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Thu Apr 13 20:11:17 2017
[*]
[dumpfile] "/home/eyesis/git/elphel393/fpga-elphel/x393_sata/simulation/tb_ahci-20170413140803914.fst"
[dumpfile_mtime] "Thu Apr 13 20:08:56 2017"
[dumpfile_size] 13252819
[savefile] "/home/eyesis/git/elphel393/fpga-elphel/x393_sata/tb_ahci_06.sav"
[timestart] 0
[size] 1814 1171
[pos] 0 51
*-23.996487 12744868 42208588 49301212 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev.
[treeopen] tb_ahci.dev.linkMonitorFIS.
[treeopen] tb_ahci.dev.linkTransmitFIS.
[treeopen] tb_ahci.dev.phy.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.dataiface.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.
[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.ser.
[treeopen] tb_ahci.dev.phy.oob_dev.
[treeopen] tb_ahci.dut.
[treeopen] tb_ahci.dut.axi_hp_clk_i.
[treeopen] tb_ahci.dut.sata_top.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.crc.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.dataiface.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.tx.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.ahci_dma_rd_stuff_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.
[treeopen] tb_ahci.elastic1632_fast_i.
[treeopen] tb_ahci.elastic1632_slow_i.
[treeopen] tb_ahci.read_sipo_meas.
[treeopen] tb_ahci.simul_axi_hp_rd_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.
[treeopen] tb_ahci.simul_axi_read_i.
[sst_width] 289
[signals_width] 276
[sst_expanded] 1
[sst_vpaned_height] 608
@820
tb_ahci.TESTBENCH_TITLE[639:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0]
tb_ahci.DEVICE_TITLE[639:0]
@c00820
tb_ahci.dev.DEV_TITLE[639:0]
@28
(0)tb_ahci.dev.DEV_TITLE[639:0]
(1)tb_ahci.dev.DEV_TITLE[639:0]
(2)tb_ahci.dev.DEV_TITLE[639:0]
(3)tb_ahci.dev.DEV_TITLE[639:0]
(4)tb_ahci.dev.DEV_TITLE[639:0]
(5)tb_ahci.dev.DEV_TITLE[639:0]
(6)tb_ahci.dev.DEV_TITLE[639:0]
(7)tb_ahci.dev.DEV_TITLE[639:0]
(8)tb_ahci.dev.DEV_TITLE[639:0]
(9)tb_ahci.dev.DEV_TITLE[639:0]
(10)tb_ahci.dev.DEV_TITLE[639:0]
(11)tb_ahci.dev.DEV_TITLE[639:0]
(12)tb_ahci.dev.DEV_TITLE[639:0]
(13)tb_ahci.dev.DEV_TITLE[639:0]
(14)tb_ahci.dev.DEV_TITLE[639:0]
(15)tb_ahci.dev.DEV_TITLE[639:0]
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