Update Readme for current state

2. ssh-copy-id user@ip  

# Swtich between synthesis & simulation

See update below

Edit *.editor_defines*:

* simulation:

  `define SIMULATION 1

Refresh the project and update hierarchy (or rescan)

**Update:** Not needed anymore with updated VDT plugin - it now calculates closure per-tool and per-top file defines,

so *.editor_defines* is now just for the editor (which branches to parse). No refresh/rescan is required.

# Simulation

* Get unisims library - refresh project files otherwise nothing will work  

* Add constraints file through Synthesis parameters

* Bitstream Tool parameters - check *Force(overwrite)*

# Current step:

# Current step in try2 branch:

Not yet tested in hardware, started AHCI implementation (currently coded registers and DMA engine, that processes command table/PRD list,

Transfers data between clock domains, re-aligns between WORD size granularity, HAB 32-bit data and 64-bit AFI accesses.

# Current step in main branch:

Testing basic functionallity of a host.  

Trying out pio access.  

Fullfilling device-side drivers and monitors via tasks.