test_top.v 7.03 KB
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/*******************************************************************************
 * Module: tb
 * Date: 2015-07-11  
 * Author: Alexey     
 * Description: dut inputs control for for tb_top.v
 *
 * Copyright (c) 2015 Elphel, Inc.
 * test_top.v is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * test_top.v file is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/> .
 *******************************************************************************/
/*
 * this file is included into tb_top.v due to the compatibility with x393 design testbench
 */

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// external clock to gtx

always #3.333
begin
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    EXTCLK_P = ~EXTCLK_P;
    EXTCLK_N = ~EXTCLK_N;
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end

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integer i;
integer status;
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integer id;
reg [31:0] data;
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// write registers
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initial
begin
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//    CLK =1'b0;
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    RST = 1'bx;
    AR_SET_CMD_r = 1'b0;
    AW_SET_CMD_r = 1'b0;
    W_SET_CMD_r = 1'b0;
    #500;
//    $display ("x393_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.rst=%d",x393_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.rst);
    #500;
    RST = 1'b1;
    NUM_WORDS_EXPECTED =0;
//    #99000; // same as glbl
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    #900; // same as glbl
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    repeat (20) @(posedge EXTCLK_P) ;
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    RST =1'b0;
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    @ (negedge dut.sata_top.sata_rst);
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    repeat (20) 
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        @ (posedge dev.clk);
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// test MAXI1 inface
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    axi_set_rd_lag(0);
    axi_write_single(32'h4, 32'hdeadbeef);
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//    axi_read_addr(12'h777, 32'h4, 4'h3, 2'b01);
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    repeat (7) 
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        @ (posedge dev.clk);
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    axi_write_single(32'h8, 32'hd34db33f);
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//    axi_read_addr(12'h555, 32'h0, 4'h3, 2'b01);
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    for (i = 0; i < 2048; i = i + 1) begin
        dev.receive_data_pause[i] = 32'h0;
    end
    dev.receive_wait_fifo = 0;

// issue Identify Device command
    // ATAPI command id = EC
    axi_write_single({30'h5, 2'b00}, 32'hEC);
    // start!
    axi_write_single({30'hf, 2'b00}, 32'h0108);
    $display("[Test] H2D Reg with pio cmd issued");
    // wait until reception
    while (dev.receive_id != 1) begin
        repeat (100)
            @ (posedge dev.clk);
    end

    if (dev.receive_status != 0) begin
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        $display("[Test] Failed");
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        $finish;
    end

    $display("[Test] H2D Reg with pio cmd received by dev");
    // send dev2host reg fis with BSY flag
    repeat (100)
        @ (posedge dev.clk);
    for (i = 0; i < 2048; i = i + 1) begin
        dev.transmit_data_pause[i] = 32'h0;
    end
    dev.transmit_data[0] = 32'h00800034; // BSY -> 1, type = dev2host reg
    dev.transmit_data[1] = 32'hdeadbeef; // whatever
    dev.transmit_data[2] = 32'hdeadbeef; // whatever
    dev.transmit_data[3] = 32'hdeadbeef; // whatever
    dev.transmit_data[4] = 32'hdeadbeef; // whatever

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    dev.linkTransmitFIS(66, 5, 0, status);
    if (status != 0) begin
        $display("[Test] Failed");
        $finish;
    end
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    $display("[Test] Dev sent BSY flag");

    // checks if BSY is set up // only on waves TODO
    axi_read_addr(12'h555, {30'h11, 2'b00}, 4'h3, 2'b01);
    repeat (50)
        @ (posedge dev.clk);

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    $display("[Test] Device sends PIO Setup");
    dev.transmit_data[0] = 32'h0080205f; // direction d2h, type = 5f
    dev.transmit_data[1] = 32'hdeadbeef; // whatever
    dev.transmit_data[2] = 32'hdeadbeef; // whatever
    dev.transmit_data[3] = 32'h00adbeef; // whatever
    dev.transmit_data[4] = 32'h00000014; // let it be 20 bytes to be transfered
    dev.linkTransmitFIS(11, 5, 0, status);
    if (status != 0) begin
        $display("[Test] Failed");
        $finish;
    end

    $display("[Test] Device sends data FIS");
    dev.transmit_data[0] = 32'h00000046; // type = 46
    dev.transmit_data[1] = 32'hfeeddeaf;
    dev.transmit_data[2] = 32'ha114bea7;
    dev.transmit_data[3] = 32'hca110911;
    dev.transmit_data[4] = 32'hCA715F1E;
    dev.transmit_data[5] = 32'hdeadbeef;
    dev.linkTransmitFIS(22, 6, 0, status);
    if (status != 0) begin
        $display("[Test] Failed");
        $finish;
    end

    repeat (20)
        @ (posedge dev.clk);

    // prepare monitor - clean it before actual usage
    while (~maxiMonitorIsEmpty(0)) begin
        maxiMonitorPop(data, id);
    end
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    // imitating PIO reads
    $display("[Test] Read data word 0");
    axi_read_addr(12'h660, {30'h00, 2'b00}, 4'h0, 2'b01);

    $display("[Test] Read data word 1");
    axi_read_addr(12'h661, {30'h00, 2'b00}, 4'h0, 2'b01);
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    $display("[Test] Read data word 2");
    axi_read_addr(12'h662, {30'h00, 2'b00}, 4'h0, 2'b01);
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    $display("[Test] Read data word 3");
    axi_read_addr(12'h663, {30'h00, 2'b00}, 4'h0, 2'b01);
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    $display("[Test] Read data word 4");
    axi_read_addr(12'h664, {30'h00, 2'b00}, 4'h0, 2'b01);
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    // check if all ok
    i = 0;
    while (~maxiMonitorIsEmpty(0)) begin
        maxiMonitorPop(data, id);
        if (dev.transmit_data[i] != data) begin
            $display("[Test] Data check failed");
            $finish;
        end
        i = i + 1;
    end
    $display("[Test] Data check OK");
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    repeat (30) 
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        @ (posedge dev.clk);

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/*    for (i = 0; i < 32; i = i + 1) begin
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        $display("data received : %h", dev.receive_data[i]);
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    end*/
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    $display("============= DONE =============");
    $finish;
    
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// test SAXI3 iface
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/*    afi_setup(3);
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    axi_write_single(32'h10, 32'h0add9e55); // addr
    axi_write_single(32'h14, 32'h12345678); // lba
    axi_write_single(32'h18, 32'h00000020); // sector count
    axi_write_single(32'h20, 32'h00100000); // dma type
    axi_write_single(32'h24, 32'h00010000); // start
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    axi_write_single(32'h28, 32'hdeadbee2); // data
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    axi_write_single(32'h2c, 32'hdeadbee3); // data
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    axi_write_single(32'h1c, 32'hffffffff); // start */
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end
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/*
// control the device
reg [112:0] rprim;
integer status;
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initial
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begin
    @ (posedge dev.phy_ready);
    repeat (30)
        @ (posedge dev.clk);
    dev.linkSendPrim("XRDY");
    rprim = dev.linkGetPrim(0);
    while (rprim != "RRDY") begin
        if (rprim != "SYNC") begin
            $display("Expected SYNC primitive, got %8s", rprim);
            $finish;
        end
        @ (posedge dev.clk)
            rprim = dev.linkGetPrim(0);
    end
    dev.linkSendPrim("SYNC");
    repeat (30)
        @ (posedge dev.clk);
    for (i = 0; i < 2048; i = i + 1) begin
        dev.transmit_data[i] = 32'hdeadbeef;
        dev.transmit_data_pause[i] = 32'h0;
    end
//    dev.transmit_crc = 32'hfd60f8a6;
    dev.transmit_crc = 32'hfd60f8a5;
    dev.linkTransmitFIS(66, 12, status);
    $display("Fis %d transmitted, status %d", 66, status);


    repeat (1000) 
        @ (posedge dev.clk);
    $display("============= DONE =============");
    $finish;
end
*/
initial begin
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    #150000;
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    $display("[Test] Failed");
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    $display("============= TIMELIMIT =============");
    $finish;
end