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.settings testing hardware, adding related code
axi working on synthesis with Vivado tools
ddr3 debugging/simulation
docs Description of the memory controller clocks and programmable delays
hardware_tests eye pattern tests at 400MHz
includes chaneged handling of the shared parameters, added defaults and saving modified parameters as Verilog include file
memctrl porting delay scan/adjustment functions from the eddr3 Python code
py393 Split py393/x393_mcntrl_adjust.py
python code to align bit delays on random data
simulation_modules debugging, more corrections, tested write levelling/buffer reading
unisims_patches patch to work with Icarus Verilog simulator
util_modules working on synthesis with Vivado tools
wrap working with hardware
.editor_defines.vh working on synthesis with Vivado tools
.gitignore working on Python code for hardware testing
.project testing hardware, adding related code
.pydevproject organized new/debug files
OSERDESE1.diff Modifications for Icarus Verilog
README.md more changes to convert project
address_map.txt before adding extra register layer between channel buffers outputs and memory controller
cmd_mux.v before adding extra register layer between channel buffers outputs and memory controller
ddrc_test01.xcf added configuration for ISE, timing constraints for Vivado
ddrc_test01.xdc troubleshooting lack of DONE during loading of the bitfile
ddrc_test01_testbench.sav more changes to convert project
ddrc_test01_timing.xdc troubleshooting lack of DONE during loading of the bitfile
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system_defines.vh Loading commit data...
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