[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Fri Feb 13 00:32:14 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150212171214320.lxt"
[dumpfile_mtime] "Fri Feb 13 00:16:41 2015"
[dumpfile_size] 226686145
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 141310400
[size] 1823 1173
[pos] 1922 0
*-14.698502 141381875 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.x393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
[sst_width] 328
[signals_width] 377
[sst_expanded] 1
[sst_vpaned_height] 371
@800200
-top_simulation
@28
x393_testbench01.CLK[0]
x393_testbench01.WAITING_STATUS[0]
x393_testbench01.AXI_RD_EMPTY[0]
x393_testbench01.SIMUL_AXI_EMPTY[0]
x393_testbench01.SIMUL_AXI_FULL[0]
@22
x393_testbench01.SIMUL_AXI_ADDR[15:0]
x393_testbench01.SIMUL_AXI_READ[31:0]
@c00200
-top_extra
@22
x393_testbench01.NUM_WORDS_READ[31:0]
x393_testbench01.NUM_WORDS_EXPECTED[31:0]
@28
x393_testbench01.rstb[0]
@22
x393_testbench01.rdata[31:0]
x393_testbench01.SIMUL_AXI_ADDR_W[15:0]
@c00022
x393_testbench01.registered_rdata[31:0]
@28
(0)x393_testbench01.registered_rdata[31:0]
(1)x393_testbench01.registered_rdata[31:0]
(2)x393_testbench01.registered_rdata[31:0]
(3)x393_testbench01.registered_rdata[31:0]
(4)x393_testbench01.registered_rdata[31:0]
(5)x393_testbench01.registered_rdata[31:0]
(6)x393_testbench01.registered_rdata[31:0]
(7)x393_testbench01.registered_rdata[31:0]
(8)x393_testbench01.registered_rdata[31:0]
(9)x393_testbench01.registered_rdata[31:0]
(10)x393_testbench01.registered_rdata[31:0]
(11)x393_testbench01.registered_rdata[31:0]
(12)x393_testbench01.registered_rdata[31:0]
(13)x393_testbench01.registered_rdata[31:0]
(14)x393_testbench01.registered_rdata[31:0]
(15)x393_testbench01.registered_rdata[31:0]
(16)x393_testbench01.registered_rdata[31:0]
(17)x393_testbench01.registered_rdata[31:0]
(18)x393_testbench01.registered_rdata[31:0]
(19)x393_testbench01.registered_rdata[31:0]
(20)x393_testbench01.registered_rdata[31:0]
(21)x393_testbench01.registered_rdata[31:0]
(22)x393_testbench01.registered_rdata[31:0]
(23)x393_testbench01.registered_rdata[31:0]
(24)x393_testbench01.registered_rdata[31:0]
(25)x393_testbench01.registered_rdata[31:0]
(26)x393_testbench01.registered_rdata[31:0]
(27)x393_testbench01.registered_rdata[31:0]
(28)x393_testbench01.registered_rdata[31:0]
(29)x393_testbench01.registered_rdata[31:0]
(30)x393_testbench01.registered_rdata[31:0]
(31)x393_testbench01.registered_rdata[31:0]
@1401200
-group_end
@22
x393_testbench01.read_and_wait_status.address[7:0]
x393_testbench01.x393_i.status_rdata[31:0]
x393_testbench01.x393_i.axird_rdata[31:0]
x393_testbench01.target_phase[7:0]
x393_testbench01.read_and_wait_status.address[7:0]
@1401200
-top_extra
@c00200
-read_block_buf_chn
@22
x393_testbench01.read_block_buf_chn.chn[31:0]
x393_testbench01.read_block_buf_chn.num_read[31:0]
@28
x393_testbench01.read_block_buf_chn.page[1:0]
@22
x393_testbench01.read_block_buf_chn.start_addr[29:0]
@1401200
-read_block_buf_chn
@c00200
-simul_axi_read
@28
x393_testbench01.simul_axi_read_i.burst[0]
x393_testbench01.simul_axi_read_i.burst_r[0]
x393_testbench01.simul_axi_read_i.clk[0]
x393_testbench01.simul_axi_read_i.data_stb[0]
x393_testbench01.simul_axi_read_i.err_out[0]
x393_testbench01.simul_axi_read_i.error_w[0]
x393_testbench01.simul_axi_read_i.fifo_in_rdy[0]
x393_testbench01.simul_axi_read_i.fifo_valid[0]
x393_testbench01.simul_axi_read_i.generated_last[0]
x393_testbench01.simul_axi_read_i.last[0]
@22
x393_testbench01.simul_axi_read_i.left_plus_1[3:0]
@28
x393_testbench01.simul_axi_read_i.rcmd[0]
x393_testbench01.simul_axi_read_i.reset[0]
@22
x393_testbench01.simul_axi_read_i.rlen[3:0]
x393_testbench01.simul_axi_read_i.rlen_fifo[3:0]
@28
x393_testbench01.simul_axi_read_i.start_burst[0]
@1401200
-simul_axi_read
@c00200
-WAIT_STATUS_CONDITION
@28
x393_testbench01.wait_status_condition.invert_match[0]
@22
x393_testbench01.wait_status_condition.mask[25:0]
@28
x393_testbench01.wait_status_condition.match[0]
@22
x393_testbench01.wait_status_condition.pattern[25:0]
x393_testbench01.wait_status_condition.seq_num[5:0]
x393_testbench01.wait_status_condition.status_address[7:0]
x393_testbench01.wait_status_condition.status_control_address[29:0]
@28
x393_testbench01.wait_status_condition.status_mode[1:0]
@1401200
-WAIT_STATUS_CONDITION
@1000200
-top_simulation
@200
-
@c00200
-axi
@28
x393_testbench01.x393_i.axi_aclk[0]
@22
x393_testbench01.x393_i.axi_araddr[31:0]
@28
x393_testbench01.x393_i.axi_arburst[1:0]
@22
x393_testbench01.x393_i.axi_arid[11:0]
x393_testbench01.x393_i.axi_arlen[3:0]
@28
x393_testbench01.x393_i.axi_arready[0]
x393_testbench01.x393_i.axi_arsize[1:0]
x393_testbench01.x393_i.axi_arvalid[0]
@22
x393_testbench01.x393_i.axi_awaddr[31:0]
@28
x393_testbench01.x393_i.axi_awburst[1:0]
@22
x393_testbench01.x393_i.axi_awid[11:0]
x393_testbench01.x393_i.axi_awlen[3:0]
@28
x393_testbench01.x393_i.axi_awready[0]
x393_testbench01.x393_i.axi_awsize[1:0]
x393_testbench01.x393_i.axi_awvalid[0]
@22
x393_testbench01.x393_i.axi_bid[11:0]
@28
x393_testbench01.x393_i.axi_bready[0]
x393_testbench01.x393_i.axi_bresp[1:0]
x393_testbench01.x393_i.axi_bvalid[0]
@22
x393_testbench01.x393_i.axi_rdata[31:0]
x393_testbench01.x393_i.axi_rid[11:0]
@28
x393_testbench01.x393_i.axi_rlast[0]
x393_testbench01.x393_i.axi_rready[0]
x393_testbench01.x393_i.axi_rresp[1:0]
x393_testbench01.x393_i.axi_rst[0]
x393_testbench01.x393_i.axi_rst_pre[0]
x393_testbench01.x393_i.axi_rvalid[0]
@22
x393_testbench01.x393_i.axi_wdata[31:0]
x393_testbench01.x393_i.axi_wid[11:0]
@28
x393_testbench01.x393_i.axi_wlast[0]
x393_testbench01.x393_i.axi_wready[0]
@22
x393_testbench01.x393_i.axi_wstb[3:0]
@28
x393_testbench01.x393_i.axi_wvalid[0]
x393_testbench01.x393_i.axird_bram_rclk[0]
x393_testbench01.x393_i.axird_dev_busy[0]
x393_testbench01.x393_i.axird_dev_ready[0]
@22
x393_testbench01.x393_i.axird_pre_araddr[12:0]
x393_testbench01.x393_i.axird_raddr[12:0]
x393_testbench01.x393_i.axird_rdata[31:0]
@28
x393_testbench01.x393_i.axird_regen[0]
x393_testbench01.x393_i.axird_ren[0]
x393_testbench01.x393_i.axird_start_burst[0]
@22
x393_testbench01.x393_i.axiwr_bram_wstb[3:0]
@28
x393_testbench01.x393_i.axiwr_dev_busy[0]
x393_testbench01.x393_i.axiwr_dev_ready[0]
@22
x393_testbench01.x393_i.axiwr_pre_awaddr[12:0]
@28
x393_testbench01.x393_i.axiwr_start_burst[0]
@22
x393_testbench01.x393_i.axiwr_waddr[12:0]
@28
x393_testbench01.x393_i.axiwr_wclk[0]
@22
x393_testbench01.x393_i.axiwr_wdata[31:0]
@28
x393_testbench01.x393_i.axiwr_wen[0]
@1401200
-axi
@c00200
-cmd_mux
@22
x393_testbench01.x393_i.cmd_root_ad[7:0]
@28
x393_testbench01.x393_i.cmd_root_stb[0]
x393_testbench01.x393_i.cmd_mux_i.ad_stb[0]
x393_testbench01.x393_i.cmd_mux_i.ad_stb_r[0]
x393_testbench01.x393_i.cmd_mux_i.axi_clk[0]
x393_testbench01.x393_i.cmd_mux_i.busy[0]
x393_testbench01.x393_i.cmd_mux_i.busy_r[0]
@22
x393_testbench01.x393_i.cmd_mux_i.byte_ad[7:0]
@28
x393_testbench01.x393_i.cmd_mux_i.can_start_w[0]
x393_testbench01.x393_i.cmd_mux_i.cmdseq_full_r[0]
x393_testbench01.x393_i.cmd_mux_i.cseq_ackn[0]
@22
x393_testbench01.x393_i.cmd_mux_i.cseq_waddr[12:0]
x393_testbench01.x393_i.cmd_mux_i.cseq_waddr_r[12:0]
x393_testbench01.x393_i.cmd_mux_i.cseq_wdata[31:0]
x393_testbench01.x393_i.cmd_mux_i.cseq_wdata_r[31:0]
@28
x393_testbench01.x393_i.cmd_mux_i.cseq_wr_en[0]
x393_testbench01.x393_i.cmd_mux_i.fifo_half_empty[0]
x393_testbench01.x393_i.cmd_mux_i.fifo_nempty[0]
x393_testbench01.x393_i.cmd_mux_i.mclk[0]
@22
x393_testbench01.x393_i.cmd_mux_i.par_ad[47:0]
x393_testbench01.x393_i.cmd_mux_i.par_data[31:0]
x393_testbench01.x393_i.cmd_mux_i.par_waddr[12:0]
x393_testbench01.x393_i.cmd_mux_i.pre_waddr[12:0]
@28
x393_testbench01.x393_i.cmd_mux_i.rst[0]
x393_testbench01.x393_i.cmd_mux_i.selected[0]
x393_testbench01.x393_i.cmd_mux_i.selected_w[0]
@800022
x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0]
@28
(0)x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0]
(1)x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0]
(2)x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0]
(3)x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0]
(4)x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0]
@1001200
-group_end
@22
x393_testbench01.x393_i.cmd_mux_i.seq_length[3:0]
x393_testbench01.x393_i.cmd_mux_i.seq_length_rom_a[3:0]
@28
x393_testbench01.x393_i.cmd_mux_i.ss[0]
x393_testbench01.x393_i.cmd_mux_i.start_axi_w[0]
x393_testbench01.x393_i.cmd_mux_i.start_w[0]
x393_testbench01.x393_i.cmd_mux_i.start_wburst[0]
@22
x393_testbench01.x393_i.cmd_mux_i.waddr[12:0]
x393_testbench01.x393_i.cmd_mux_i.waddr_fifo_out[12:0]
x393_testbench01.x393_i.cmd_mux_i.wdata[31:0]
x393_testbench01.x393_i.cmd_mux_i.wdata_fifo_out[31:0]
@28
x393_testbench01.x393_i.cmd_mux_i.wr_en[0]
@1401200
-cmd_mux
@c00200
-status_read
@22
x393_testbench01.x393_i.status_read_i.ad[7:0]
@28
x393_testbench01.x393_i.status_read_i.axi_clk[0]
@22
x393_testbench01.x393_i.status_read_i.axi_status_rdata[31:0]
x393_testbench01.x393_i.status_read_i.axi_status_rdata_r[31:0]
x393_testbench01.x393_i.status_read_i.axird_pre_araddr[12:0]
x393_testbench01.x393_i.status_read_i.axird_raddr[7:0]
x393_testbench01.x393_i.status_read_i.axird_rdata[31:0]
@28
x393_testbench01.x393_i.status_read_i.axird_regen[0]
x393_testbench01.x393_i.status_read_i.axird_ren[0]
x393_testbench01.x393_i.status_read_i.axird_selected[0]
x393_testbench01.x393_i.status_read_i.axird_start_burst[0]
x393_testbench01.x393_i.status_read_i.clk[0]
@22
x393_testbench01.x393_i.status_read_i.dstb[3:0]
@28
x393_testbench01.x393_i.status_read_i.rd[0]
x393_testbench01.x393_i.status_read_i.regen[0]
x393_testbench01.x393_i.status_read_i.rq[0]
x393_testbench01.x393_i.status_read_i.rq_r[0]
x393_testbench01.x393_i.status_read_i.rst[0]
x393_testbench01.x393_i.status_read_i.select_d[0]
x393_testbench01.x393_i.status_read_i.select_r[0]
x393_testbench01.x393_i.status_read_i.select_w[0]
x393_testbench01.x393_i.status_read_i.start[0]
@22
x393_testbench01.x393_i.status_read_i.waddr[7:0]
x393_testbench01.x393_i.status_read_i.wdata[31:0]
@28
x393_testbench01.x393_i.status_read_i.we[0]
@1401200
-status_read
@c00200
-status_router_top
@28
x393_testbench01.x393_i.status_router2_top_i.chn_sel_w[0]
x393_testbench01.x393_i.status_router2_top_i.current_chn_r[0]
x393_testbench01.x393_i.status_router2_top_i.clk[0]
x393_testbench01.x393_i.status_router2_top_i.rq_in0[0]
x393_testbench01.x393_i.status_router2_top_i.start_in0[0]
@22
x393_testbench01.x393_i.status_router2_top_i.db_in0[7:0]
@28
x393_testbench01.x393_i.status_router2_top_i.rq_in1[0]
x393_testbench01.x393_i.status_router2_top_i.start_in1[0]
@22
x393_testbench01.x393_i.status_router2_top_i.db_in1[7:0]
@28
x393_testbench01.x393_i.status_router2_top_i.rq_out[0]
x393_testbench01.x393_i.status_router2_top_i.start_out[0]
@22
x393_testbench01.x393_i.status_router2_top_i.db_out[7:0]
@28
x393_testbench01.x393_i.status_router2_top_i.early_chn[0]
@22
x393_testbench01.x393_i.status_router2_top_i.fifo0_out[7:0]
x393_testbench01.x393_i.status_router2_top_i.fifo1_out[7:0]
@800028
x393_testbench01.x393_i.status_router2_top_i.fifo_half_full[1:0]
@28
(0)x393_testbench01.x393_i.status_router2_top_i.fifo_half_full[1:0]
(1)x393_testbench01.x393_i.status_router2_top_i.fifo_half_full[1:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.status_router2_top_i.fifo_last_byte[1:0]
x393_testbench01.x393_i.status_router2_top_i.fifo_nempty[1:0]
x393_testbench01.x393_i.status_router2_top_i.fifo_re[1:0]
x393_testbench01.x393_i.status_router2_top_i.next_chn[0]
@800028
x393_testbench01.x393_i.status_router2_top_i.rcv_rest_r[1:0]
@28
(0)x393_testbench01.x393_i.status_router2_top_i.rcv_rest_r[1:0]
(1)x393_testbench01.x393_i.status_router2_top_i.rcv_rest_r[1:0]
@1001200
-group_end
@c00028
x393_testbench01.x393_i.status_router2_top_i.rq_in[1:0]
@28
(0)x393_testbench01.x393_i.status_router2_top_i.rq_in[1:0]
(1)x393_testbench01.x393_i.status_router2_top_i.rq_in[1:0]
@1401200
-group_end
@28
x393_testbench01.x393_i.status_router2_top_i.rst[0]
x393_testbench01.x393_i.status_router2_top_i.snd_last_byte[0]
x393_testbench01.x393_i.status_router2_top_i.snd_pre_start[0]
x393_testbench01.x393_i.status_router2_top_i.snd_rest_r[0]
@800028
x393_testbench01.x393_i.status_router2_top_i.start_rcv[1:0]
@28
(0)x393_testbench01.x393_i.status_router2_top_i.start_rcv[1:0]
(1)x393_testbench01.x393_i.status_router2_top_i.start_rcv[1:0]
@1001200
-group_end
@1401200
-status_router_top
@c00200
-status_router16_mctrl_top
@28
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in0[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in1[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in2[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in3[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in4[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in5[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in6[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in7[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in8[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in9[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in10[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in11[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in12[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in13[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in14[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in15[7:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_out[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in0[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in1[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in2[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in3[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in4[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in5[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in6[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in7[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in8[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in9[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in10[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in11[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in12[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in13[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in14[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in15[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_int[1:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_out[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in0[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in1[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in2[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in3[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in4[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in5[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in6[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in7[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in8[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in9[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in10[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in11[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in12[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in13[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in14[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in15[0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_int[1:0]
x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_out[0]
@1401200
-status_router16_mctrl_top
@c00200
-memcntrl16_status_router2_top
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.chn_sel_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.current_chn_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.early_chn[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rq_in0[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.start_in0[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.db_in0[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rq_in1[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.start_in1[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.db_in1[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rq_out[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.start_out[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.db_out[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.snd_last_byte[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.snd_rest_r[0]
(1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty_pre[1:0]
(0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty_pre[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo0_out[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo1_out[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_half_full[1:0]
@800028
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_last_byte[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_last_byte[1:0]
(1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_last_byte[1:0]
@1001200
-group_end
@800028
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty[1:0]
(1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty[1:0]
@1001200
-group_end
@800028
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty_pre[1:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_re[1:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.next_chn[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rcv_rest_r[1:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rq_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.snd_pre_start[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.start_rcv[1:0]
@1401200
-memcntrl16_status_router2_top
@c00200
-mcontr_sequencer_status_generate
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.dly_ready[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.dci_ready[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.locked_mmcm[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.locked_pll[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_busy[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.locked[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ps_rdy[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ps_out[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.ad[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.aligned_status[17:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.cmd_pend[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.data[23:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.mode[1:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.mode_w[1:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.need_to_send[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.rq[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.rq_r[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.rst[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.seq[5:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.snd_rest[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.start[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.status[14:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.status_changed_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.status_r[14:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.wd[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.we[0]
@1401200
-mcontr_sequencer_status_generate
@c00200
-mcontr_cmd_deser_16bit
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.addr[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.data[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.stb[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.we[0]
@1401200
-mcontr_cmd_deser_16bit
@c00200
-mcont_cmd_deser_16bit_multi
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.addr[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.data[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.deser_r[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.match_high[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.match_low[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.rst[0]
@800028
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.sr[2:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.sr[2:0]
(1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.sr[2:0]
(2)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.sr[2:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.stb[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.stb_d[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.we[0]
@1401200
-mcont_cmd_deser_16bit_multi
@c00200
-test01_status_router4
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_in0[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_in1[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_in2[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_in3[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_out[7:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_in0[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_in1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_in2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_in3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_int[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_out[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rst[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_in0[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_in1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_in2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_in3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_int[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_out[0]
@1401200
-test01_status_router4
@c00200
-test01_status_router2_top
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.clk[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rq_in[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rq_in0[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.start_in0[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rq_in1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.start_in1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rq_out[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.chn_sel_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.start_out[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.current_chn_r[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.db_in0[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.db_in1[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.db_out[7:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.early_chn[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo0_out[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo1_out[7:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_half_full[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_last_byte[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_nempty[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_nempty_pre[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_re[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.next_chn[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rcv_rest_r[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rst[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.set_other_only_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.snd_last_byte[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.snd_pre_start[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.snd_rest_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.start_rcv[1:0]
@1401200
-test01_status_router2_top
@c00200
-test01_status_router2_01
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.chn_sel_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.clk[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.current_chn_r[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.db_in0[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.db_in1[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.db_out[7:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.early_chn[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo0_out[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo1_out[7:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_half_full[1:0]
@800028
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_last_byte[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_last_byte[1:0]
(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_last_byte[1:0]
@1001200
-group_end
@800028
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty[1:0]
(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty[1:0]
@1001200
-group_end
@800028
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty_pre[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty_pre[1:0]
(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty_pre[1:0]
@1001200
-group_end
@800028
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_re[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_re[1:0]
(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_re[1:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.next_chn[0]
@800028
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rcv_rest_r[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rcv_rest_r[1:0]
(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rcv_rest_r[1:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in0[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in1[0]
@800028
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in[1:0]
(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in[1:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_out[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rst[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.set_other_only_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.snd_last_byte[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.snd_pre_start[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.snd_rest_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_in0[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_in1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_out[0]
@800028
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_rcv[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_rcv[1:0]
(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_rcv[1:0]
@1001200
-group_end
@1401200
-test01_status_router2_01
@c00200
-axibram_read
@28
x393_testbench01.x393_i.axibram_read_i.aclk[0]
x393_testbench01.x393_i.axibram_read_i.ar_half_full[0]
x393_testbench01.x393_i.axibram_read_i.ar_nempty[0]
@22
x393_testbench01.x393_i.axibram_read_i.araddr[31:0]
x393_testbench01.x393_i.axibram_read_i.araddr_out[12:0]
@28
x393_testbench01.x393_i.axibram_read_i.arburst[1:0]
x393_testbench01.x393_i.axibram_read_i.arburst_out[1:0]
@22
x393_testbench01.x393_i.axibram_read_i.arid[11:0]
x393_testbench01.x393_i.axibram_read_i.arid_out[11:0]
x393_testbench01.x393_i.axibram_read_i.arlen[3:0]
x393_testbench01.x393_i.axibram_read_i.arlen_out[3:0]
@28
x393_testbench01.x393_i.axibram_read_i.arready[0]
x393_testbench01.x393_i.axibram_read_i.arsize[1:0]
x393_testbench01.x393_i.axibram_read_i.arsize_out[1:0]
x393_testbench01.x393_i.axibram_read_i.arvalid[0]
@22
x393_testbench01.x393_i.axibram_read_i.bram_raddr[12:0]
@28
x393_testbench01.x393_i.axibram_read_i.bram_rclk[0]
@22
x393_testbench01.x393_i.axibram_read_i.bram_rdata[31:0]
@28
x393_testbench01.x393_i.axibram_read_i.bram_reg_re_0[0]
x393_testbench01.x393_i.axibram_read_i.bram_reg_re_w[0]
x393_testbench01.x393_i.axibram_read_i.bram_regen[0]
x393_testbench01.x393_i.axibram_read_i.bram_ren[0]
x393_testbench01.x393_i.axibram_read_i.dev_ready[0]
x393_testbench01.x393_i.axibram_read_i.last_in_burst_0[0]
x393_testbench01.x393_i.axibram_read_i.last_in_burst_1[0]
x393_testbench01.x393_i.axibram_read_i.last_in_burst_d_w[0]
x393_testbench01.x393_i.axibram_read_i.last_in_burst_w[0]
@22
x393_testbench01.x393_i.axibram_read_i.next_rd_address_w[12:0]
x393_testbench01.x393_i.axibram_read_i.pre_araddr[12:0]
@28
x393_testbench01.x393_i.axibram_read_i.pre_last_in_burst_r[0]
x393_testbench01.x393_i.axibram_read_i.pre_left_zero_w[0]
@22
x393_testbench01.x393_i.axibram_read_i.pre_rid0[11:0]
x393_testbench01.x393_i.axibram_read_i.pre_rid[11:0]
@28
x393_testbench01.x393_i.axibram_read_i.pre_rvalid_w[0]
x393_testbench01.x393_i.axibram_read_i.rburst[1:0]
@22
x393_testbench01.x393_i.axibram_read_i.rdata[31:0]
x393_testbench01.x393_i.axibram_read_i.read_address[12:0]
@28
x393_testbench01.x393_i.axibram_read_i.read_in_progress[0]
x393_testbench01.x393_i.axibram_read_i.read_in_progress_d[0]
x393_testbench01.x393_i.axibram_read_i.read_in_progress_d_w[0]
x393_testbench01.x393_i.axibram_read_i.read_in_progress_or[0]
x393_testbench01.x393_i.axibram_read_i.read_in_progress_w[0]
@22
x393_testbench01.x393_i.axibram_read_i.read_left[3:0]
x393_testbench01.x393_i.axibram_read_i.rid[11:0]
@28
x393_testbench01.x393_i.axibram_read_i.rlast[0]
@22
x393_testbench01.x393_i.axibram_read_i.rlen[3:0]
@28
x393_testbench01.x393_i.axibram_read_i.rready[0]
x393_testbench01.x393_i.axibram_read_i.rresp[1:0]
x393_testbench01.x393_i.axibram_read_i.rst[0]
x393_testbench01.x393_i.axibram_read_i.rvalid[0]
x393_testbench01.x393_i.axibram_read_i.start_burst[0]
x393_testbench01.x393_i.axibram_read_i.start_read_burst_0[0]
x393_testbench01.x393_i.axibram_read_i.start_read_burst_1[0]
x393_testbench01.x393_i.axibram_read_i.start_read_burst_w[0]
@1401200
-axibram_read
@c00200
-refresh
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.sel_refresh_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_seq_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.sequencer_run_busy[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.cry[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.en[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.en_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.en_refresh[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.grant[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.need[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.over[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.pending_rq[4:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.period_cntr[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.pre_div[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.refresh_due[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.refresh_period[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.set[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.want[0]
@1401200
-refresh
@800200
-DDR3
@28
x393_testbench01.x393_i.SDRST[0]
x393_testbench01.x393_i.SDCKE[0]
x393_testbench01.x393_i.SDCLK[0]
@22
x393_testbench01.x393_i.SDA[14:0]
@28
x393_testbench01.x393_i.SDBA[2:0]
x393_testbench01.x393_i.SDRAS[0]
x393_testbench01.x393_i.SDCAS[0]
x393_testbench01.x393_i.SDWE[0]
x393_testbench01.x393_i.DQSL[0]
x393_testbench01.x393_i.DQSU[0]
x393_testbench01.x393_i.NDQSL[0]
x393_testbench01.x393_i.NDQSU[0]
x393_testbench01.x393_i.SDDML[0]
x393_testbench01.x393_i.SDDMU[0]
@22
x393_testbench01.x393_i.SDD[15:0]
@28
x393_testbench01.x393_i.SDODT[0]
@1000200
-DDR3
@c00200
-scheduler
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.chn_en[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.en_schedul[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_chn[3:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_chn_r[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_sent[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.index[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.index_valid[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_conf[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_set[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_some[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_want_conf[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_want_conf_d[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.next_need_conf[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.next_want_conf[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_addr[3:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_data[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_en[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pri_reg[255:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.rst[0]
@c00022
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(2)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(3)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(4)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(5)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(6)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(7)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(8)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(9)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(10)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(11)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(12)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(13)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(14)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(15)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(16)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(17)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(18)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(19)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(20)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(21)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(22)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(23)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(24)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(25)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(26)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(27)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(28)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(29)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(30)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(31)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(32)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(33)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(34)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(35)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(36)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(37)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(38)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
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(223)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(224)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(225)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(226)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(227)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(228)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(229)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(230)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(231)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(232)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(233)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(234)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(235)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(236)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(237)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(238)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(239)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(240)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(241)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(242)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(243)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(244)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(245)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(246)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(247)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(248)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(249)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(250)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(251)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(252)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(253)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(254)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(255)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
@1401200
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@22
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@c00022
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
@28
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(9)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(10)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(11)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
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(13)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(14)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
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@1401200
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@22
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@1401200
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@22
x393_testbench01.axi_set_dqs_odelay.delay[7:0]
@200
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@c00200
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@28
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@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
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@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_idly[7:0]
@28
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@22
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@28
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@22
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dq_r[3:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dqs[3:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dqs_r[3:0]
@1401200
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@c00200
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@28
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@800022
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@28
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@1001200
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.values[255:0]
@1401200
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@800200
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@c00200
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@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.ad[7:0]
@28
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@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.mode[1:0]
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x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.need_to_send[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.rq[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.rq_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.rst[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.seq[5:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.snd_rest[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.status[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.status_changed_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.status_r[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.wd[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.we[0]
@1401200
-PS_PIO_STATUS
@800200
-PS_PIO_CHN0
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.data_in[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_data_out[31:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_raddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_rd[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_regen[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.page_next[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.page_r[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.waddr[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wclk[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_set[0]
@1000200
-PS_PIO_CHN0
@200
-
@800200
-PS_PIO_CHN1
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.data_out[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_data_in[31:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_waddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page_next[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page_r[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.raddr[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rclk[0]
@29
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rd[0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_set[0]
@1000200
-PS_PIO_CHN1
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_rd_chn1[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_rdata_chn1[63:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_wdata_chn0[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_wpage_nxt_chn0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_wr_chn0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.busy[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.channel_pgm_en0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.channel_pgm_en1[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.channel_pgm_en[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn_en[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn_rst[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_a[4:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_chn[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_data[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_half_full[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_need[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_nempty[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_out[13:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_page[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_seq_a[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_set[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_set_d[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_set_d_neg[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_stb[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.en_reset[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.mclk[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.mem_run[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.need_rq0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.need_rq1[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_neg[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port0_addr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port0_clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port0_data[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port0_re[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port0_regen[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port1_addr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port1_clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port1_data[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port1_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.rpage_nxt_chn1[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.rst[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_data0[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_chn_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_seq_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.sel_refresh_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_run[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_chn[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_done0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_done1[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_set0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.set_cmd_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.set_en_rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.set_status_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.start[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_ad[7:0]
@800028
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_data[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_data[1:0]
(1)x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_data[1:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_rq[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq1[0]
@1000200
-PS_PIO
@800200
-memcntrl16_0
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rchn_late[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rd_late[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_rdata_chn1[63:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rdata1[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rpage_nxt[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rchn[3:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rdata[63:0]
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.buf_chn_sel[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.buf_rd_chn[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.buf_rdata_chn[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.ext_buf_rchn[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.ext_buf_rd[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.ext_buf_rdata[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.ext_buf_rrefresh[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.mclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_enabled[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_data0[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_set0[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_data[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_set[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_fill[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_full[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.en_schedul[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_chn_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_seq_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.sel_refresh_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_wr[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_run[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.grant_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_set[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_addr_start[10:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_done0[0]
@200
-
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_addr[10:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_busy[0]
@800200
-memcntr_sequencer
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_nop[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_addr_in[14:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_bank_in[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw_pos[2:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_odt_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cke_dis[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_sel_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_en_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_en_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_toggle_en[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_en_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_wr[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rd[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cmd_add_pause[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rst[0]
@1000200
-memcntr_sequencer
@200
-
@800200
-cmd0_buf
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.data_in[31:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.data_out[31:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.raddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.rclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.ren[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.waddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.wclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.we[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.web[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rrefresh[0]
@1000200
-cmd0_buf
-memcntrl16_0
@c00200
-max_0001
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.a[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.b[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.mask_a[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.mask_b[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.max[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.s[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.s_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.s_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.valid[0]
@1401200
-max_0001
@c00200
-max_00010203
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.a[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.b[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.mask_a[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.mask_b[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.max[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.s[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.s_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.s_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.valid[0]
@1401200
-max_00010203
@c00200
-max_0001020304050607
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.a[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.b[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.mask_a[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.mask_b[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.max[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.s[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.s_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.s_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.valid[0]
@1401200
-max_0001020304050607
@c00200
-max_00__15
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.a[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.b[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.mask_a[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.mask_b[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.max[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.s[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.s_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.s_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.valid[0]
@1401200
-max_00__15
[pattern_trace] 1
[pattern_trace] 0