Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 | Date : Thu Apr 4 13:44:26 2019 | Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS | Command : report_timing_summary -file vivado_build/x393.timing_summary_impl | Design : x393 | Device : 7z030-fbg484 | Speed File : -1 PRODUCTION 1.11 2014-09-11 ------------------------------------------------------------------------------------ Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : false Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 16 register/latch pins with no clock driven by root clock pin: DQSL (HIGH) There are 16 register/latch pins with no clock driven by root clock pin: DQSU (HIGH) There is 1 register/latch pin with no clock driven by root clock pin: ffclk1p (HIGH) There is 1 register/latch pin with no clock driven by root clock pin: memclk (HIGH) There are 436 register/latch pins with no clock driven by root clock pin: sns1_clkp (HIGH) There are 436 register/latch pins with no clock driven by root clock pin: sns2_clkp (HIGH) There are 436 register/latch pins with no clock driven by root clock pin: sns3_clkp (HIGH) There are 436 register/latch pins with no clock driven by root clock pin: sns4_clkp (HIGH) 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 4100 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 62 input ports with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 95 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.006 0.000 0 148663 0.022 0.000 0 148663 0.264 0.000 0 60733 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- axi_aclk {0.000 10.000} 20.000 50.000 axihp_clk {0.000 3.333} 6.667 150.000 clk_fb {0.000 10.000} 20.000 50.000 ddr3_clk {0.000 1.250} 2.500 400.000 ddr3_clk_div {0.000 2.500} 5.000 200.000 ddr3_clk_ref {0.000 2.500} 5.000 200.000 ddr3_mclk {1.250 3.750} 5.000 200.000 ddr3_sdclk {0.000 1.250} 2.500 400.000 multi_clkfb {0.000 10.000} 20.000 50.000 sclk {0.000 5.000} 10.000 100.000 xclk {0.000 2.083} 4.167 240.000 ffclk0 {0.000 20.833} 41.667 24.000 clkfb {0.000 20.833} 41.667 24.000 pclk {0.000 2.315} 4.630 215.998 gtrefclk {0.000 3.333} 6.666 150.015 rx_clk {0.000 3.333} 6.666 150.015 txoutclk {0.000 3.333} 6.666 150.015 usrclk2 {0.000 6.666} 13.333 75.002 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- axi_aclk 14.087 0.000 0 2685 0.055 0.000 0 2685 7.000 0.000 0 737 axihp_clk 0.379 0.000 0 10209 0.055 0.000 0 10209 0.267 0.000 0 3863 clk_fb 18.751 0.000 0 2 ddr3_clk 0.279 0.000 0 45 ddr3_clk_div 0.262 0.000 0 2158 0.137 0.000 0 2158 1.389 0.000 0 755 ddr3_clk_ref 0.264 0.000 0 5 ddr3_mclk 0.131 0.000 0 81699 0.022 0.000 0 81699 1.389 0.000 0 33130 ddr3_sdclk 1.092 0.000 0 3 multi_clkfb 18.751 0.000 0 2 sclk 4.184 0.000 0 2740 0.056 0.000 0 2740 4.090 0.000 0 1349 xclk 0.029 0.000 0 33043 0.043 0.000 0 33043 0.875 0.000 0 13479 ffclk0 40.600 0.000 0 1 0.397 0.000 0 1 10.833 0.000 0 2 clkfb 10.966 0.000 0 2 pclk 0.204 0.000 0 9523 0.042 0.000 0 9523 1.405 0.000 0 4843 gtrefclk 3.851 0.000 0 45 0.253 0.000 0 45 2.553 0.000 0 25 rx_clk 0.312 0.000 0 917 0.087 0.000 0 917 2.423 0.000 0 329 txoutclk 2.057 0.000 0 232 0.179 0.000 0 232 2.666 0.000 0 138 usrclk2 4.647 0.000 0 4576 0.059 0.000 0 4576 5.756 0.000 0 2024 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ddr3_clk_div ddr3_clk 0.084 0.000 0 23 0.155 0.000 0 23 ddr3_mclk ddr3_clk_div 0.006 0.000 0 146 1.357 0.000 0 146 ddr3_clk_div ddr3_mclk 2.860 0.000 0 76 0.273 0.000 0 76 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** axihp_clk axihp_clk 1.841 0.000 0 23 0.617 0.000 0 23 **async_default** ddr3_mclk ddr3_mclk 0.375 0.000 0 453 0.275 0.000 0 453 **async_default** pclk pclk 0.508 0.000 0 20 0.356 0.000 0 20 **async_default** sclk sclk 5.006 0.000 0 16 0.288 0.000 0 16 **async_default** usrclk2 usrclk2 5.183 0.000 0 7 0.984 0.000 0 7 **async_default** xclk xclk 0.650 0.000 0 72 0.388 0.000 0 72 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: axi_aclk To Clock: axi_aclk Setup : 0 Failing Endpoints, Worst Slack 14.087ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.055ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 14.087ns (required time - arrival time) Source: mcntrl393_i/select_buf3rd_reg/C (rising edge-triggered cell FDRE clocked by axi_aclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ps7_i/MAXIGP0RDATA[2] (rising edge-triggered cell PS7 clocked by axi_aclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: axi_aclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (axi_aclk rise@20.000ns - axi_aclk rise@0.000ns) Data Path Delay: 5.361ns (logic 0.510ns (9.513%) route 4.851ns (90.487%)) Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: 0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.336ns = ( 21.336 - 20.000 ) Source Clock Delay (SCD): 1.391ns Clock Pessimism Removal (CPR): 0.089ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_aclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.391 1.391 mcntrl393_i/axi_clk SLICE_X40Y148 FDRE r mcntrl393_i/select_buf3rd_reg/C ------------------------------------------------------------------- ------------------- SLICE_X40Y148 FDRE (Prop_fdre_C_Q) 0.246 1.637 r mcntrl393_i/select_buf3rd_reg/Q net (fo=34, routed) 1.849 3.486 cmd_readback_i/lopt_3 SLICE_X70Y139 LUT4 (Prop_lut4_I3_O) 0.158 3.644 r cmd_readback_i/xlnx_opt_LUT_ps7_i_i_59/O net (fo=1, routed) 1.032 4.676 cmd_readback_i/xlnx_opt_MAXIGP0RDATA[2]_1 SLICE_X56Y139 LUT5 (Prop_lut5_I4_O) 0.053 4.729 r cmd_readback_i/xlnx_opt_LUT_ps7_i_i_59_1/O net (fo=1, routed) 1.116 5.845 cmd_readback_i/xlnx_opt_MAXIGP0RDATA[2] SLICE_X41Y150 LUT6 (Prop_lut6_I5_O) 0.053 5.898 r cmd_readback_i/xlnx_opt_LUT_ps7_i_i_59_2/O net (fo=1, routed) 0.854 6.752 axird_rdata[2] PS7_X0Y0 PS7 r ps7_i/MAXIGP0RDATA[2] ------------------------------------------------------------------- ------------------- (clock axi_aclk rise edge) 20.000 20.000 r BUFGCTRL_X0Y23 BUFG 0.000 20.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.336 21.336 axi_aclk PS7_X0Y0 PS7 r ps7_i/MAXIGP0ACLK clock pessimism 0.089 21.425 clock uncertainty -0.035 21.390 PS7_X0Y0 PS7 (Setup_ps7_MAXIGP0ACLK_MAXIGP0RDATA[2]) -0.550 20.840 ps7_i ------------------------------------------------------------------- required time 20.840 arrival time -6.752 ------------------------------------------------------------------- slack 14.087 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.055ns (arrival time - required time) Source: axibram_write_i/wdata_i/inreg_reg[38]/C (rising edge-triggered cell FDRE clocked by axi_aclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axibram_write_i/wdata_i/ram_reg_0_15_36_41/RAMB/I (rising edge-triggered cell RAMD32 clocked by axi_aclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: axi_aclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (axi_aclk rise@0.000ns - axi_aclk rise@0.000ns) Data Path Delay: 0.201ns (logic 0.100ns (49.726%) route 0.101ns (50.274%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.857ns Source Clock Delay (SCD): 0.632ns Clock Pessimism Removal (CPR): 0.211ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_aclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.632 0.632 axibram_write_i/wdata_i/axi_clk SLICE_X28Y154 FDRE r axibram_write_i/wdata_i/inreg_reg[38]/C ------------------------------------------------------------------- ------------------- SLICE_X28Y154 FDRE (Prop_fdre_C_Q) 0.100 0.732 r axibram_write_i/wdata_i/inreg_reg[38]/Q net (fo=1, routed) 0.101 0.833 axibram_write_i/wdata_i/ram_reg_0_15_36_41/DIB0 SLICE_X30Y154 RAMD32 r axibram_write_i/wdata_i/ram_reg_0_15_36_41/RAMB/I ------------------------------------------------------------------- ------------------- (clock axi_aclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.857 0.857 axibram_write_i/wdata_i/ram_reg_0_15_36_41/WCLK SLICE_X30Y154 RAMD32 r axibram_write_i/wdata_i/ram_reg_0_15_36_41/RAMB/CLK clock pessimism -0.211 0.646 SLICE_X30Y154 RAMD32 (Hold_ramd32_CLK_I) 0.132 0.778 axibram_write_i/wdata_i/ram_reg_0_15_36_41/RAMB ------------------------------------------------------------------- required time -0.778 arrival time 0.833 ------------------------------------------------------------------- slack 0.055 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: axi_aclk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { clocks393_i/bufg_axi_aclk_i/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 20.000 17.817 RAMB36_X3Y30 cmd_readback_i/ram_reg_0/CLKBWRCLK Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X1Y2 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1 Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X1Y2 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1 High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X1Y2 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: axihp_clk To Clock: axihp_clk Setup : 0 Failing Endpoints, Worst Slack 0.379ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.055ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.267ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.379ns (required time - arrival time) Source: sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C (rising edge-triggered cell FDRE clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns}) Destination: sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register1_r_reg[11]/R (rising edge-triggered cell FDRE clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns}) Path Group: axihp_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 6.667ns (axihp_clk rise@6.667ns - axihp_clk rise@0.000ns) Data Path Delay: 5.928ns (logic 0.282ns (4.757%) route 5.646ns (95.243%)) Logic Levels: 0 Clock Path Skew: 0.158ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.739ns = ( 11.406 - 6.667 ) Source Clock Delay (SCD): 4.817ns Clock Pessimism Removal (CPR): 0.236ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axihp_clk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.602 1.602 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.088 1.690 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 1.621 3.311 clocks393_i/hclk_i/hclk_pre BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.120 3.431 r clocks393_i/hclk_i/clk1x_i/O net (fo=3868, routed) 1.386 4.817 sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk SLICE_X34Y113 FDRE r sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X34Y113 FDRE (Prop_fdre_C_Q) 0.282 5.099 r sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q net (fo=335, routed) 5.646 10.745 sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/regs_reg[1][0] SLICE_X106Y2 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register1_r_reg[11]/R ------------------------------------------------------------------- ------------------- (clock axihp_clk rise edge) 6.667 6.667 r BUFGCTRL_X0Y23 BUFG 0.000 6.667 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.461 8.128 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.083 8.211 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 1.538 9.749 clocks393_i/hclk_i/hclk_pre BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.113 9.862 r clocks393_i/hclk_i/clk1x_i/O net (fo=3868, routed) 1.544 11.406 sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/hclk SLICE_X106Y2 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register1_r_reg[11]/C clock pessimism 0.236 11.642 clock uncertainty -0.071 11.570 SLICE_X106Y2 FDRE (Setup_fdre_C_R) -0.446 11.124 sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register1_r_reg[11] ------------------------------------------------------------------- required time 11.124 arrival time -10.745 ------------------------------------------------------------------- slack 0.379 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.055ns (arrival time - required time) Source: sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/inreg_reg[7]/C (rising edge-triggered cell FDRE clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns}) Destination: sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/ram_reg_0_15_6_11/RAMA_D1/I (rising edge-triggered cell RAMD32 clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns}) Path Group: axihp_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (axihp_clk rise@0.000ns - axihp_clk rise@0.000ns) Data Path Delay: 0.279ns (logic 0.100ns (35.808%) route 0.179ns (64.192%)) Logic Levels: 0 Clock Path Skew: 0.116ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.286ns Source Clock Delay (SCD): 1.872ns Clock Pessimism Removal (CPR): 0.298ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axihp_clk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.586 0.586 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.050 0.636 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 0.577 1.213 clocks393_i/hclk_i/hclk_pre BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 1.239 r clocks393_i/hclk_i/clk1x_i/O net (fo=3868, routed) 0.633 1.872 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/hclk SLICE_X29Y152 FDRE r sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/inreg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y152 FDRE (Prop_fdre_C_Q) 0.100 1.972 r sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/inreg_reg[7]/Q net (fo=1, routed) 0.179 2.151 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/ram_reg_0_15_6_11/DIA1 SLICE_X30Y145 RAMD32 r sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/ram_reg_0_15_6_11/RAMA_D1/I ------------------------------------------------------------------- ------------------- (clock axihp_clk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.803 0.803 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.053 0.856 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 0.643 1.499 clocks393_i/hclk_i/hclk_pre BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.030 1.529 r clocks393_i/hclk_i/clk1x_i/O net (fo=3868, routed) 0.757 2.286 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/ram_reg_0_15_6_11/WCLK SLICE_X30Y145 RAMD32 r sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/ram_reg_0_15_6_11/RAMA_D1/CLK clock pessimism -0.298 1.988 SLICE_X30Y145 RAMD32 (Hold_ramd32_CLK_I) 0.108 2.096 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/ram_reg_0_15_6_11/RAMA_D1 ------------------------------------------------------------------- required time -2.096 arrival time 2.151 ------------------------------------------------------------------- slack 0.055 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: axihp_clk Waveform(ns): { 0.000 3.333 } Period(ns): 6.667 Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 6.400 6.667 0.267 GTXE2_CHANNEL_X0Y0 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/DRPCLK Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 6.667 153.333 PLLE2_ADV_X1Y2 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 Low Pulse Width Slow RAMD32/CLK n/a 0.910 3.333 2.423 SLICE_X26Y119 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_ram_reg_0_7_60_63/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 0.910 3.333 2.423 SLICE_X26Y122 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_ram_reg_0_7_12_17/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: clk_fb To Clock: clk_fb Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 18.751ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_fb Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 20.000 80.000 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: ddr3_clk To Clock: ddr3_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.279ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ddr3_clk Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFR/I n/a 2.221 2.500 0.279 BUFR_X1Y8 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/I Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 2.500 210.860 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 --------------------------------------------------------------------------------------------------- From Clock: ddr3_clk_div To Clock: ddr3_clk_div Setup : 0 Failing Endpoints, Worst Slack 0.262ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.137ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 1.389ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.262ns (required time - arrival time) Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[0]/C (rising edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_addr_reg[6]/D (rising edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: ddr3_clk_div Path Type: Setup (Max at Slow Process Corner) Requirement: 5.000ns (ddr3_clk_div rise@5.000ns - ddr3_clk_div rise@0.000ns) Data Path Delay: 4.587ns (logic 0.322ns (7.020%) route 4.265ns (92.980%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.526ns = ( 8.526 - 5.000 ) Source Clock Delay (SCD): 3.919ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.156ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ddr3_clk_div rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.575 1.575 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) 0.088 1.663 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 net (fo=1, routed) 1.106 2.769 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.377 3.146 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O net (fo=753, routed) 0.773 3.919 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div SLICE_X71Y123 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y123 FDRE (Prop_fdre_C_Q) 0.269 4.188 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[0]/Q net (fo=62, routed) 4.265 8.453 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/dly_addr_r_reg[6][0] SLICE_X118Y145 LUT6 (Prop_lut6_I3_O) 0.053 8.506 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_addr[6]_i_1/O net (fo=1, routed) 0.000 8.506 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_addr[6]_i_1_n_0 SLICE_X118Y145 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_addr_reg[6]/D ------------------------------------------------------------------- ------------------- (clock ddr3_clk_div rise edge) 5.000 5.000 r BUFGCTRL_X0Y23 BUFG 0.000 5.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.437 6.437 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) 0.083 6.520 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 net (fo=1, routed) 1.016 7.536 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.370 7.906 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O net (fo=753, routed) 0.620 8.526 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg SLICE_X118Y145 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_addr_reg[6]/C clock pessimism 0.256 8.782 clock uncertainty -0.085 8.697 SLICE_X118Y145 FDRE (Setup_fdre_C_D) 0.071 8.768 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_addr_reg[6] ------------------------------------------------------------------- required time 8.768 arrival time -8.506 ------------------------------------------------------------------- slack 0.262 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.137ns (arrival time - required time) Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_pre_reg[1]/C (rising edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_reg[1]/D (rising edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: ddr3_clk_div Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ddr3_clk_div rise@0.000ns - ddr3_clk_div rise@0.000ns) Data Path Delay: 0.209ns (logic 0.100ns (47.820%) route 0.109ns (52.180%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.740ns Source Clock Delay (SCD): 1.424ns Clock Pessimism Removal (CPR): 0.303ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ddr3_clk_div rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.580 0.580 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) 0.050 0.630 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 net (fo=1, routed) 0.433 1.063 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.090 1.153 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O net (fo=753, routed) 0.271 1.424 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/psincdec_reg SLICE_X117Y135 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_pre_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y135 FDRE (Prop_fdre_C_Q) 0.100 1.524 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_pre_reg[1]/Q net (fo=2, routed) 0.109 1.633 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_pre_reg_n_0_[1] SLICE_X118Y135 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_reg[1]/D ------------------------------------------------------------------- ------------------- (clock ddr3_clk_div rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.796 0.796 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) 0.053 0.849 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 net (fo=1, routed) 0.490 1.339 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.093 1.432 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O net (fo=753, routed) 0.308 1.740 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/psincdec_reg SLICE_X118Y135 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_reg[1]/C clock pessimism -0.303 1.437 SLICE_X118Y135 FDRE (Hold_fdre_C_D) 0.059 1.496 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_reg[1] ------------------------------------------------------------------- required time -1.496 arrival time 1.633 ------------------------------------------------------------------- slack 0.137 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ddr3_clk_div Waveform(ns): { 0.000 2.500 } Period(ns): 5.000 Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFR/I n/a 2.221 5.000 2.779 BUFR_X1Y9 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/I Max Period n/a MMCME2_ADV/CLKOUT2 n/a 213.360 5.000 208.360 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 Low Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.111 2.500 1.389 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK High Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.111 2.500 1.389 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK --------------------------------------------------------------------------------------------------- From Clock: ddr3_clk_ref To Clock: ddr3_clk_ref Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ddr3_clk_ref Waveform(ns): { 0.000 2.500 } Period(ns): 5.000 Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT5 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a IDELAYCTRL/REFCLK n/a 3.225 5.000 1.775 IDELAYCTRL_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK --------------------------------------------------------------------------------------------------- From Clock: ddr3_mclk To Clock: ddr3_mclk Setup : 0 Failing Endpoints, Worst Slack 0.131ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.022ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 1.389ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.131ns (required time - arrival time) Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK (rising edge-triggered cell RAMB36E1 clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns}) Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/ENARDEN (rising edge-triggered cell RAMB36E1 clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns}) Path Group: ddr3_mclk Path Type: Setup (Max at Slow Process Corner) Requirement: 5.000ns (ddr3_mclk rise@6.250ns - ddr3_mclk rise@1.250ns) Data Path Delay: 4.384ns (logic 1.013ns (23.106%) route 3.371ns (76.894%)) Logic Levels: 5 (LUT2=1 LUT4=1 LUT5=1 LUT6=2) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.522ns = ( 10.772 - 6.250 ) Source Clock Delay (SCD): 4.878ns = ( 6.128 - 1.250 ) Clock Pessimism Removal (CPR): 0.331ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.156ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ddr3_mclk rise edge) 1.250 1.250 r BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.575 2.825 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) 0.088 2.913 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 net (fo=1, routed) 1.628 4.541 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.120 4.661 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O net (fo=33128, routed) 1.467 6.128 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/CLK RAMB36_X5Y24 RAMB36E1 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK ------------------------------------------------------------------- ------------------- RAMB36_X5Y24 RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[27]) 0.748 6.876 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/DOADO[27] net (fo=1, routed) 0.635 7.511 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_0[26] SLICE_X92Y129 LUT4 (Prop_lut4_I3_O) 0.053 7.564 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/phy_addr_prev[10]_i_1/O net (fo=13, routed) 0.495 8.059 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/phy_addr_prev_reg[14][22] SLICE_X90Y126 LUT2 (Prop_lut2_I1_O) 0.053 8.112 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/pause_cntr[7]_i_2/O net (fo=2, routed) 0.719 8.831 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/pause_len[7] SLICE_X88Y125 LUT6 (Prop_lut6_I3_O) 0.053 8.884 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_4/O net (fo=2, routed) 0.472 9.356 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_4_n_0 SLICE_X88Y126 LUT6 (Prop_lut6_I1_O) 0.053 9.409 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_2/O net (fo=3, routed) 0.371 9.780 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_2_n_0 SLICE_X87Y127 LUT5 (Prop_lut5_I1_O) 0.053 9.833 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_1__0/O net (fo=2, routed) 0.678 10.512 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/ren1 RAMB36_X5Y24 RAMB36E1 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/ENARDEN ------------------------------------------------------------------- ------------------- (clock ddr3_mclk rise edge) 6.250 6.250 r BUFGCTRL_X0Y23 BUFG 0.000 6.250 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.437 7.687 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) 0.083 7.770 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 net (fo=1, routed) 1.544 9.314 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.113 9.427 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O net (fo=33128, routed) 1.345 10.772 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/CLK RAMB36_X5Y24 RAMB36E1 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK clock pessimism 0.331 11.103 clock uncertainty -0.085 11.017 RAMB36_X5Y24 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_ENARDEN) -0.375 10.642 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i ------------------------------------------------------------------- required time 10.642 arrival time -10.512 ------------------------------------------------------------------- slack 0.131 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.022ns (arrival time - required time) Source: status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/ra_reg_rep[1]/C (rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns}) Destination: status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/outreg_reg[6]/D (rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns}) Path Group: ddr3_mclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ddr3_mclk rise@1.250ns - ddr3_mclk rise@1.250ns) Data Path Delay: 0.416ns (logic 0.154ns (37.031%) route 0.262ns (62.969%)) Logic Levels: 1 (RAMD32=1) Clock Path Skew: 0.298ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.337ns = ( 3.587 - 1.250 ) Source Clock Delay (SCD): 1.744ns = ( 2.994 - 1.250 ) Clock Pessimism Removal (CPR): 0.295ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ddr3_mclk rise edge) 1.250 1.250 r BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.580 1.830 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) 0.050 1.880 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 net (fo=1, routed) 0.559 2.439 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 2.465 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O net (fo=33128, routed) 0.529 2.994 status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/mclk SLICE_X53Y149 FDRE r status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/ra_reg_rep[1]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y149 FDRE (Prop_fdre_C_Q) 0.091 3.085 r status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/ra_reg_rep[1]/Q net (fo=12, routed) 0.262 3.347 status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/ram_reg_0_15_6_8/ADDRA1 SLICE_X52Y150 RAMD32 (Prop_ramd32_RADR1_O) 0.063 3.410 r status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/ram_reg_0_15_6_8/RAMA/O net (fo=1, routed) 0.000 3.410 status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/outreg0__8[6] SLICE_X52Y150 FDRE r status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/outreg_reg[6]/D ------------------------------------------------------------------- ------------------- (clock ddr3_mclk rise edge) 1.250 1.250 r BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.796 2.046 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) 0.053 2.099 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 net (fo=1, routed) 0.623 2.722 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.030 2.752 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O net (fo=33128, routed) 0.835 3.587 status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/mclk SLICE_X52Y150 FDRE r status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/outreg_reg[6]/C clock pessimism -0.295 3.292 SLICE_X52Y150 FDRE (Hold_fdre_C_D) 0.096 3.388 status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/outreg_reg[6] ------------------------------------------------------------------- required time -3.388 arrival time 3.410 ------------------------------------------------------------------- slack 0.022 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ddr3_mclk Waveform(ns): { 1.250 3.750 } Period(ns): 5.000 Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.495 5.000 2.505 RAMB36_X1Y12 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/sens_hist_ram_snglclk_32_i/ramt_var_w_var_r_even_i/RAMB36E1_i/CLKBWRCLK Max Period n/a MMCME2_ADV/CLKOUT3 n/a 213.360 5.000 208.360 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 Low Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.111 2.500 1.389 MMCME2_ADV_X0Y0 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/PSCLK High Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.111 2.500 1.389 MMCME2_ADV_X0Y1 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/PSCLK --------------------------------------------------------------------------------------------------- From Clock: ddr3_sdclk To Clock: ddr3_sdclk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 1.092ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ddr3_sdclk Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFIO/I n/a 1.408 2.500 1.092 BUFIO_X1Y9 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/iclk_bufio_i/I Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 2.500 210.860 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0 --------------------------------------------------------------------------------------------------- From Clock: multi_clkfb To Clock: multi_clkfb Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 18.751ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: multi_clkfb Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X1Y2 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X1Y2 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: sclk To Clock: sclk Setup : 0 Failing Endpoints, Worst Slack 4.184ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.056ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 4.090ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.184ns (required time - arrival time) Source: event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C (rising edge-triggered cell FDRE clocked by sclk {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D (falling edge-triggered cell FDRE clocked by sclk {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sclk Path Type: Setup (Max at Slow Process Corner) Requirement: 5.000ns (sclk fall@5.000ns - sclk rise@0.000ns) Data Path Delay: 0.682ns (logic 0.269ns (39.450%) route 0.413ns (60.550%)) Logic Levels: 0 Clock Path Skew: -0.027ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.585ns = ( 9.585 - 5.000 ) Source Clock Delay (SCD): 4.987ns Clock Pessimism Removal (CPR): 0.375ns Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.133ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.602 1.602 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 1.690 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 net (fo=1, routed) 1.621 3.311 clocks393_i/sync_clk_i/sync_clk_pre BUFGCTRL_X0Y22 BUFG (Prop_bufg_I_O) 0.120 3.431 r clocks393_i/sync_clk_i/clk1x_i/O net (fo=1347, routed) 1.556 4.987 event_logger_i/i_imu_spi/camsync_clk SLICE_X68Y176 FDRE r event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X68Y176 FDRE (Prop_fdre_C_Q) 0.269 5.256 r event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/Q net (fo=2, routed) 0.413 5.669 event_logger_i/i_imu_spi/sngl_wire_stb_reg_n_0_[0] SLICE_X71Y175 FDRE r event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sclk fall edge) 5.000 5.000 f BUFGCTRL_X0Y23 BUFG 0.000 5.000 f clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.461 6.461 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.083 6.544 f clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 net (fo=1, routed) 1.538 8.082 clocks393_i/sync_clk_i/sync_clk_pre BUFGCTRL_X0Y22 BUFG (Prop_bufg_I_O) 0.113 8.195 f clocks393_i/sync_clk_i/clk1x_i/O net (fo=1347, routed) 1.390 9.585 event_logger_i/i_imu_spi/camsync_clk SLICE_X71Y175 FDRE r event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/C (IS_INVERTED) clock pessimism 0.375 9.960 clock uncertainty -0.075 9.885 SLICE_X71Y175 FDRE (Setup_fdre_C_D) -0.032 9.853 event_logger_i/i_imu_spi/sngl_wire_r_reg[1] ------------------------------------------------------------------- required time 9.853 arrival time -5.669 ------------------------------------------------------------------- slack 4.184 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.056ns (arrival time - required time) Source: event_logger_i/i_imu_timestamps/ts_data_r_reg[0]/C (rising edge-triggered cell FDRE clocked by sclk {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/RAMA/I (rising edge-triggered cell RAMD32 clocked by sclk {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sclk rise@0.000ns - sclk rise@0.000ns) Data Path Delay: 0.200ns (logic 0.100ns (50.053%) route 0.100ns (49.947%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.355ns Source Clock Delay (SCD): 1.840ns Clock Pessimism Removal (CPR): 0.502ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.586 0.586 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.636 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 net (fo=1, routed) 0.577 1.213 clocks393_i/sync_clk_i/sync_clk_pre BUFGCTRL_X0Y22 BUFG (Prop_bufg_I_O) 0.026 1.239 r clocks393_i/sync_clk_i/clk1x_i/O net (fo=1347, routed) 0.601 1.840 event_logger_i/i_imu_timestamps/camsync_clk SLICE_X71Y170 FDRE r event_logger_i/i_imu_timestamps/ts_data_r_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y170 FDRE (Prop_fdre_C_Q) 0.100 1.940 r event_logger_i/i_imu_timestamps/ts_data_r_reg[0]/Q net (fo=1, routed) 0.100 2.040 event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/DIA0 SLICE_X70Y169 RAMD32 r event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/RAMA/I ------------------------------------------------------------------- ------------------- (clock sclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.803 0.803 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.053 0.856 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 net (fo=1, routed) 0.643 1.499 clocks393_i/sync_clk_i/sync_clk_pre BUFGCTRL_X0Y22 BUFG (Prop_bufg_I_O) 0.030 1.529 r clocks393_i/sync_clk_i/clk1x_i/O net (fo=1347, routed) 0.826 2.355 event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/WCLK SLICE_X70Y169 RAMD32 r event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/RAMA/CLK clock pessimism -0.502 1.853 SLICE_X70Y169 RAMD32 (Hold_ramd32_CLK_I) 0.131 1.984 event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/RAMA ------------------------------------------------------------------- required time -1.984 arrival time 2.040 ------------------------------------------------------------------- slack 0.056 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sclk Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 1.600 10.000 8.400 BUFGCTRL_X0Y22 clocks393_i/sync_clk_i/clk1x_i/I Max Period n/a PLLE2_ADV/CLKOUT3 n/a 160.000 10.000 150.000 PLLE2_ADV_X1Y2 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 Low Pulse Width Fast RAMD32/CLK n/a 0.910 5.000 4.090 SLICE_X54Y171 event_logger_i/i_buf_xclk_mclk16/fifo_4x16_ram_reg_0_3_12_15/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 0.910 5.000 4.090 SLICE_X54Y169 event_logger_i/i_buf_xclk_mclk16/fifo_4x16_ram_reg_0_3_0_5/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: xclk To Clock: xclk Setup : 0 Failing Endpoints, Worst Slack 0.029ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.043ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.875ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.029ns (required time - arrival time) Source: compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/outreg_reg[8]/C (rising edge-triggered cell FDRE clocked by xclk {rise@0.000ns fall@2.083ns period=4.167ns}) Destination: compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out_reg[8]/R (rising edge-triggered cell FDRE clocked by xclk {rise@0.000ns fall@2.083ns period=4.167ns}) Path Group: xclk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.167ns (xclk rise@4.167ns - xclk rise@0.000ns) Data Path Delay: 3.677ns (logic 0.651ns (17.704%) route 3.026ns (82.296%)) Logic Levels: 5 (LUT4=1 LUT6=4) Clock Path Skew: -0.026ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.734ns = ( 8.901 - 4.167 ) Source Clock Delay (SCD): 5.080ns Clock Pessimism Removal (CPR): 0.320ns Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.114ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock xclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.602 1.602 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.088 1.690 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 net (fo=1, routed) 1.621 3.311 clocks393_i/xclk_i/xclk_pre BUFGCTRL_X0Y21 BUFG (Prop_bufg_I_O) 0.120 3.431 r clocks393_i/xclk_i/clk1x_i/O net (fo=13477, routed) 1.649 5.080 compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/xclk SLICE_X96Y37 FDRE r compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/outreg_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y37 FDRE (Prop_fdre_C_Q) 0.282 5.362 r compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/outreg_reg[8]/Q net (fo=4, routed) 0.617 5.979 compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[0].fifo_same_clock_i/outreg_reg[8]_2[8] SLICE_X97Y38 LUT6 (Prop_lut6_I1_O) 0.157 6.136 r compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[0].fifo_same_clock_i/d_out[14]_i_2/O net (fo=19, routed) 0.731 6.868 compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/outreg_reg[8]_0 SLICE_X95Y37 LUT6 (Prop_lut6_I2_O) 0.053 6.921 r compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/outreg[8]_i_4__4/O net (fo=2, routed) 0.362 7.283 compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/cry_ff_reg_3 SLICE_X94Y40 LUT6 (Prop_lut6_I1_O) 0.053 7.336 r compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/outreg[8]_i_2__12/O net (fo=9, routed) 0.445 7.781 compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/bytes_out0 SLICE_X94Y40 LUT6 (Prop_lut6_I0_O) 0.053 7.834 r compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/d_out[23]_i_1__0/O net (fo=35, routed) 0.430 8.264 compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/dv0 SLICE_X94Y41 LUT4 (Prop_lut4_I0_O) 0.053 8.317 r compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/d_out[15]_i_1/O net (fo=4, routed) 0.440 8.757 compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i_n_1 SLICE_X93Y42 FDRE r compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out_reg[8]/R ------------------------------------------------------------------- ------------------- (clock xclk rise edge) 4.167 4.167 r BUFGCTRL_X0Y23 BUFG 0.000 4.167 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.461 5.628 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.083 5.711 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 net (fo=1, routed) 1.538 7.249 clocks393_i/xclk_i/xclk_pre BUFGCTRL_X0Y21 BUFG (Prop_bufg_I_O) 0.113 7.362 r clocks393_i/xclk_i/clk1x_i/O net (fo=13477, routed) 1.539 8.901 compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/xclk SLICE_X93Y42 FDRE r compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out_reg[8]/C clock pessimism 0.320 9.221 clock uncertainty -0.067 9.153 SLICE_X93Y42 FDRE (Setup_fdre_C_R) -0.367 8.786 compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out_reg[8] ------------------------------------------------------------------- required time 8.786 arrival time -8.757 ------------------------------------------------------------------- slack 0.029 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.043ns (arrival time - required time) Source: compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_buf_average_i/avrPage_wa_reg/C (rising edge-triggered cell FDRE clocked by xclk {rise@0.000ns fall@2.083ns period=4.167ns}) Destination: compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_buf_average_i/avermem_reg_0_15_0_5/RAMA/WADR3 (rising edge-triggered cell RAMD32 clocked by xclk {rise@0.000ns fall@2.083ns period=4.167ns}) Path Group: xclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (xclk rise@0.000ns - xclk rise@0.000ns) Data Path Delay: 0.281ns (logic 0.100ns (35.545%) route 0.181ns (64.455%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.352ns Source Clock Delay (SCD): 1.842ns Clock Pessimism Removal (CPR): 0.497ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock xclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.586 0.586 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.050 0.636 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 net (fo=1, routed) 0.577 1.213 clocks393_i/xclk_i/xclk_pre BUFGCTRL_X0Y21 BUFG (Prop_bufg_I_O) 0.026 1.239 r clocks393_i/xclk_i/clk1x_i/O net (fo=13477, routed) 0.603 1.842 compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_buf_average_i/xclk SLICE_X91Y16 FDRE r compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_buf_average_i/avrPage_wa_reg/C ------------------------------------------------------------------- ------------------- SLICE_X91Y16 FDRE (Prop_fdre_C_Q) 0.100 1.942 r compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_buf_average_i/avrPage_wa_reg/Q net (fo=16, routed) 0.181 2.123 compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_buf_average_i/avermem_reg_0_15_0_5/ADDRD3 SLICE_X90Y15 RAMD32 r compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_buf_average_i/avermem_reg_0_15_0_5/RAMA/WADR3 ------------------------------------------------------------------- ------------------- (clock xclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.803 0.803 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.053 0.856 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 net (fo=1, routed) 0.643 1.499 clocks393_i/xclk_i/xclk_pre BUFGCTRL_X0Y21 BUFG (Prop_bufg_I_O) 0.030 1.529 r clocks393_i/xclk_i/clk1x_i/O net (fo=13477, routed) 0.823 2.352 compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_buf_average_i/avermem_reg_0_15_0_5/WCLK SLICE_X90Y15 RAMD32 r compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_buf_average_i/avermem_reg_0_15_0_5/RAMA/CLK clock pessimism -0.497 1.855 SLICE_X90Y15 RAMD32 (Hold_ramd32_CLK_WADR3) 0.225 2.080 compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_buf_average_i/avermem_reg_0_15_0_5/RAMA ------------------------------------------------------------------- required time -2.080 arrival time 2.123 ------------------------------------------------------------------- slack 0.043 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: xclk Waveform(ns): { 0.000 2.083 } Period(ns): 4.167 Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a DSP48E1/CLK n/a 3.292 4.167 0.875 DSP48_X3Y5 compressor393_i/cmprs_channel_block[0].jp_channel_i/focus_sharp393_i/mult_p_r_reg/CLK Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 4.167 155.833 PLLE2_ADV_X1Y2 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 Low Pulse Width Slow RAMD32/CLK n/a 0.910 2.083 1.173 SLICE_X50Y44 compressor393_i/cmprs_channel_block[3].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_metadata_i/time_ram0_reg_0_3_0_5/RAMA/CLK High Pulse Width Fast RAMS32/CLK n/a 0.910 2.083 1.173 SLICE_X58Y18 compressor393_i/cmprs_channel_block[0].jp_channel_i/encoderDCAC393_i/dc_mem_reg_0_7_0_0/SP/CLK --------------------------------------------------------------------------------------------------- From Clock: ffclk0 To Clock: ffclk0 Setup : 0 Failing Endpoints, Worst Slack 40.600ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.397ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 10.833ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 40.600ns (required time - arrival time) Source: clocks393_i/test_clk_reg[1]/C (rising edge-triggered cell FDCE clocked by ffclk0 {rise@0.000ns fall@20.833ns period=41.667ns}) Destination: clocks393_i/test_clk_reg[1]/D (rising edge-triggered cell FDCE clocked by ffclk0 {rise@0.000ns fall@20.833ns period=41.667ns}) Path Group: ffclk0 Path Type: Setup (Max at Slow Process Corner) Requirement: 41.667ns (ffclk0 rise@41.667ns - ffclk0 rise@0.000ns) Data Path Delay: 1.103ns (logic 0.361ns (32.739%) route 0.742ns (67.261%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.336ns = ( 45.003 - 41.667 ) Source Clock Delay (SCD): 3.927ns Clock Pessimism Removal (CPR): 0.591ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ffclk0 rise edge) 0.000 0.000 r Y12 0.000 0.000 r ffclk0p (IN) net (fo=0) 0.000 0.000 clocks393_i/ibufds_ibufgds0_i/ffclk0p Y12 IBUFDS (Prop_ibufds_I_O) 0.906 0.906 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O net (fo=2, routed) 3.021 3.927 clocks393_i/ffclk0 SLICE_X46Y107 FDCE r clocks393_i/test_clk_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y107 FDCE (Prop_fdce_C_Q) 0.308 4.235 f clocks393_i/test_clk_reg[1]/Q net (fo=4, routed) 0.742 4.976 clocks393_i/test_clk_reg SLICE_X46Y107 LUT1 (Prop_lut1_I0_O) 0.053 5.029 r clocks393_i/test_clk[1]_i_1/O net (fo=1, routed) 0.000 5.029 clocks393_i/test_clk[1]_i_1_n_0 SLICE_X46Y107 FDCE r clocks393_i/test_clk_reg[1]/D ------------------------------------------------------------------- ------------------- (clock ffclk0 rise edge) 41.667 41.667 r Y12 0.000 41.667 r ffclk0p (IN) net (fo=0) 0.000 41.667 clocks393_i/ibufds_ibufgds0_i/ffclk0p Y12 IBUFDS (Prop_ibufds_I_O) 0.827 42.494 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O net (fo=2, routed) 2.509 45.003 clocks393_i/ffclk0 SLICE_X46Y107 FDCE r clocks393_i/test_clk_reg[1]/C clock pessimism 0.591 45.594 clock uncertainty -0.035 45.558 SLICE_X46Y107 FDCE (Setup_fdce_C_D) 0.071 45.629 clocks393_i/test_clk_reg[1] ------------------------------------------------------------------- required time 45.629 arrival time -5.029 ------------------------------------------------------------------- slack 40.600 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.397ns (arrival time - required time) Source: clocks393_i/test_clk_reg[1]/C (rising edge-triggered cell FDCE clocked by ffclk0 {rise@0.000ns fall@20.833ns period=41.667ns}) Destination: clocks393_i/test_clk_reg[1]/D (rising edge-triggered cell FDCE clocked by ffclk0 {rise@0.000ns fall@20.833ns period=41.667ns}) Path Group: ffclk0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ffclk0 rise@0.000ns - ffclk0 rise@0.000ns) Data Path Delay: 0.484ns (logic 0.146ns (30.186%) route 0.338ns (69.814%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.196ns Source Clock Delay (SCD): 1.844ns Clock Pessimism Removal (CPR): 0.352ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ffclk0 rise edge) 0.000 0.000 r Y12 0.000 0.000 r ffclk0p (IN) net (fo=0) 0.000 0.000 clocks393_i/ibufds_ibufgds0_i/ffclk0p Y12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O net (fo=2, routed) 1.398 1.844 clocks393_i/ffclk0 SLICE_X46Y107 FDCE r clocks393_i/test_clk_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y107 FDCE (Prop_fdce_C_Q) 0.118 1.962 f clocks393_i/test_clk_reg[1]/Q net (fo=4, routed) 0.338 2.299 clocks393_i/test_clk_reg SLICE_X46Y107 LUT1 (Prop_lut1_I0_O) 0.028 2.327 r clocks393_i/test_clk[1]_i_1/O net (fo=1, routed) 0.000 2.327 clocks393_i/test_clk[1]_i_1_n_0 SLICE_X46Y107 FDCE r clocks393_i/test_clk_reg[1]/D ------------------------------------------------------------------- ------------------- (clock ffclk0 rise edge) 0.000 0.000 r Y12 0.000 0.000 r ffclk0p (IN) net (fo=0) 0.000 0.000 clocks393_i/ibufds_ibufgds0_i/ffclk0p Y12 IBUFDS (Prop_ibufds_I_O) 0.521 0.521 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O net (fo=2, routed) 1.675 2.196 clocks393_i/ffclk0 SLICE_X46Y107 FDCE r clocks393_i/test_clk_reg[1]/C clock pessimism -0.352 1.844 SLICE_X46Y107 FDCE (Hold_fdce_C_D) 0.087 1.931 clocks393_i/test_clk_reg[1] ------------------------------------------------------------------- required time -1.931 arrival time 2.327 ------------------------------------------------------------------- slack 0.397 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ffclk0 Waveform(ns): { 0.000 20.833 } Period(ns): 41.667 Sources: { ffclk0p } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 41.667 40.418 PLLE2_ADV_X0Y0 clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1 Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 41.667 10.966 PLLE2_ADV_X0Y0 clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1 Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 10.000 20.833 10.833 PLLE2_ADV_X0Y0 clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1 High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 10.000 20.833 10.833 PLLE2_ADV_X0Y0 clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clkfb To Clock: clkfb Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 10.966ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfb Waveform(ns): { 0.000 20.833 } Period(ns): 41.667 Sources: { clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 41.667 40.418 PLLE2_ADV_X0Y0 clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 41.667 10.966 PLLE2_ADV_X0Y0 clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: pclk To Clock: pclk Setup : 0 Failing Endpoints, Worst Slack 0.204ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.042ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 1.405ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.204ns (required time - arrival time) Source: sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul1_p_reg/CLK (rising edge-triggered cell DSP48E1 clocked by pclk {rise@0.000ns fall@2.315ns period=4.630ns}) Destination: sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/psdsp_11/D (rising edge-triggered cell FDRE clocked by pclk {rise@0.000ns fall@2.315ns period=4.630ns}) Path Group: pclk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.630ns (pclk rise@4.630ns - pclk rise@0.000ns) Data Path Delay: 4.186ns (logic 2.036ns (48.634%) route 2.150ns (51.366%)) Logic Levels: 3 (LUT4=2 LUT5=1) Clock Path Skew: -0.092ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.447ns = ( 10.076 - 4.630 ) Source Clock Delay (SCD): 5.893ns Clock Pessimism Removal (CPR): 0.354ns Clock Uncertainty: 0.115ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.219ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock pclk rise edge) 0.000 0.000 r Y12 0.000 0.000 r ffclk0p (IN) net (fo=0) 0.000 0.000 clocks393_i/ibufds_ibufgds0_i/ffclk0p Y12 IBUFDS (Prop_ibufds_I_O) 0.906 0.906 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O net (fo=2, routed) 1.253 2.159 clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.088 2.247 r clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 2.009 4.256 clocks393_i/dual_clock_pclk_i/clk1x_pre BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.120 4.376 r clocks393_i/dual_clock_pclk_i/clk1x_i/O net (fo=4841, routed) 1.517 5.893 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/clk1x DSP48_X0Y26 DSP48E1 r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul1_p_reg/CLK ------------------------------------------------------------------- ------------------- DSP48_X0Y26 DSP48E1 (Prop_dsp48e1_CLK_P[30]) 1.877 7.770 r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul1_p_reg/P[30] net (fo=11, routed) 0.823 8.593 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul1_p_reg_n_75 SLICE_X11Y65 LUT4 (Prop_lut4_I0_O) 0.053 8.646 r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_91__1/O net (fo=1, routed) 0.452 9.097 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_91__1_n_0 SLICE_X13Y65 LUT5 (Prop_lut5_I1_O) 0.053 9.150 r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_43__1/O net (fo=13, routed) 0.514 9.664 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_43__1_n_0 SLICE_X13Y66 LUT4 (Prop_lut4_I1_O) 0.053 9.717 r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_12__1/O net (fo=1, routed) 0.362 10.079 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mult_first_scaled[6] SLICE_X13Y67 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/psdsp_11/D ------------------------------------------------------------------- ------------------- (clock pclk rise edge) 4.630 4.630 r Y12 0.000 4.630 r ffclk0p (IN) net (fo=0) 0.000 4.630 clocks393_i/ibufds_ibufgds0_i/ffclk0p Y12 IBUFDS (Prop_ibufds_I_O) 0.827 5.456 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O net (fo=2, routed) 1.170 6.626 clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.083 6.709 r clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 1.911 8.620 clocks393_i/dual_clock_pclk_i/clk1x_pre BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.113 8.733 r clocks393_i/dual_clock_pclk_i/clk1x_i/O net (fo=4841, routed) 1.343 10.076 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/clk1x SLICE_X13Y67 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/psdsp_11/C clock pessimism 0.354 10.430 clock uncertainty -0.115 10.316 SLICE_X13Y67 FDRE (Setup_fdre_C_D) -0.032 10.284 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/psdsp_11 ------------------------------------------------------------------- required time 10.284 arrival time -10.079 ------------------------------------------------------------------- slack 0.204 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.042ns (arrival time - required time) Source: sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[10].dly01_16_i/sr_reg[0]/C (rising edge-triggered cell FDRE clocked by pclk {rise@0.000ns fall@2.315ns period=4.630ns}) Destination: sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[10].dly01_16_i/sr_reg[9]_srl9/D (rising edge-triggered cell SRL16E clocked by pclk {rise@0.000ns fall@2.315ns period=4.630ns}) Path Group: pclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (pclk rise@0.000ns - pclk rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.432%) route 0.055ns (35.568%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.876ns Source Clock Delay (SCD): 2.454ns Clock Pessimism Removal (CPR): 0.411ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock pclk rise edge) 0.000 0.000 r Y12 0.000 0.000 r ffclk0p (IN) net (fo=0) 0.000 0.000 clocks393_i/ibufds_ibufgds0_i/ffclk0p Y12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O net (fo=2, routed) 0.503 0.949 clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.050 0.999 r clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 0.771 1.770 clocks393_i/dual_clock_pclk_i/clk1x_pre BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.026 1.796 r clocks393_i/dual_clock_pclk_i/clk1x_i/O net (fo=4841, routed) 0.658 2.454 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[10].dly01_16_i/clk1x SLICE_X5Y20 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[10].dly01_16_i/sr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y20 FDRE (Prop_fdre_C_Q) 0.100 2.554 r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[10].dly01_16_i/sr_reg[0]/Q net (fo=1, routed) 0.055 2.609 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[10].dly01_16_i/sr_reg_n_0_[0] SLICE_X4Y20 SRL16E r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[10].dly01_16_i/sr_reg[9]_srl9/D ------------------------------------------------------------------- ------------------- (clock pclk rise edge) 0.000 0.000 r Y12 0.000 0.000 r ffclk0p (IN) net (fo=0) 0.000 0.000 clocks393_i/ibufds_ibufgds0_i/ffclk0p Y12 IBUFDS (Prop_ibufds_I_O) 0.521 0.521 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O net (fo=2, routed) 0.554 1.075 clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.053 1.128 r clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 0.840 1.968 clocks393_i/dual_clock_pclk_i/clk1x_pre BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.030 1.998 r clocks393_i/dual_clock_pclk_i/clk1x_i/O net (fo=4841, routed) 0.878 2.876 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[10].dly01_16_i/clk1x SLICE_X4Y20 SRL16E r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[10].dly01_16_i/sr_reg[9]_srl9/CLK clock pessimism -0.411 2.465 SLICE_X4Y20 SRL16E (Hold_srl16e_CLK_D) 0.102 2.567 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[10].dly01_16_i/sr_reg[9]_srl9 ------------------------------------------------------------------- required time -2.567 arrival time 2.609 ------------------------------------------------------------------- slack 0.042 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: pclk Waveform(ns): { 0.000 2.315 } Period(ns): 4.630 Sources: { clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a DSP48E1/CLK n/a 3.124 4.630 1.506 DSP48_X2Y6 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_gamma_i/table_mult/CLK Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 4.630 155.370 PLLE2_ADV_X0Y0 clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 Low Pulse Width Slow RAMD32/CLK n/a 0.910 2.315 1.405 SLICE_X32Y63 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 0.910 2.315 1.405 SLICE_X48Y66 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: gtrefclk To Clock: gtrefclk Setup : 0 Failing Endpoints, Worst Slack 3.851ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.253ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 2.553ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.851ns (required time - arrival time) Source: sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/C (rising edge-triggered cell FDRE clocked by gtrefclk {rise@0.000ns fall@3.333ns period=6.666ns}) Destination: sata_top/ahci_sata_layers_i/phy/rst_timer_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtrefclk {rise@0.000ns fall@3.333ns period=6.666ns}) Path Group: gtrefclk Path Type: Setup (Max at Slow Process Corner) Requirement: 6.666ns (gtrefclk rise@6.666ns - gtrefclk rise@0.000ns) Data Path Delay: 2.514ns (logic 0.375ns (14.917%) route 2.139ns (85.083%)) Logic Levels: 2 (LUT3=1 LUT6=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.443ns = ( 8.109 - 6.666 ) Source Clock Delay (SCD): 1.567ns Clock Pessimism Removal (CPR): 0.102ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtrefclk rise edge) 0.000 0.000 r IBUFDS_GTE2_X0Y0 IBUFDS_GTE2 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O net (fo=25, routed) 1.567 1.567 sata_top/ahci_sata_layers_i/phy/gtrefclk SLICE_X65Y48 FDRE r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y48 FDRE (Prop_fdre_C_Q) 0.269 1.836 r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/Q net (fo=7, routed) 1.131 2.968 sata_top/ahci_sata_layers_i/phy/rst_timer_reg__0[0] SLICE_X65Y49 LUT6 (Prop_lut6_I2_O) 0.053 3.021 f sata_top/ahci_sata_layers_i/phy/sata_areset_i_2/O net (fo=4, routed) 0.584 3.605 sata_top/ahci_sata_layers_i/phy/sata_areset_i_2_n_0 SLICE_X64Y49 LUT3 (Prop_lut3_I2_O) 0.053 3.658 r sata_top/ahci_sata_layers_i/phy/rst_timer[7]_i_2/O net (fo=8, routed) 0.424 4.081 sata_top/ahci_sata_layers_i/phy/rst_timer[7]_i_2_n_0 SLICE_X64Y49 FDRE r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtrefclk rise edge) 6.666 6.666 r IBUFDS_GTE2_X0Y0 IBUFDS_GTE2 0.000 6.666 r sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O net (fo=25, routed) 1.443 8.109 sata_top/ahci_sata_layers_i/phy/gtrefclk SLICE_X64Y49 FDRE r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[6]/C clock pessimism 0.102 8.211 clock uncertainty -0.035 8.176 SLICE_X64Y49 FDRE (Setup_fdre_C_CE) -0.244 7.932 sata_top/ahci_sata_layers_i/phy/rst_timer_reg[6] ------------------------------------------------------------------- required time 7.932 arrival time -4.081 ------------------------------------------------------------------- slack 3.851 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.253ns (arrival time - required time) Source: sata_top/ahci_sata_layers_i/phy/rst_timer_reg[4]/C (rising edge-triggered cell FDRE clocked by gtrefclk {rise@0.000ns fall@3.333ns period=6.666ns}) Destination: sata_top/ahci_sata_layers_i/phy/rst_timer_reg[5]/D (rising edge-triggered cell FDRE clocked by gtrefclk {rise@0.000ns fall@3.333ns period=6.666ns}) Path Group: gtrefclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtrefclk rise@0.000ns - gtrefclk rise@0.000ns) Data Path Delay: 0.314ns (logic 0.157ns (49.995%) route 0.157ns (50.005%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.657ns Source Clock Delay (SCD): 0.454ns Clock Pessimism Removal (CPR): 0.203ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtrefclk rise edge) 0.000 0.000 r IBUFDS_GTE2_X0Y0 IBUFDS_GTE2 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O net (fo=25, routed) 0.454 0.454 sata_top/ahci_sata_layers_i/phy/gtrefclk SLICE_X65Y49 FDRE r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y49 FDRE (Prop_fdre_C_Q) 0.091 0.545 r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[4]/Q net (fo=3, routed) 0.157 0.702 sata_top/ahci_sata_layers_i/phy/rst_timer_reg__0[4] SLICE_X65Y49 LUT6 (Prop_lut6_I5_O) 0.066 0.768 r sata_top/ahci_sata_layers_i/phy/rst_timer[5]_i_1/O net (fo=1, routed) 0.000 0.768 sata_top/ahci_sata_layers_i/phy/rst_timer0[5] SLICE_X65Y49 FDRE r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtrefclk rise edge) 0.000 0.000 r IBUFDS_GTE2_X0Y0 IBUFDS_GTE2 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O net (fo=25, routed) 0.657 0.657 sata_top/ahci_sata_layers_i/phy/gtrefclk SLICE_X65Y49 FDRE r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[5]/C clock pessimism -0.203 0.454 SLICE_X65Y49 FDRE (Hold_fdre_C_D) 0.061 0.515 sata_top/ahci_sata_layers_i/phy/rst_timer_reg[5] ------------------------------------------------------------------- required time -0.515 arrival time 0.768 ------------------------------------------------------------------- slack 0.253 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtrefclk Waveform(ns): { 0.000 3.333 } Period(ns): 6.666 Sources: { sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/GTREFCLK0 n/a 1.538 6.666 5.128 GTXE2_CHANNEL_X0Y0 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/GTREFCLK0 Low Pulse Width Slow SRL16E/CLK n/a 0.780 3.333 2.553 SLICE_X70Y45 sata_top/ahci_sata_layers_i/phy/rxreset_f_r_reg_srl2/CLK High Pulse Width Slow SRL16E/CLK n/a 0.780 3.333 2.553 SLICE_X70Y45 sata_top/ahci_sata_layers_i/phy/rxreset_f_r_reg_srl2/CLK --------------------------------------------------------------------------------------------------- From Clock: rx_clk To Clock: rx_clk Setup : 0 Failing Endpoints, Worst Slack 0.312ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.087ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 2.423ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.312ns (required time - arrival time) Source: sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/CLKARDCLK (rising edge-triggered cell RAMB36E1 clocked by rx_clk {rise@0.000ns fall@3.333ns period=6.666ns}) Destination: sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]/CE (rising edge-triggered cell FDRE clocked by rx_clk {rise@0.000ns fall@3.333ns period=6.666ns}) Path Group: rx_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 6.666ns (rx_clk rise@6.666ns - rx_clk rise@0.000ns) Data Path Delay: 5.885ns (logic 1.248ns (21.208%) route 4.637ns (78.792%)) Logic Levels: 7 (LUT3=4 LUT6=3) Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.673ns = ( 9.339 - 6.666 ) Source Clock Delay (SCD): 2.955ns Clock Pessimism Removal (CPR): 0.066ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rx_clk rise edge) 0.000 0.000 r GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK net (fo=1, routed) 1.349 1.349 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.120 1.469 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O net (fo=327, routed) 1.486 2.955 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/CLK RAMB36_X5Y20 RAMB36E1 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/CLKARDCLK ------------------------------------------------------------------- ------------------- RAMB36_X5Y20 RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[8]) 0.748 3.703 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/DOADO[8] net (fo=5, routed) 1.719 5.421 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/p_1_in[2] SLICE_X59Y126 LUT6 (Prop_lut6_I3_O) 0.053 5.474 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[15]_i_8/O net (fo=2, routed) 0.442 5.916 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[15]_i_8_n_0 SLICE_X59Y125 LUT6 (Prop_lut6_I4_O) 0.053 5.969 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[15]_i_5/O net (fo=7, routed) 0.540 6.509 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/data_in_r_reg[2] SLICE_X57Y126 LUT3 (Prop_lut3_I1_O) 0.065 6.574 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/is_prim_r[11]_i_3/O net (fo=2, routed) 0.240 6.813 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/RAMB36E1_i_0 SLICE_X57Y127 LUT6 (Prop_lut6_I5_O) 0.170 6.983 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[16]_i_2/O net (fo=4, routed) 0.356 7.340 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r_reg[16] SLICE_X57Y127 LUT3 (Prop_lut3_I2_O) 0.053 7.393 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_aligned_r_i_2/O net (fo=6, routed) 0.466 7.859 sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/RAMB36E1_i_0 SLICE_X55Y128 LUT3 (Prop_lut3_I1_O) 0.053 7.912 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/msb_in_r_i_1/O net (fo=2, routed) 0.444 8.356 sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/msb_in_r_i_1_n_0 SLICE_X52Y130 LUT3 (Prop_lut3_I0_O) 0.053 8.409 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/xlnx_opt_LUT_wen_reg[0]_CE_cooolgate_en_gate_1288/O net (fo=6, routed) 0.430 8.839 sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]_CE_cooolgate_en_sig_217 SLICE_X52Y130 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock rx_clk rise edge) 6.666 6.666 r GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 6.666 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK net (fo=1, routed) 1.300 7.966 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.113 8.079 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O net (fo=327, routed) 1.260 9.339 sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/CLK SLICE_X52Y130 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]/C clock pessimism 0.066 9.405 clock uncertainty -0.035 9.370 SLICE_X52Y130 FDRE (Setup_fdre_C_CE) -0.219 9.151 sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0] ------------------------------------------------------------------- required time 9.151 arrival time -8.839 ------------------------------------------------------------------- slack 0.312 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.087ns (arrival time - required time) Source: sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/data_in_r_reg[13]/C (rising edge-triggered cell FDRE clocked by rx_clk {rise@0.000ns fall@3.333ns period=6.666ns}) Destination: sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/is_prim_r_reg[2]/D (rising edge-triggered cell FDRE clocked by rx_clk {rise@0.000ns fall@3.333ns period=6.666ns}) Path Group: rx_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rx_clk rise@0.000ns - rx_clk rise@0.000ns) Data Path Delay: 0.339ns (logic 0.128ns (37.765%) route 0.211ns (62.235%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.192ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.068ns Clock Pessimism Removal (CPR): 0.049ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rx_clk rise edge) 0.000 0.000 r GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK net (fo=1, routed) 0.526 0.526 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.552 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O net (fo=327, routed) 0.516 1.068 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/CLK SLICE_X59Y127 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/data_in_r_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y127 FDRE (Prop_fdre_C_Q) 0.100 1.168 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/data_in_r_reg[13]/Q net (fo=14, routed) 0.211 1.379 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/data_in_r_reg[13][0] SLICE_X57Y126 LUT6 (Prop_lut6_I5_O) 0.028 1.407 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/is_prim_r[2]_i_1/O net (fo=1, routed) 0.000 1.407 sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/RAMB36E1_i_9 SLICE_X57Y126 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/is_prim_r_reg[2]/D ------------------------------------------------------------------- ------------------- (clock rx_clk rise edge) 0.000 0.000 r GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK net (fo=1, routed) 0.563 0.563 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.030 0.593 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O net (fo=327, routed) 0.716 1.309 sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/CLK SLICE_X57Y126 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/is_prim_r_reg[2]/C clock pessimism -0.049 1.260 SLICE_X57Y126 FDRE (Hold_fdre_C_D) 0.060 1.320 sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/is_prim_r_reg[2] ------------------------------------------------------------------- required time -1.320 arrival time 1.407 ------------------------------------------------------------------- slack 0.087 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rx_clk Waveform(ns): { 0.000 3.333 } Period(ns): 6.666 Sources: { sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 4.000 6.666 2.666 GTXE2_CHANNEL_X0Y0 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXUSRCLK Low Pulse Width Fast RAMD32/CLK n/a 0.910 3.333 2.423 SLICE_X62Y127 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_24_29/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 0.910 3.333 2.423 SLICE_X58Y125 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: txoutclk To Clock: txoutclk Setup : 0 Failing Endpoints, Worst Slack 2.057ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.179ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 2.666ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.057ns (required time - arrival time) Source: sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[11]/C (rising edge-triggered cell FDRE clocked by txoutclk {rise@0.000ns fall@3.333ns period=6.666ns}) Destination: sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/ADDRBWRADDR[8] (rising edge-triggered cell RAMB36E1 clocked by txoutclk {rise@0.000ns fall@3.333ns period=6.666ns}) Path Group: txoutclk Path Type: Setup (Max at Slow Process Corner) Requirement: 6.666ns (txoutclk rise@6.666ns - txoutclk rise@0.000ns) Data Path Delay: 4.163ns (logic 0.282ns (6.774%) route 3.881ns (93.226%)) Logic Levels: 0 Clock Path Skew: 0.173ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.968ns = ( 9.634 - 6.666 ) Source Clock Delay (SCD): 2.851ns Clock Pessimism Removal (CPR): 0.056ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk rise edge) 0.000 0.000 r GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK net (fo=1, routed) 1.349 1.349 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.120 1.469 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O net (fo=136, routed) 1.382 2.851 sata_top/ahci_sata_layers_i/phy/gtx_wrap/CLK SLICE_X54Y115 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y115 FDRE (Prop_fdre_C_Q) 0.282 3.133 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[11]/Q net (fo=1, routed) 3.881 7.014 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/ADDRBWRADDR[3] RAMB36_X6Y5 RAMB36E1 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/ADDRBWRADDR[8] ------------------------------------------------------------------- ------------------- (clock txoutclk rise edge) 6.666 6.666 r GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 6.666 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK net (fo=1, routed) 1.300 7.966 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.113 8.079 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O net (fo=136, routed) 1.555 9.634 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/CLK RAMB36_X6Y5 RAMB36E1 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/CLKBWRCLK clock pessimism 0.056 9.690 clock uncertainty -0.035 9.654 RAMB36_X6Y5 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[8]) -0.583 9.071 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i ------------------------------------------------------------------- required time 9.071 arrival time -7.014 ------------------------------------------------------------------- slack 2.057 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.179ns (arrival time - required time) Source: sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/table1_r_reg[18]/C (rising edge-triggered cell FDRE clocked by txoutclk {rise@0.000ns fall@3.333ns period=6.666ns}) Destination: sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[18]/D (rising edge-triggered cell FDRE clocked by txoutclk {rise@0.000ns fall@3.333ns period=6.666ns}) Path Group: txoutclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk rise@0.000ns - txoutclk rise@0.000ns) Data Path Delay: 0.270ns (logic 0.155ns (57.355%) route 0.115ns (42.645%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.434ns Source Clock Delay (SCD): 1.174ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk rise edge) 0.000 0.000 r GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK net (fo=1, routed) 0.526 0.526 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 0.552 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O net (fo=136, routed) 0.622 1.174 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/CLK SLICE_X109Y25 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/table1_r_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y25 FDRE (Prop_fdre_C_Q) 0.091 1.265 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/table1_r_reg[18]/Q net (fo=2, routed) 0.115 1.380 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/table1_r[18] SLICE_X110Y25 LUT3 (Prop_lut3_I0_O) 0.064 1.444 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l[18]_i_1/O net (fo=1, routed) 0.000 1.444 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/enc1[8] SLICE_X110Y25 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[18]/D ------------------------------------------------------------------- ------------------- (clock txoutclk rise edge) 0.000 0.000 r GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK net (fo=1, routed) 0.563 0.563 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 0.593 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O net (fo=136, routed) 0.841 1.434 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/CLK SLICE_X110Y25 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[18]/C clock pessimism -0.229 1.205 SLICE_X110Y25 FDRE (Hold_fdre_C_D) 0.060 1.265 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[18] ------------------------------------------------------------------- required time -1.265 arrival time 1.444 ------------------------------------------------------------------- slack 0.179 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txoutclk Waveform(ns): { 0.000 3.333 } Period(ns): 6.666 Sources: { sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 4.000 6.666 2.666 GTXE2_CHANNEL_X0Y0 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXUSRCLK Low Pulse Width Slow FDRE/C n/a 0.400 3.333 2.933 SLICE_X54Y115 sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[11]/C High Pulse Width Slow FDCE/C n/a 0.350 3.333 2.983 SLICE_X52Y118 sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/data_out_reg[0]/C --------------------------------------------------------------------------------------------------- From Clock: usrclk2 To Clock: usrclk2 Setup : 0 Failing Endpoints, Worst Slack 4.647ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.059ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 5.756ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.647ns (required time - arrival time) Source: sata_top/ahci_sata_layers_i/link/phy_data_in_r_reg[22]/C (rising edge-triggered cell FDRE clocked by usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns}) Destination: sata_top/ahci_sata_layers_i/link/crc/crc_reg[5]/D (rising edge-triggered cell FDSE clocked by usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns}) Path Group: usrclk2 Path Type: Setup (Max at Slow Process Corner) Requirement: 13.333ns (usrclk2 rise@13.333ns - usrclk2 rise@0.000ns) Data Path Delay: 8.580ns (logic 1.044ns (12.168%) route 7.536ns (87.832%)) Logic Levels: 9 (LUT4=4 LUT6=5) Clock Path Skew: -0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.914ns = ( 16.247 - 13.333 ) Source Clock Delay (SCD): 3.300ns Clock Pessimism Removal (CPR): 0.280ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock usrclk2 rise edge) 0.000 0.000 r SLICE_X61Y50 FDRE 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q net (fo=2, routed) 1.794 1.794 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r BUFGCTRL_X0Y5 BUFG (Prop_bufg_I_O) 0.120 1.914 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O net (fo=2023, routed) 1.386 3.300 sata_top/ahci_sata_layers_i/link/usrclk2_r_reg SLICE_X62Y135 FDRE r sata_top/ahci_sata_layers_i/link/phy_data_in_r_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y135 FDRE (Prop_fdre_C_Q) 0.308 3.608 r sata_top/ahci_sata_layers_i/link/phy_data_in_r_reg[22]/Q net (fo=10, routed) 1.094 4.702 sata_top/ahci_sata_layers_i/link/crc/Q[22] SLICE_X57Y136 LUT4 (Prop_lut4_I2_O) 0.067 4.769 f sata_top/ahci_sata_layers_i/link/crc/data_val_out_r_i_29/O net (fo=1, routed) 0.559 5.328 sata_top/ahci_sata_layers_i/link/crc/data_val_out_r_i_29_n_0 SLICE_X58Y136 LUT6 (Prop_lut6_I0_O) 0.170 5.498 f sata_top/ahci_sata_layers_i/link/crc/xlnx_opt_LUT_data_val_out_r_i_10_1/O net (fo=1, routed) 0.331 5.829 sata_top/ahci_sata_layers_i/link/crc/xlnx_opt_data_val_out_r_i_10_n_0 SLICE_X58Y136 LUT6 (Prop_lut6_I5_O) 0.053 5.882 r sata_top/ahci_sata_layers_i/link/crc/xlnx_opt_LUT_data_val_out_r_i_10_2/O net (fo=3, routed) 0.989 6.871 sata_top/ahci_sata_layers_i/link/crc/data_val_out_r_i_10_n_0 SLICE_X52Y137 LUT4 (Prop_lut4_I0_O) 0.066 6.937 r sata_top/ahci_sata_layers_i/link/crc/data_val_out_r_i_4/O net (fo=2, routed) 0.579 7.516 sata_top/ahci_sata_layers_i/link/crc/data_val_out_r_i_4_n_0 SLICE_X54Y137 LUT6 (Prop_lut6_I2_O) 0.168 7.684 r sata_top/ahci_sata_layers_i/link/crc/data_val_out_r_i_1/O net (fo=103, routed) 0.920 8.605 sata_top/ahci_sata_layers_i/link/crc/inc_is_data SLICE_X48Y143 LUT4 (Prop_lut4_I0_O) 0.053 8.658 r sata_top/ahci_sata_layers_i/link/crc/now[15]_i_2/O net (fo=84, routed) 1.245 9.903 sata_top/ahci_sata_layers_i/link/crc/val_in0 SLICE_X54Y136 LUT6 (Prop_lut6_I2_O) 0.053 9.956 r sata_top/ahci_sata_layers_i/link/crc/crc[31]_i_10/O net (fo=11, routed) 1.142 11.098 sata_top/ahci_sata_layers_i/link/crc/crc[31]_i_10_n_0 SLICE_X45Y143 LUT4 (Prop_lut4_I2_O) 0.053 11.151 r sata_top/ahci_sata_layers_i/link/crc/crc[30]_i_5/O net (fo=4, routed) 0.676 11.827 sata_top/ahci_sata_layers_i/link/crc/crc[30]_i_5_n_0 SLICE_X49Y142 LUT6 (Prop_lut6_I0_O) 0.053 11.880 r sata_top/ahci_sata_layers_i/link/crc/crc[5]_i_1/O net (fo=1, routed) 0.000 11.880 sata_top/ahci_sata_layers_i/link/crc/crc047_out SLICE_X49Y142 FDSE r sata_top/ahci_sata_layers_i/link/crc/crc_reg[5]/D ------------------------------------------------------------------- ------------------- (clock usrclk2 rise edge) 13.333 13.333 r SLICE_X61Y50 FDRE 0.000 13.333 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q net (fo=2, routed) 1.531 14.864 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r BUFGCTRL_X0Y5 BUFG (Prop_bufg_I_O) 0.113 14.977 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O net (fo=2023, routed) 1.270 16.247 sata_top/ahci_sata_layers_i/link/crc/usrclk2_r_reg SLICE_X49Y142 FDSE r sata_top/ahci_sata_layers_i/link/crc/crc_reg[5]/C clock pessimism 0.280 16.527 clock uncertainty -0.035 16.492 SLICE_X49Y142 FDSE (Setup_fdse_C_D) 0.035 16.527 sata_top/ahci_sata_layers_i/link/crc/crc_reg[5] ------------------------------------------------------------------- required time 16.527 arrival time -11.880 ------------------------------------------------------------------- slack 4.647 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.059ns (arrival time - required time) Source: sata_top/ahci_sata_layers_i/fifo_d2h_control_i/mem_ra_reg[2]/C (rising edge-triggered cell FDRE clocked by usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns}) Destination: sata_top/ahci_sata_layers_i/fifo_d2h_i/ram_i/RAMB36E1_i/ADDRARDADDR[7] (rising edge-triggered cell RAMB18E1 clocked by usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns}) Path Group: usrclk2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (usrclk2 rise@0.000ns - usrclk2 rise@0.000ns) Data Path Delay: 0.289ns (logic 0.118ns (40.798%) route 0.171ns (59.202%)) Logic Levels: 0 Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.760ns Source Clock Delay (SCD): 1.376ns Clock Pessimism Removal (CPR): 0.336ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock usrclk2 rise edge) 0.000 0.000 r SLICE_X61Y50 FDRE 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q net (fo=2, routed) 0.828 0.828 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r BUFGCTRL_X0Y5 BUFG (Prop_bufg_I_O) 0.026 0.854 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O net (fo=2023, routed) 0.522 1.376 sata_top/ahci_sata_layers_i/fifo_d2h_control_i/usrclk2_r_reg SLICE_X54Y131 FDRE r sata_top/ahci_sata_layers_i/fifo_d2h_control_i/mem_ra_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y131 FDRE (Prop_fdre_C_Q) 0.118 1.494 r sata_top/ahci_sata_layers_i/fifo_d2h_control_i/mem_ra_reg[2]/Q net (fo=6, routed) 0.171 1.665 sata_top/ahci_sata_layers_i/fifo_d2h_i/ram_i/mem_ra_reg[8][2] RAMB18_X3Y52 RAMB18E1 r sata_top/ahci_sata_layers_i/fifo_d2h_i/ram_i/RAMB36E1_i/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock usrclk2 rise edge) 0.000 0.000 r SLICE_X61Y50 FDRE 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q net (fo=2, routed) 0.968 0.968 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r BUFGCTRL_X0Y5 BUFG (Prop_bufg_I_O) 0.030 0.998 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O net (fo=2023, routed) 0.762 1.760 sata_top/ahci_sata_layers_i/fifo_d2h_i/ram_i/usrclk2_r_reg RAMB18_X3Y52 RAMB18E1 r sata_top/ahci_sata_layers_i/fifo_d2h_i/ram_i/RAMB36E1_i/CLKARDCLK clock pessimism -0.336 1.424 RAMB18_X3Y52 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) 0.183 1.607 sata_top/ahci_sata_layers_i/fifo_d2h_i/ram_i/RAMB36E1_i ------------------------------------------------------------------- required time -1.607 arrival time 1.665 ------------------------------------------------------------------- slack 0.059 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: usrclk2 Waveform(ns): { 0.000 6.666 } Period(ns): 13.333 Sources: { sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E1/CLKARDCLK n/a 2.183 13.333 11.150 RAMB36_X2Y25 sata_top/ahci_top_i/ahci_dma_i/ct_data_ram_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMD32/CLK n/a 0.910 6.667 5.757 SLICE_X30Y138 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/fifo0_ram_reg_0_7_24_29/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 0.910 6.666 5.756 SLICE_X30Y135 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/fifo0_ram_reg_0_7_12_17/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: ddr3_clk_div To Clock: ddr3_clk Setup : 0 Failing Endpoints, Worst Slack 0.084ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.155ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.084ns (required time - arrival time) Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C (rising edge-triggered cell FDSE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/oserdes_i/T1 (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: ddr3_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (ddr3_clk rise@2.500ns - ddr3_clk_div rise@0.000ns) Data Path Delay: 1.515ns (logic 0.269ns (17.756%) route 1.246ns (82.244%)) Logic Levels: 0 Clock Path Skew: -0.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.645ns = ( 6.145 - 2.500 ) Source Clock Delay (SCD): 3.805ns Clock Pessimism Removal (CPR): 0.143ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.156ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ddr3_clk_div rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.575 1.575 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) 0.088 1.663 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 net (fo=1, routed) 1.106 2.769 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.377 3.146 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O net (fo=753, routed) 0.659 3.805 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg SLICE_X117Y137 FDSE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X117Y137 FDSE (Prop_fdse_C_Q) 0.269 4.074 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/Q net (fo=23, routed) 1.246 5.320 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/in_tri_r_reg OLOGIC_X1Y101 OSERDESE2 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/oserdes_i/T1 ------------------------------------------------------------------- ------------------- (clock ddr3_clk rise edge) 2.500 2.500 r BUFGCTRL_X0Y23 BUFG 0.000 2.500 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.437 3.937 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) 0.083 4.020 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 net (fo=1, routed) 1.016 5.036 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_pre BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.370 5.406 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/O net (fo=75, routed) 0.739 6.145 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/clk OLOGIC_X1Y101 OSERDESE2 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/oserdes_i/CLK clock pessimism 0.143 6.288 clock uncertainty -0.205 6.083 OLOGIC_X1Y101 OSERDESE2 (Setup_oserdese2_CLK_T1) -0.679 5.404 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/oserdes_i ------------------------------------------------------------------- required time 5.404 arrival time -5.320 ------------------------------------------------------------------- slack 0.084 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.155ns (arrival time - required time) Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C (rising edge-triggered cell FDSE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[11].cmda_addr_i/oserdes_i/oserdes_i/T1 (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: ddr3_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ddr3_clk rise@0.000ns - ddr3_clk_div rise@0.000ns) Data Path Delay: 0.413ns (logic 0.100ns (24.228%) route 0.313ns (75.772%)) Logic Levels: 0 Clock Path Skew: 0.156ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.800ns Source Clock Delay (SCD): 1.425ns Clock Pessimism Removal (CPR): 0.219ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.156ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ddr3_clk_div rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.580 0.580 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) 0.050 0.630 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 net (fo=1, routed) 0.433 1.063 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.090 1.153 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O net (fo=753, routed) 0.272 1.425 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg SLICE_X117Y137 FDSE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X117Y137 FDSE (Prop_fdse_C_Q) 0.100 1.525 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/Q net (fo=23, routed) 0.313 1.838 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[11].cmda_addr_i/oserdes_i/in_tri_r_reg OLOGIC_X1Y141 OSERDESE2 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[11].cmda_addr_i/oserdes_i/oserdes_i/T1 ------------------------------------------------------------------- ------------------- (clock ddr3_clk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.796 0.796 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) 0.053 0.849 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 net (fo=1, routed) 0.490 1.339 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_pre BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.093 1.432 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/O net (fo=75, routed) 0.368 1.800 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[11].cmda_addr_i/oserdes_i/clk OLOGIC_X1Y141 OSERDESE2 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[11].cmda_addr_i/oserdes_i/oserdes_i/CLK clock pessimism -0.219 1.581 clock uncertainty 0.205 1.786 OLOGIC_X1Y141 OSERDESE2 (Hold_oserdese2_CLK_T1) -0.104 1.682 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[11].cmda_addr_i/oserdes_i/oserdes_i ------------------------------------------------------------------- required time -1.682 arrival time 1.838 ------------------------------------------------------------------- slack 0.155 --------------------------------------------------------------------------------------------------- From Clock: ddr3_mclk To Clock: ddr3_clk_div Setup : 0 Failing Endpoints, Worst Slack 0.006ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.357ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.006ns (required time - arrival time) Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK (rising edge-triggered cell RAMB36E1 clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns}) Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/tin_dqs_r_reg[1]/D (rising edge-triggered cell FDSE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: ddr3_clk_div Path Type: Setup (Max at Slow Process Corner) Requirement: 3.750ns (ddr3_clk_div rise@5.000ns - ddr3_mclk rise@1.250ns) Data Path Delay: 2.414ns (logic 0.854ns (35.381%) route 1.560ns (64.619%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -1.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.628ns = ( 8.628 - 5.000 ) Source Clock Delay (SCD): 4.878ns = ( 6.128 - 1.250 ) Clock Pessimism Removal (CPR): 0.143ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.156ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ddr3_mclk rise edge) 1.250 1.250 r BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.575 2.825 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) 0.088 2.913 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 net (fo=1, routed) 1.628 4.541 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.120 4.661 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O net (fo=33128, routed) 1.467 6.128 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/CLK RAMB36_X5Y24 RAMB36E1 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK ------------------------------------------------------------------- ------------------- RAMB36_X5Y24 RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[6]) 0.748 6.876 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/DOADO[6] net (fo=1, routed) 0.704 7.579 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_0[5] SLICE_X91Y126 LUT4 (Prop_lut4_I3_O) 0.053 7.632 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/extra_prev[5]_i_1/O net (fo=6, routed) 0.370 8.002 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/RAMB36E1_i[0] SLICE_X90Y127 LUT6 (Prop_lut6_I1_O) 0.053 8.055 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/tin_dqs_r[1]_i_1/O net (fo=2, routed) 0.486 8.541 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/tin_dqs[1] SLICE_X89Y126 FDSE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/tin_dqs_r_reg[1]/D ------------------------------------------------------------------- ------------------- (clock ddr3_clk_div rise edge) 5.000 5.000 r BUFGCTRL_X0Y23 BUFG 0.000 5.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.437 6.437 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) 0.083 6.520 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 net (fo=1, routed) 1.016 7.536 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.370 7.906 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O net (fo=753, routed) 0.722 8.628 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/psincdec_reg_0 SLICE_X89Y126 FDSE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/tin_dqs_r_reg[1]/C clock pessimism 0.143 8.771 clock uncertainty -0.205 8.566 SLICE_X89Y126 FDSE (Setup_fdse_C_D) -0.018 8.548 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/tin_dqs_r_reg[1] ------------------------------------------------------------------- required time 8.548 arrival time -8.541 ------------------------------------------------------------------- slack 0.006 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.357ns (arrival time - required time) Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/deser_r_reg[1]/C (rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns}) Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[1]/D (rising edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: ddr3_clk_div Path Type: Hold (Min at Fast Process Corner) Requirement: -1.250ns (ddr3_clk_div rise@0.000ns - ddr3_mclk rise@1.250ns) Data Path Delay: 0.199ns (logic 0.100ns (50.292%) route 0.099ns (49.707%)) Logic Levels: 0 Clock Path Skew: -0.146ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.808ns Source Clock Delay (SCD): 1.735ns = ( 2.985 - 1.250 ) Clock Pessimism Removal (CPR): 0.219ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.156ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ddr3_mclk rise edge) 1.250 1.250 r BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.580 1.830 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) 0.050 1.880 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 net (fo=1, routed) 0.559 2.439 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 2.465 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O net (fo=33128, routed) 0.520 2.985 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/CLK SLICE_X71Y121 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/deser_r_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y121 FDRE (Prop_fdre_C_Q) 0.100 3.085 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/deser_r_reg[1]/Q net (fo=1, routed) 0.099 3.184 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/deser_r_reg[6][1] SLICE_X71Y120 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[1]/D ------------------------------------------------------------------- ------------------- (clock ddr3_clk_div rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.796 0.796 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) 0.053 0.849 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 net (fo=1, routed) 0.490 1.339 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.093 1.432 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O net (fo=753, routed) 0.376 1.808 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div SLICE_X71Y120 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[1]/C clock pessimism -0.219 1.589 clock uncertainty 0.205 1.794 SLICE_X71Y120 FDRE (Hold_fdre_C_D) 0.032 1.826 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[1] ------------------------------------------------------------------- required time -1.826 arrival time 3.184 ------------------------------------------------------------------- slack 1.357 --------------------------------------------------------------------------------------------------- From Clock: ddr3_clk_div To Clock: ddr3_mclk Setup : 0 Failing Endpoints, Worst Slack 2.860ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.273ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.860ns (required time - arrival time) Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[7].dq_i/iserdes_mem_i/iserdes_i/CLKDIV (rising edge-triggered cell ISERDESE2 clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata_r_reg[7]/D (falling edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns}) Path Group: ddr3_mclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.750ns (ddr3_mclk fall@3.750ns - ddr3_clk_div rise@0.000ns) Data Path Delay: 1.536ns (logic 0.573ns (37.294%) route 0.963ns (62.706%)) Logic Levels: 0 Clock Path Skew: 0.854ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.507ns = ( 8.257 - 3.750 ) Source Clock Delay (SCD): 3.796ns Clock Pessimism Removal (CPR): 0.143ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.156ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ddr3_clk_div rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.575 1.575 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) 0.088 1.663 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 net (fo=1, routed) 1.106 2.769 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.377 3.146 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O net (fo=753, routed) 0.650 3.796 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[7].dq_i/iserdes_mem_i/psincdec_reg ILOGIC_X1Y116 ISERDESE2 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[7].dq_i/iserdes_mem_i/iserdes_i/CLKDIV ------------------------------------------------------------------- ------------------- ILOGIC_X1Y116 ISERDESE2 (Prop_iserdese2_CLKDIV_Q4) 0.573 4.369 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[7].dq_i/iserdes_mem_i/iserdes_i/Q4 net (fo=1, routed) 0.963 5.332 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata[7] SLICE_X102Y117 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata_r_reg[7]/D ------------------------------------------------------------------- ------------------- (clock ddr3_mclk fall edge) 3.750 3.750 f BUFGCTRL_X0Y23 BUFG 0.000 3.750 f clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.437 5.187 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) 0.083 5.270 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 net (fo=1, routed) 1.544 6.814 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.113 6.927 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O net (fo=33128, routed) 1.330 8.257 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/CLK SLICE_X102Y117 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata_r_reg[7]/C (IS_INVERTED) clock pessimism 0.143 8.400 clock uncertainty -0.205 8.195 SLICE_X102Y117 FDRE (Setup_fdre_C_D) -0.002 8.193 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata_r_reg[7] ------------------------------------------------------------------- required time 8.193 arrival time -5.332 ------------------------------------------------------------------- slack 2.860 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.273ns (arrival time - required time) Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[4]/C (falling edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[4]/D (rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns}) Path Group: ddr3_mclk Path Type: Hold (Min at Slow Process Corner) Requirement: -1.250ns (ddr3_mclk rise@1.250ns - ddr3_clk_div fall@2.500ns) Data Path Delay: 0.425ns (logic 0.218ns (51.320%) route 0.207ns (48.680%)) Logic Levels: 0 Clock Path Skew: 1.009ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 4.802ns = ( 6.052 - 1.250 ) Source Clock Delay (SCD): 3.650ns = ( 6.150 - 2.500 ) Clock Pessimism Removal (CPR): 0.143ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.156ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ddr3_clk_div fall edge) 2.500 2.500 f BUFGCTRL_X0Y23 BUFG 0.000 2.500 f clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.437 3.937 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) 0.083 4.020 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 net (fo=1, routed) 1.016 5.036 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.370 5.406 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O net (fo=753, routed) 0.744 6.150 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div SLICE_X67Y106 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[4]/C (IS_INVERTED) ------------------------------------------------------------------- ------------------- SLICE_X67Y106 FDRE (Prop_fdre_C_Q) 0.218 6.368 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[4]/Q net (fo=1, routed) 0.207 6.575 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1[4] SLICE_X66Y106 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[4]/D ------------------------------------------------------------------- ------------------- (clock ddr3_mclk rise edge) 1.250 1.250 r BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.575 2.825 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) 0.088 2.913 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 net (fo=1, routed) 1.628 4.541 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.120 4.661 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O net (fo=33128, routed) 1.391 6.052 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/CLK SLICE_X66Y106 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[4]/C clock pessimism -0.143 5.909 clock uncertainty 0.205 6.114 SLICE_X66Y106 FDRE (Hold_fdre_C_D) 0.187 6.301 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[4] ------------------------------------------------------------------- required time -6.301 arrival time 6.575 ------------------------------------------------------------------- slack 0.273 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: axihp_clk To Clock: axihp_clk Setup : 0 Failing Endpoints, Worst Slack 1.841ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.617ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.841ns (required time - arrival time) Source: sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C (rising edge-triggered cell FDRE clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns}) Destination: mult_saxi_wr_i/status_wr_i/in_reg_reg/CLR (recovery check against rising-edge clock axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.667ns (axihp_clk rise@6.667ns - axihp_clk rise@0.000ns) Data Path Delay: 4.409ns (logic 0.282ns (6.396%) route 4.127ns (93.604%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.583ns = ( 11.250 - 6.667 ) Source Clock Delay (SCD): 4.817ns Clock Pessimism Removal (CPR): 0.246ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axihp_clk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.602 1.602 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.088 1.690 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 1.621 3.311 clocks393_i/hclk_i/hclk_pre BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.120 3.431 r clocks393_i/hclk_i/clk1x_i/O net (fo=3868, routed) 1.386 4.817 sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk SLICE_X34Y113 FDRE r sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X34Y113 FDRE (Prop_fdre_C_Q) 0.282 5.099 f sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q net (fo=335, routed) 4.127 9.226 mult_saxi_wr_i/status_wr_i/rst[0] SLICE_X35Y174 FDCE f mult_saxi_wr_i/status_wr_i/in_reg_reg/CLR ------------------------------------------------------------------- ------------------- (clock axihp_clk rise edge) 6.667 6.667 r BUFGCTRL_X0Y23 BUFG 0.000 6.667 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.461 8.128 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.083 8.211 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 1.538 9.749 clocks393_i/hclk_i/hclk_pre BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.113 9.862 r clocks393_i/hclk_i/clk1x_i/O net (fo=3868, routed) 1.388 11.250 mult_saxi_wr_i/status_wr_i/hclk SLICE_X35Y174 FDCE r mult_saxi_wr_i/status_wr_i/in_reg_reg/C clock pessimism 0.246 11.496 clock uncertainty -0.071 11.424 SLICE_X35Y174 FDCE (Recov_fdce_C_CLR) -0.357 11.067 mult_saxi_wr_i/status_wr_i/in_reg_reg ------------------------------------------------------------------- required time 11.067 arrival time -9.226 ------------------------------------------------------------------- slack 1.841 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.617ns (arrival time - required time) Source: sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C (rising edge-triggered cell FDRE clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns}) Destination: sata_top/ahci_top_i/axi_ahci_regs_i/afi_cache_set_i/in_reg_reg/CLR (removal check against rising-edge clock axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (axihp_clk rise@0.000ns - axihp_clk rise@0.000ns) Data Path Delay: 0.563ns (logic 0.107ns (18.996%) route 0.456ns (81.004%)) Logic Levels: 0 Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.281ns Source Clock Delay (SCD): 1.767ns Clock Pessimism Removal (CPR): 0.463ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axihp_clk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.586 0.586 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.050 0.636 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 0.577 1.213 clocks393_i/hclk_i/hclk_pre BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 1.239 r clocks393_i/hclk_i/clk1x_i/O net (fo=3868, routed) 0.528 1.767 sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk SLICE_X34Y113 FDRE r sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X34Y113 FDRE (Prop_fdre_C_Q) 0.107 1.874 f sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q net (fo=335, routed) 0.456 2.330 sata_top/ahci_top_i/axi_ahci_regs_i/afi_cache_set_i/regs_reg[1][0] SLICE_X29Y114 FDCE f sata_top/ahci_top_i/axi_ahci_regs_i/afi_cache_set_i/in_reg_reg/CLR ------------------------------------------------------------------- ------------------- (clock axihp_clk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.803 0.803 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.053 0.856 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 0.643 1.499 clocks393_i/hclk_i/hclk_pre BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.030 1.529 r clocks393_i/hclk_i/clk1x_i/O net (fo=3868, routed) 0.752 2.281 sata_top/ahci_top_i/axi_ahci_regs_i/afi_cache_set_i/hclk SLICE_X29Y114 FDCE r sata_top/ahci_top_i/axi_ahci_regs_i/afi_cache_set_i/in_reg_reg/C clock pessimism -0.463 1.818 SLICE_X29Y114 FDCE (Remov_fdce_C_CLR) -0.105 1.713 sata_top/ahci_top_i/axi_ahci_regs_i/afi_cache_set_i/in_reg_reg ------------------------------------------------------------------- required time -1.713 arrival time 2.330 ------------------------------------------------------------------- slack 0.617 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: ddr3_mclk To Clock: ddr3_mclk Setup : 0 Failing Endpoints, Worst Slack 0.375ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.275ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.375ns (required time - arrival time) Source: sync_resets_i/rst_early_master_reg_replica_23/C (rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns}) Destination: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_xfer_done_i/in_reg_reg/CLR (recovery check against rising-edge clock ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 5.000ns (ddr3_mclk rise@6.250ns - ddr3_mclk rise@1.250ns) Data Path Delay: 4.223ns (logic 0.246ns (5.825%) route 3.977ns (94.175%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.520ns = ( 10.770 - 6.250 ) Source Clock Delay (SCD): 4.796ns = ( 6.046 - 1.250 ) Clock Pessimism Removal (CPR): 0.316ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.156ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ddr3_mclk rise edge) 1.250 1.250 r BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.575 2.825 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) 0.088 2.913 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 net (fo=1, routed) 1.628 4.541 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.120 4.661 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O net (fo=33128, routed) 1.385 6.046 sync_resets_i/mclk SLICE_X35Y78 FDRE r sync_resets_i/rst_early_master_reg_replica_23/C ------------------------------------------------------------------- ------------------- SLICE_X35Y78 FDRE (Prop_fdre_C_Q) 0.246 6.292 f sync_resets_i/rst_early_master_reg_replica_23/Q net (fo=325, routed) 3.977 10.269 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_xfer_done_i/rst[0]_repN_23_alias SLICE_X25Y61 FDCE f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_xfer_done_i/in_reg_reg/CLR ------------------------------------------------------------------- ------------------- (clock ddr3_mclk rise edge) 6.250 6.250 r BUFGCTRL_X0Y23 BUFG 0.000 6.250 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.437 7.687 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) 0.083 7.770 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 net (fo=1, routed) 1.544 9.314 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.113 9.427 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O net (fo=33128, routed) 1.343 10.770 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_xfer_done_i/mclk SLICE_X25Y61 FDCE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_xfer_done_i/in_reg_reg/C clock pessimism 0.316 11.086 clock uncertainty -0.085 11.001 SLICE_X25Y61 FDCE (Recov_fdce_C_CLR) -0.357 10.644 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_xfer_done_i/in_reg_reg ------------------------------------------------------------------- required time 10.644 arrival time -10.269 ------------------------------------------------------------------- slack 0.375 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.275ns (arrival time - required time) Source: sync_resets_i/rst_early_master_reg_replica_4/C (rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns}) Destination: compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_raw_buf_iface_i/page_ready_i/in_reg_reg/CLR (removal check against rising-edge clock ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ddr3_mclk rise@1.250ns - ddr3_mclk rise@1.250ns) Data Path Delay: 0.217ns (logic 0.100ns (46.061%) route 0.117ns (53.939%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.320ns = ( 3.570 - 1.250 ) Source Clock Delay (SCD): 1.812ns = ( 3.062 - 1.250 ) Clock Pessimism Removal (CPR): 0.497ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ddr3_mclk rise edge) 1.250 1.250 r BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.580 1.830 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) 0.050 1.880 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 net (fo=1, routed) 0.559 2.439 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 2.465 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O net (fo=33128, routed) 0.597 3.062 sync_resets_i/mclk SLICE_X68Y39 FDRE r sync_resets_i/rst_early_master_reg_replica_4/C ------------------------------------------------------------------- ------------------- SLICE_X68Y39 FDRE (Prop_fdre_C_Q) 0.100 3.162 f sync_resets_i/rst_early_master_reg_replica_4/Q net (fo=240, routed) 0.117 3.279 compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_raw_buf_iface_i/page_ready_i/rst[0]_repN_4_alias SLICE_X69Y39 FDCE f compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_raw_buf_iface_i/page_ready_i/in_reg_reg/CLR ------------------------------------------------------------------- ------------------- (clock ddr3_mclk rise edge) 1.250 1.250 r BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.796 2.046 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) 0.053 2.099 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 net (fo=1, routed) 0.623 2.722 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.030 2.752 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O net (fo=33128, routed) 0.818 3.570 compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_raw_buf_iface_i/page_ready_i/mclk SLICE_X69Y39 FDCE r compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_raw_buf_iface_i/page_ready_i/in_reg_reg/C clock pessimism -0.497 3.073 SLICE_X69Y39 FDCE (Remov_fdce_C_CLR) -0.069 3.004 compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_raw_buf_iface_i/page_ready_i/in_reg_reg ------------------------------------------------------------------- required time -3.004 arrival time 3.279 ------------------------------------------------------------------- slack 0.275 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: pclk To Clock: pclk Setup : 0 Failing Endpoints, Worst Slack 0.508ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.356ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.508ns (required time - arrival time) Source: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_10398_i/prst_with_sens_mrst_reg[0]/C (rising edge-triggered cell FDPE clocked by pclk {rise@0.000ns fall@2.315ns period=4.630ns}) Destination: sensors393_i/sensor_channel_block[0].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/CLR (recovery check against rising-edge clock pclk {rise@0.000ns fall@2.315ns period=4.630ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 4.630ns (pclk rise@4.630ns - pclk rise@0.000ns) Data Path Delay: 3.328ns (logic 0.269ns (8.084%) route 3.059ns (91.916%)) Logic Levels: 0 Clock Path Skew: -0.424ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.377ns = ( 10.006 - 4.630 ) Source Clock Delay (SCD): 6.083ns Clock Pessimism Removal (CPR): 0.282ns Clock Uncertainty: 0.115ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.219ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock pclk rise edge) 0.000 0.000 r Y12 0.000 0.000 r ffclk0p (IN) net (fo=0) 0.000 0.000 clocks393_i/ibufds_ibufgds0_i/ffclk0p Y12 IBUFDS (Prop_ibufds_I_O) 0.906 0.906 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O net (fo=2, routed) 1.253 2.159 clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.088 2.247 r clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 2.009 4.256 clocks393_i/dual_clock_pclk_i/clk1x_pre BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.120 4.376 r clocks393_i/dual_clock_pclk_i/clk1x_i/O net (fo=4841, routed) 1.707 6.083 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_10398_i/clk1x SLICE_X5Y33 FDPE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_10398_i/prst_with_sens_mrst_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y33 FDPE (Prop_fdpe_C_Q) 0.269 6.352 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_10398_i/prst_with_sens_mrst_reg[0]/Q net (fo=120, routed) 3.059 9.410 sensors393_i/sensor_channel_block[0].sensor_channel_i/pulse_cross_clock_eof_mclk_i/Q[0] SLICE_X47Y80 FDCE f sensors393_i/sensor_channel_block[0].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/CLR ------------------------------------------------------------------- ------------------- (clock pclk rise edge) 4.630 4.630 r Y12 0.000 4.630 r ffclk0p (IN) net (fo=0) 0.000 4.630 clocks393_i/ibufds_ibufgds0_i/ffclk0p Y12 IBUFDS (Prop_ibufds_I_O) 0.827 5.456 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O net (fo=2, routed) 1.170 6.626 clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.083 6.709 r clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 1.911 8.620 clocks393_i/dual_clock_pclk_i/clk1x_pre BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.113 8.733 r clocks393_i/dual_clock_pclk_i/clk1x_i/O net (fo=4841, routed) 1.273 10.006 sensors393_i/sensor_channel_block[0].sensor_channel_i/pulse_cross_clock_eof_mclk_i/clk1x SLICE_X47Y80 FDCE r sensors393_i/sensor_channel_block[0].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/C clock pessimism 0.282 10.288 clock uncertainty -0.115 10.174 SLICE_X47Y80 FDCE (Recov_fdce_C_CLR) -0.255 9.919 sensors393_i/sensor_channel_block[0].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg ------------------------------------------------------------------- required time 9.919 arrival time -9.410 ------------------------------------------------------------------- slack 0.508 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.356ns (arrival time - required time) Source: sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C (rising edge-triggered cell FDRE clocked by pclk {rise@0.000ns fall@2.315ns period=4.630ns}) Destination: sensors393_i/sensor_channel_block[3].sensor_membuf_i/page_written_i/in_reg_reg/CLR (removal check against rising-edge clock pclk {rise@0.000ns fall@2.315ns period=4.630ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (pclk rise@0.000ns - pclk rise@0.000ns) Data Path Delay: 0.263ns (logic 0.107ns (40.668%) route 0.156ns (59.332%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.745ns Source Clock Delay (SCD): 2.342ns Clock Pessimism Removal (CPR): 0.389ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock pclk rise edge) 0.000 0.000 r Y12 0.000 0.000 r ffclk0p (IN) net (fo=0) 0.000 0.000 clocks393_i/ibufds_ibufgds0_i/ffclk0p Y12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O net (fo=2, routed) 0.503 0.949 clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.050 0.999 r clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 0.771 1.770 clocks393_i/dual_clock_pclk_i/clk1x_pre BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.026 1.796 r clocks393_i/dual_clock_pclk_i/clk1x_i/O net (fo=4841, routed) 0.546 2.342 sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/CLK SLICE_X46Y95 FDRE r sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y95 FDRE (Prop_fdre_C_Q) 0.107 2.449 f sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q net (fo=100, routed) 0.156 2.605 sensors393_i/sensor_channel_block[3].sensor_membuf_i/page_written_i/rst[0] SLICE_X47Y94 FDCE f sensors393_i/sensor_channel_block[3].sensor_membuf_i/page_written_i/in_reg_reg/CLR ------------------------------------------------------------------- ------------------- (clock pclk rise edge) 0.000 0.000 r Y12 0.000 0.000 r ffclk0p (IN) net (fo=0) 0.000 0.000 clocks393_i/ibufds_ibufgds0_i/ffclk0p Y12 IBUFDS (Prop_ibufds_I_O) 0.521 0.521 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O net (fo=2, routed) 0.554 1.075 clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.053 1.128 r clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 net (fo=1, routed) 0.840 1.968 clocks393_i/dual_clock_pclk_i/clk1x_pre BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.030 1.998 r clocks393_i/dual_clock_pclk_i/clk1x_i/O net (fo=4841, routed) 0.747 2.745 sensors393_i/sensor_channel_block[3].sensor_membuf_i/page_written_i/clk1x SLICE_X47Y94 FDCE r sensors393_i/sensor_channel_block[3].sensor_membuf_i/page_written_i/in_reg_reg/C clock pessimism -0.389 2.356 SLICE_X47Y94 FDCE (Remov_fdce_C_CLR) -0.107 2.249 sensors393_i/sensor_channel_block[3].sensor_membuf_i/page_written_i/in_reg_reg ------------------------------------------------------------------- required time -2.249 arrival time 2.605 ------------------------------------------------------------------- slack 0.356 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sclk To Clock: sclk Setup : 0 Failing Endpoints, Worst Slack 5.006ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.288ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.006ns (required time - arrival time) Source: sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C (rising edge-triggered cell FDRE clocked by sclk {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: timing393_i/camsync393_i/i_ts_stb_mclk3/in_reg_reg/CLR (recovery check against rising-edge clock sclk {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (sclk rise@10.000ns - sclk rise@0.000ns) Data Path Delay: 4.310ns (logic 0.322ns (7.471%) route 3.988ns (92.529%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.354ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.459ns = ( 14.459 - 10.000 ) Source Clock Delay (SCD): 5.059ns Clock Pessimism Removal (CPR): 0.246ns Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.133ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.602 1.602 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 1.690 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 net (fo=1, routed) 1.621 3.311 clocks393_i/sync_clk_i/sync_clk_pre BUFGCTRL_X0Y22 BUFG (Prop_bufg_I_O) 0.120 3.431 r clocks393_i/sync_clk_i/clk1x_i/O net (fo=1347, routed) 1.628 5.059 sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/camsync_clk SLICE_X101Y164 FDRE r sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y164 FDRE (Prop_fdre_C_Q) 0.269 5.328 f sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q net (fo=2, routed) 0.582 5.910 sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/rst[0] SLICE_X101Y168 LUT2 (Prop_lut2_I0_O) 0.053 5.963 f sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/in_reg_i_1__92/O net (fo=13, routed) 3.406 9.369 timing393_i/camsync393_i/i_ts_stb_mclk3/eprst SLICE_X71Y130 FDCE f timing393_i/camsync393_i/i_ts_stb_mclk3/in_reg_reg/CLR ------------------------------------------------------------------- ------------------- (clock sclk rise edge) 10.000 10.000 r BUFGCTRL_X0Y23 BUFG 0.000 10.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.461 11.461 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.083 11.544 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 net (fo=1, routed) 1.538 13.082 clocks393_i/sync_clk_i/sync_clk_pre BUFGCTRL_X0Y22 BUFG (Prop_bufg_I_O) 0.113 13.195 r clocks393_i/sync_clk_i/clk1x_i/O net (fo=1347, routed) 1.264 14.459 timing393_i/camsync393_i/i_ts_stb_mclk3/camsync_clk SLICE_X71Y130 FDCE r timing393_i/camsync393_i/i_ts_stb_mclk3/in_reg_reg/C clock pessimism 0.246 14.705 clock uncertainty -0.075 14.630 SLICE_X71Y130 FDCE (Recov_fdce_C_CLR) -0.255 14.375 timing393_i/camsync393_i/i_ts_stb_mclk3/in_reg_reg ------------------------------------------------------------------- required time 14.375 arrival time -9.369 ------------------------------------------------------------------- slack 5.006 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.288ns (arrival time - required time) Source: sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C (rising edge-triggered cell FDRE clocked by sclk {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/CLR (removal check against rising-edge clock sclk {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sclk rise@0.000ns - sclk rise@0.000ns) Data Path Delay: 0.213ns (logic 0.107ns (50.340%) route 0.106ns (49.660%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.359ns Source Clock Delay (SCD): 1.847ns Clock Pessimism Removal (CPR): 0.501ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.586 0.586 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.636 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 net (fo=1, routed) 0.577 1.213 clocks393_i/sync_clk_i/sync_clk_pre BUFGCTRL_X0Y22 BUFG (Prop_bufg_I_O) 0.026 1.239 r clocks393_i/sync_clk_i/clk1x_i/O net (fo=1347, routed) 0.608 1.847 sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/camsync_clk SLICE_X84Y170 FDRE r sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y170 FDRE (Prop_fdre_C_Q) 0.107 1.954 f sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q net (fo=3, routed) 0.106 2.060 timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/rst[0] SLICE_X84Y171 FDCE f timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/CLR ------------------------------------------------------------------- ------------------- (clock sclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.803 0.803 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.053 0.856 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 net (fo=1, routed) 0.643 1.499 clocks393_i/sync_clk_i/sync_clk_pre BUFGCTRL_X0Y22 BUFG (Prop_bufg_I_O) 0.030 1.529 r clocks393_i/sync_clk_i/clk1x_i/O net (fo=1347, routed) 0.830 2.359 timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/camsync_clk SLICE_X84Y171 FDCE r timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/C clock pessimism -0.501 1.858 SLICE_X84Y171 FDCE (Remov_fdce_C_CLR) -0.086 1.772 timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg ------------------------------------------------------------------- required time -1.772 arrival time 2.060 ------------------------------------------------------------------- slack 0.288 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: usrclk2 To Clock: usrclk2 Setup : 0 Failing Endpoints, Worst Slack 5.183ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.984ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.183ns (required time - arrival time) Source: sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/C (rising edge-triggered cell FDCE clocked by usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns}) Destination: sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg/CLR (recovery check against rising-edge clock usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.333ns (usrclk2 rise@13.333ns - usrclk2 rise@0.000ns) Data Path Delay: 7.537ns (logic 0.322ns (4.272%) route 7.215ns (95.728%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.322ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.917ns = ( 16.250 - 13.333 ) Source Clock Delay (SCD): 3.509ns Clock Pessimism Removal (CPR): 0.270ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock usrclk2 rise edge) 0.000 0.000 r SLICE_X61Y50 FDRE 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q net (fo=2, routed) 1.794 1.794 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r BUFGCTRL_X0Y5 BUFG (Prop_bufg_I_O) 0.120 1.914 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O net (fo=2023, routed) 1.595 3.509 sata_top/ahci_sata_layers_i/phy/rxdata_reg[0]__0 SLICE_X67Y49 FDCE r sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y49 FDCE (Prop_fdce_C_Q) 0.269 3.778 r sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/Q net (fo=8, routed) 0.471 4.249 sata_top/ahci_sata_layers_i/phy/sata_reset_done SLICE_X67Y49 LUT3 (Prop_lut3_I2_O) 0.053 4.302 f sata_top/ahci_sata_layers_i/phy/was_rst_i_1/O net (fo=278, routed) 6.745 11.047 sata_top/ahci_sata_layers_i/dbg_was_link5_i/sata_reset_done_r_reg[0] SLICE_X43Y149 FDCE f sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg/CLR ------------------------------------------------------------------- ------------------- (clock usrclk2 rise edge) 13.333 13.333 r SLICE_X61Y50 FDRE 0.000 13.333 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q net (fo=2, routed) 1.531 14.864 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r BUFGCTRL_X0Y5 BUFG (Prop_bufg_I_O) 0.113 14.977 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O net (fo=2023, routed) 1.273 16.250 sata_top/ahci_sata_layers_i/dbg_was_link5_i/usrclk2_r_reg SLICE_X43Y149 FDCE r sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg/C clock pessimism 0.270 16.520 clock uncertainty -0.035 16.485 SLICE_X43Y149 FDCE (Recov_fdce_C_CLR) -0.255 16.230 sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg ------------------------------------------------------------------- required time 16.230 arrival time -11.047 ------------------------------------------------------------------- slack 5.183 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.984ns (arrival time - required time) Source: sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/C (rising edge-triggered cell FDRE clocked by usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns}) Destination: sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/CLR (removal check against rising-edge clock usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (usrclk2 rise@0.000ns - usrclk2 rise@0.000ns) Data Path Delay: 0.972ns (logic 0.128ns (13.169%) route 0.844ns (86.831%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.733ns Source Clock Delay (SCD): 1.378ns Clock Pessimism Removal (CPR): 0.317ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock usrclk2 rise edge) 0.000 0.000 r SLICE_X61Y50 FDRE 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q net (fo=2, routed) 0.828 0.828 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r BUFGCTRL_X0Y5 BUFG (Prop_bufg_I_O) 0.026 0.854 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O net (fo=2023, routed) 0.524 1.378 sata_top/ahci_top_i/ahci_dma_i/usrclk2_r_reg SLICE_X41Y120 FDRE r sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y120 FDRE (Prop_fdre_C_Q) 0.100 1.478 f sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/Q net (fo=18, routed) 0.467 1.945 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/abort_busy_mclk_reg SLICE_X28Y117 LUT2 (Prop_lut2_I0_O) 0.028 1.973 f sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/dout_vld_r[1]_i_1/O net (fo=15, routed) 0.377 2.350 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/abort_busy_mclk_reg SLICE_X34Y114 FDCE f sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/CLR ------------------------------------------------------------------- ------------------- (clock usrclk2 rise edge) 0.000 0.000 r SLICE_X61Y50 FDRE 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q net (fo=2, routed) 0.968 0.968 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r BUFGCTRL_X0Y5 BUFG (Prop_bufg_I_O) 0.030 0.998 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O net (fo=2023, routed) 0.735 1.733 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/usrclk2_r_reg SLICE_X34Y114 FDCE r sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/C clock pessimism -0.317 1.416 SLICE_X34Y114 FDCE (Remov_fdce_C_CLR) -0.050 1.366 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg ------------------------------------------------------------------- required time -1.366 arrival time 2.350 ------------------------------------------------------------------- slack 0.984 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: xclk To Clock: xclk Setup : 0 Failing Endpoints, Worst Slack 0.650ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.388ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.650ns (required time - arrival time) Source: sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C (rising edge-triggered cell FDRE clocked by xclk {rise@0.000ns fall@2.083ns period=4.167ns}) Destination: compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_frame_sync_i/last_mb_started_i/in_reg_reg/CLR (recovery check against rising-edge clock xclk {rise@0.000ns fall@2.083ns period=4.167ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 4.167ns (xclk rise@4.167ns - xclk rise@0.000ns) Data Path Delay: 3.286ns (logic 0.308ns (9.373%) route 2.978ns (90.627%)) Logic Levels: 0 Clock Path Skew: 0.092ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.672ns = ( 8.839 - 4.167 ) Source Clock Delay (SCD): 4.826ns Clock Pessimism Removal (CPR): 0.246ns Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.114ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock xclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.602 1.602 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.088 1.690 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 net (fo=1, routed) 1.621 3.311 clocks393_i/xclk_i/xclk_pre BUFGCTRL_X0Y21 BUFG (Prop_bufg_I_O) 0.120 3.431 r clocks393_i/xclk_i/clk1x_i/O net (fo=13477, routed) 1.395 4.826 sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/pwrdwn_clk_reg[0] SLICE_X62Y61 FDRE r sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y61 FDRE (Prop_fdre_C_Q) 0.308 5.134 f sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q net (fo=116, routed) 2.978 8.112 compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_frame_sync_i/last_mb_started_i/Q[0] SLICE_X43Y38 FDCE f compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_frame_sync_i/last_mb_started_i/in_reg_reg/CLR ------------------------------------------------------------------- ------------------- (clock xclk rise edge) 4.167 4.167 r BUFGCTRL_X0Y23 BUFG 0.000 4.167 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 1.461 5.628 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.083 5.711 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 net (fo=1, routed) 1.538 7.249 clocks393_i/xclk_i/xclk_pre BUFGCTRL_X0Y21 BUFG (Prop_bufg_I_O) 0.113 7.362 r clocks393_i/xclk_i/clk1x_i/O net (fo=13477, routed) 1.477 8.839 compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_frame_sync_i/last_mb_started_i/xclk SLICE_X43Y38 FDCE r compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_frame_sync_i/last_mb_started_i/in_reg_reg/C clock pessimism 0.246 9.085 clock uncertainty -0.067 9.017 SLICE_X43Y38 FDCE (Recov_fdce_C_CLR) -0.255 8.762 compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_frame_sync_i/last_mb_started_i/in_reg_reg ------------------------------------------------------------------- required time 8.762 arrival time -8.112 ------------------------------------------------------------------- slack 0.650 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.388ns (arrival time - required time) Source: sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C (rising edge-triggered cell FDRE clocked by xclk {rise@0.000ns fall@2.083ns period=4.167ns}) Destination: compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/in_reg_reg/CLR (removal check against rising-edge clock xclk {rise@0.000ns fall@2.083ns period=4.167ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (xclk rise@0.000ns - xclk rise@0.000ns) Data Path Delay: 0.334ns (logic 0.118ns (35.371%) route 0.216ns (64.629%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.274ns Source Clock Delay (SCD): 1.782ns Clock Pessimism Removal (CPR): 0.477ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock xclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.586 0.586 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.050 0.636 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 net (fo=1, routed) 0.577 1.213 clocks393_i/xclk_i/xclk_pre BUFGCTRL_X0Y21 BUFG (Prop_bufg_I_O) 0.026 1.239 r clocks393_i/xclk_i/clk1x_i/O net (fo=13477, routed) 0.543 1.782 sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/pwrdwn_clk_reg[0] SLICE_X62Y61 FDRE r sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y61 FDRE (Prop_fdre_C_Q) 0.118 1.900 f sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q net (fo=116, routed) 0.216 2.116 compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/regs_reg[1][0] SLICE_X65Y59 FDCE f compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/in_reg_reg/CLR ------------------------------------------------------------------- ------------------- (clock xclk rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O net (fo=738, routed) 0.803 0.803 clocks393_i/pll_base_i/axi_clk PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.053 0.856 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 net (fo=1, routed) 0.643 1.499 clocks393_i/xclk_i/xclk_pre BUFGCTRL_X0Y21 BUFG (Prop_bufg_I_O) 0.030 1.529 r clocks393_i/xclk_i/clk1x_i/O net (fo=13477, routed) 0.745 2.274 compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/xclk SLICE_X65Y59 FDCE r compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/in_reg_reg/C clock pessimism -0.477 1.797 SLICE_X65Y59 FDCE (Remov_fdce_C_CLR) -0.069 1.728 compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/in_reg_reg ------------------------------------------------------------------- required time -1.728 arrival time 2.116 ------------------------------------------------------------------- slack 0.388