Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date         : Mon May 20 11:20:49 2019
| Host         : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command      : report_timing_summary -file vivado_build/x393.timing_summary_impl
| Design       : x393
| Device       : 7z030-fbg484
| Speed File   : -1  PRODUCTION 1.11 2014-09-11
------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  false

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
 There are 16 register/latch pins with no clock driven by root clock pin: DQSL (HIGH)

 There are 16 register/latch pins with no clock driven by root clock pin: DQSU (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: ffclk1p (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: memclk (HIGH)


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 20 pins that are not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
 There are 90 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
 There are 99 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.080        0.000                      0               149809        0.036        0.000                      0               149809        0.264        0.000                       0                 60885  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock           Waveform(ns)         Period(ns)      Frequency(MHz)
-----           ------------         ----------      --------------
axi_aclk        {0.000 10.000}       20.000          50.000          
  axihp_clk     {0.000 3.333}        6.667           150.000         
  clk_fb        {0.000 10.000}       20.000          50.000          
  ddr3_clk      {0.000 1.250}        2.500           400.000         
  ddr3_clk_div  {0.000 2.500}        5.000           200.000         
  ddr3_clk_ref  {0.000 2.500}        5.000           200.000         
  ddr3_mclk     {1.250 3.750}        5.000           200.000         
  ddr3_sdclk    {0.000 1.250}        2.500           400.000         
  multi_clkfb   {0.000 10.000}       20.000          50.000          
  sclk          {0.000 5.000}        10.000          100.000         
  xclk          {0.000 2.083}        4.167           240.000         
ffclk0          {0.000 20.833}       41.667          24.000          
  clkfb         {0.000 20.833}       41.667          24.000          
  pclk          {0.000 50.000}       100.001         10.000          
gtrefclk        {0.000 3.333}        6.666           150.015         
rx_clk          {0.000 3.333}        6.666           150.015         
txoutclk        {0.000 3.333}        6.666           150.015         
usrclk2         {0.000 6.666}        13.333          75.002          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
axi_aclk             13.812        0.000                      0                 2685        0.057        0.000                      0                 2685        7.000        0.000                       0                   737  
  axihp_clk           0.742        0.000                      0                10218        0.044        0.000                      0                10218        0.267        0.000                       0                  3863  
  clk_fb                                                                                                                                                         18.751        0.000                       0                     2  
  ddr3_clk                                                                                                                                                        0.279        0.000                       0                    45  
  ddr3_clk_div        0.181        0.000                      0                 2158        0.134        0.000                      0                 2158        1.389        0.000                       0                   755  
  ddr3_clk_ref                                                                                                                                                    0.264        0.000                       0                     3  
  ddr3_mclk           0.151        0.000                      0                81401        0.043        0.000                      0                81401        1.590        0.000                       0                 32799  
  ddr3_sdclk                                                                                                                                                      1.092        0.000                       0                     3  
  multi_clkfb                                                                                                                                                    18.751        0.000                       0                     2  
  sclk                4.271        0.000                      0                 2742        0.044        0.000                      0                 2742        4.090        0.000                       0                  1349  
  xclk                0.202        0.000                      0                33101        0.038        0.000                      0                33101        0.875        0.000                       0                 13490  
ffclk0               40.972        0.000                      0                    1        0.211        0.000                      0                    1       10.833        0.000                       0                     3  
  clkfb                                                                                                                                                          10.966        0.000                       0                     2  
  pclk               45.389        0.000                      0                10880        0.036        0.000                      0                10880       49.090        0.000                       0                  5316  
gtrefclk              3.795        0.000                      0                   45        0.269        0.000                      0                   45        2.553        0.000                       0                    25  
rx_clk                0.588        0.000                      0                  916        0.040        0.000                      0                  916        2.423        0.000                       0                   329  
txoutclk              2.159        0.000                      0                  232        0.159        0.000                      0                  232        2.666        0.000                       0                   138  
usrclk2               3.117        0.000                      0                 4579        0.053        0.000                      0                 4579        5.756        0.000                       0                  2024  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
ddr3_clk_div  ddr3_clk            0.319        0.000                      0                   23        0.215        0.000                      0                   23  
ddr3_mclk     ddr3_clk_div        0.080        0.000                      0                  146        1.433        0.000                      0                  146  
ddr3_clk_div  ddr3_mclk           3.006        0.000                      0                   76        0.162        0.000                      0                   76  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group         From Clock         To Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------         ----------         --------               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**  axihp_clk          axihp_clk                1.159        0.000                      0                   23        0.727        0.000                      0                   23  
**async_default**  ddr3_mclk          ddr3_mclk                0.741        0.000                      0                  469        0.274        0.000                      0                  469  
**async_default**  pclk               pclk                    89.858        0.000                      0                   20        0.318        0.000                      0                   20  
**async_default**  sclk               sclk                     6.877        0.000                      0                   16        0.201        0.000                      0                   16  
**async_default**  usrclk2            usrclk2                  3.039        0.000                      0                    7        0.785        0.000                      0                    7  
**async_default**  xclk               xclk                     0.821        0.000                      0                   72        0.388        0.000                      0                   72  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  axi_aclk
  To Clock:  axi_aclk

Setup :            0  Failing Endpoints,  Worst Slack       13.812ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.057ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        7.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             13.812ns  (required time - arrival time)
  Source:                 mcntrl393_i/select_buf2rd_reg/C
                            (rising edge-triggered cell FDRE clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            ps7_i/MAXIGP0RDATA[23]
                            (rising edge-triggered cell PS7 clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             axi_aclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (axi_aclk rise@20.000ns - axi_aclk rise@0.000ns)
  Data Path Delay:        5.640ns  (logic 0.467ns (8.280%)  route 5.173ns (91.720%))
  Logic Levels:           3  (LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        0.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.336ns = ( 21.336 - 20.000 ) 
    Source Clock Delay      (SCD):    1.388ns
    Clock Pessimism Removal (CPR):    0.089ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.388     1.388    mcntrl393_i/axi_clk
    SLICE_X48Y143        FDRE                                         r  mcntrl393_i/select_buf2rd_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y143        FDRE (Prop_fdre_C_Q)         0.308     1.696 r  mcntrl393_i/select_buf2rd_reg/Q
                         net (fo=34, routed)          2.246     3.942    cmd_readback_i/lopt_1
    SLICE_X55Y116        LUT4 (Prop_lut4_I1_O)        0.053     3.995 r  cmd_readback_i/xlnx_opt_LUT_ps7_i_i_38/O
                         net (fo=1, routed)           0.457     4.452    cmd_readback_i/xlnx_opt_MAXIGP0RDATA[23]_1
    SLICE_X55Y116        LUT5 (Prop_lut5_I4_O)        0.053     4.505 r  cmd_readback_i/xlnx_opt_LUT_ps7_i_i_38_1/O
                         net (fo=1, routed)           1.368     5.873    cmd_readback_i/xlnx_opt_MAXIGP0RDATA[23]
    SLICE_X55Y147        LUT6 (Prop_lut6_I5_O)        0.053     5.926 r  cmd_readback_i/xlnx_opt_LUT_ps7_i_i_38_2/O
                         net (fo=1, routed)           1.102     7.028    axird_rdata[23]
    PS7_X0Y0             PS7                                          r  ps7_i/MAXIGP0RDATA[23]
  -------------------------------------------------------------------    -------------------

                         (clock axi_aclk rise edge)
                                                     20.000    20.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000    20.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.336    21.336    axi_aclk
    PS7_X0Y0             PS7                                          r  ps7_i/MAXIGP0ACLK
                         clock pessimism              0.089    21.425    
                         clock uncertainty           -0.035    21.390    
    PS7_X0Y0             PS7 (Setup_ps7_MAXIGP0ACLK_MAXIGP0RDATA[23])
                                                     -0.550    20.840    ps7_i
  -------------------------------------------------------------------
                         required time                         20.840    
                         arrival time                          -7.028    
  -------------------------------------------------------------------
                         slack                                 13.812    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.057ns  (arrival time - required time)
  Source:                 axibram_write_i/waddr_i/inreg_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            axibram_write_i/waddr_i/ram_reg_0_15_12_17/RAMC/I
                            (rising edge-triggered cell RAMD32 clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             axi_aclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (axi_aclk rise@0.000ns - axi_aclk rise@0.000ns)
  Data Path Delay:        0.200ns  (logic 0.100ns (50.053%)  route 0.100ns (49.947%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.838ns
    Source Clock Delay      (SCD):    0.613ns
    Clock Pessimism Removal (CPR):    0.211ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.613     0.613    axibram_write_i/waddr_i/axi_clk
    SLICE_X37Y151        FDRE                                         r  axibram_write_i/waddr_i/inreg_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y151        FDRE (Prop_fdre_C_Q)         0.100     0.713 r  axibram_write_i/waddr_i/inreg_reg[16]/Q
                         net (fo=1, routed)           0.100     0.813    axibram_write_i/waddr_i/ram_reg_0_15_12_17/DIC0
    SLICE_X38Y151        RAMD32                                       r  axibram_write_i/waddr_i/ram_reg_0_15_12_17/RAMC/I
  -------------------------------------------------------------------    -------------------

                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.838     0.838    axibram_write_i/waddr_i/ram_reg_0_15_12_17/WCLK
    SLICE_X38Y151        RAMD32                                       r  axibram_write_i/waddr_i/ram_reg_0_15_12_17/RAMC/CLK
                         clock pessimism             -0.211     0.627    
    SLICE_X38Y151        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.129     0.756    axibram_write_i/waddr_i/ram_reg_0_15_12_17/RAMC
  -------------------------------------------------------------------
                         required time                         -0.756    
                         arrival time                           0.813    
  -------------------------------------------------------------------
                         slack                                  0.057    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         axi_aclk
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { clocks393_i/bufg_axi_aclk_i/O }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.183         20.000      17.817     RAMB36_X3Y31    cmd_readback_i/ram_reg_0/CLKBWRCLK
Max Period        n/a     PLLE2_ADV/CLKIN1    n/a            52.633        20.000      32.633     PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1    n/a            3.000         10.000      7.000      PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1    n/a            3.000         10.000      7.000      PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  axihp_clk
  To Clock:  axihp_clk

Setup :            0  Failing Endpoints,  Worst Slack        0.742ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.044ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.267ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.742ns  (required time - arrival time)
  Source:                 sata_top/ahci_top_i/axi_ahci_regs_i/drp_read_data_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            sata_top/ahci_top_i/axi_ahci_regs_i/bram_rdata_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             axihp_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (axihp_clk rise@6.667ns - axihp_clk rise@0.000ns)
  Data Path Delay:        5.549ns  (logic 0.361ns (6.505%)  route 5.188ns (93.495%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.377ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.053ns = ( 11.720 - 6.667 ) 
    Source Clock Delay      (SCD):    5.675ns
    Clock Pessimism Removal (CPR):    0.245ns
  Clock Uncertainty:      0.071ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.124ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     3.904    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        1.651     5.675    sata_top/ahci_top_i/axi_ahci_regs_i/hclk
    SLICE_X108Y38        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/drp_read_data_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y38        FDRE (Prop_fdre_C_Q)         0.308     5.983 r  sata_top/ahci_top_i/axi_ahci_regs_i/drp_read_data_reg[7]/Q
                         net (fo=1, routed)           5.188    11.171    sata_top/ahci_top_i/axi_ahci_regs_i/ahci_regs_i/drp_read_data_reg[15][7]
    SLICE_X34Y148        LUT5 (Prop_lut5_I0_O)        0.053    11.224 r  sata_top/ahci_top_i/axi_ahci_regs_i/ahci_regs_i/bram_rdata_r[7]_i_1/O
                         net (fo=1, routed)           0.000    11.224    sata_top/ahci_top_i/axi_ahci_regs_i/ahci_regs_i_n_73
    SLICE_X34Y148        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/bram_rdata_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      6.667     6.667 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     6.667 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     8.339    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083     8.422 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    10.333    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.113    10.446 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        1.274    11.720    sata_top/ahci_top_i/axi_ahci_regs_i/hclk
    SLICE_X34Y148        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/bram_rdata_r_reg[7]/C
                         clock pessimism              0.245    11.965    
                         clock uncertainty           -0.071    11.893    
    SLICE_X34Y148        FDRE (Setup_fdre_C_D)        0.073    11.966    sata_top/ahci_top_i/axi_ahci_regs_i/bram_rdata_r_reg[7]
  -------------------------------------------------------------------
                         required time                         11.966    
                         arrival time                         -11.224    
  -------------------------------------------------------------------
                         slack                                  0.742    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.044ns  (arrival time - required time)
  Source:                 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/inreg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/ram_reg_0_15_0_5/RAMC/I
                            (rising edge-triggered cell RAMD32 clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             axihp_clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (axihp_clk rise@0.000ns - axihp_clk rise@0.000ns)
  Data Path Delay:        0.146ns  (logic 0.091ns (62.374%)  route 0.055ns (37.626%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.651ns
    Source Clock Delay      (SCD):    2.118ns
    Clock Pessimism Removal (CPR):    0.522ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.478    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        0.614     2.118    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/hclk
    SLICE_X37Y155        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/inreg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y155        FDRE (Prop_fdre_C_Q)         0.091     2.209 r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/inreg_reg[4]/Q
                         net (fo=1, routed)           0.055     2.264    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/ram_reg_0_15_0_5/DIC0
    SLICE_X36Y155        RAMD32                                       r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/ram_reg_0_15_0_5/RAMC/I
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.782    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        0.839     2.651    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/ram_reg_0_15_0_5/WCLK
    SLICE_X36Y155        RAMD32                                       r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/ram_reg_0_15_0_5/RAMC/CLK
                         clock pessimism             -0.522     2.129    
    SLICE_X36Y155        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.091     2.220    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/ram_reg_0_15_0_5/RAMC
  -------------------------------------------------------------------
                         required time                         -2.220    
                         arrival time                           2.264    
  -------------------------------------------------------------------
                         slack                                  0.044    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         axihp_clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.667
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 }

Check Type        Corner  Lib Pin               Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/DRPCLK  n/a            6.400         6.667       0.267      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/DRPCLK
Max Period        n/a     PLLE2_ADV/CLKOUT0     n/a            160.000       6.667       153.333    PLLE2_ADV_X0Y0      clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
Low Pulse Width   Slow    RAMD32/CLK            n/a            0.910         3.333       2.423      SLICE_X14Y83        compressor393_i/cmprs_afi0_mux_i/cmprs_afi_mux_ptr_i/ptr_ram_reg_0_7_15_15/DP/CLK
High Pulse Width  Slow    RAMD32/CLK            n/a            0.910         3.333       2.423      SLICE_X32Y123       sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_ram_reg_0_7_54_59/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_fb
  To Clock:  clk_fb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       18.751ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_fb
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         20.000      18.751     MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       20.000      80.000     MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk
  To Clock:  ddr3_clk

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.279ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk
Waveform(ns):       { 0.000 1.250 }
Period(ns):         2.500
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFR/I              n/a            2.221         2.500       0.279      BUFR_X1Y8        mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/I
Max Period  n/a     MMCME2_ADV/CLKOUT1  n/a            213.360       2.500       210.860    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_div
  To Clock:  ddr3_clk_div

Setup :            0  Failing Endpoints,  Worst Slack        0.181ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.134ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.389ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.181ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/C
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/oserdes_i/RST
                            (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (ddr3_clk_div rise@5.000ns - ddr3_clk_div rise@0.000ns)
  Data Path Delay:        4.074ns  (logic 0.269ns (6.604%)  route 3.805ns (93.396%))
  Logic Levels:           0  
  Clock Path Skew:        0.085ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.639ns = ( 8.639 - 5.000 ) 
    Source Clock Delay      (SCD):    3.810ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     1.575    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.088     1.663 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.106     2.769    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.377     3.146 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.664     3.810    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/CLK
    SLICE_X116Y102       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X116Y102       FDRE (Prop_fdre_C_Q)         0.269     4.079 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/Q
                         net (fo=786, routed)         3.805     7.884    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/tin
    OLOGIC_X1Y138        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/oserdes_i/RST
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      5.000     5.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     5.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     6.437    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.083     6.520 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.016     7.536    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.370     7.906 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.733     8.639    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/psincdec_reg
    OLOGIC_X1Y138        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/oserdes_i/CLKDIV
                         clock pessimism              0.256     8.895    
                         clock uncertainty           -0.085     8.810    
    OLOGIC_X1Y138        OSERDESE2 (Setup_oserdese2_CLKDIV_RST)
                                                     -0.745     8.065    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/oserdes_i
  -------------------------------------------------------------------
                         required time                          8.065    
                         arrival time                          -7.884    
  -------------------------------------------------------------------
                         slack                                  0.181    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.134ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dly_data_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_clk_div rise@0.000ns - ddr3_clk_div rise@0.000ns)
  Data Path Delay:        0.205ns  (logic 0.128ns (62.372%)  route 0.077ns (37.628%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.740ns
    Source Clock Delay      (SCD):    1.424ns
    Clock Pessimism Removal (CPR):    0.305ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     0.580    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.050     0.630 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.433     1.063    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.090     1.153 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.271     1.424    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/psincdec_reg_0
    SLICE_X116Y113       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dly_data_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X116Y113       FDRE (Prop_fdre_C_Q)         0.100     1.524 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dly_data_r_reg[0]/Q
                         net (fo=19, routed)          0.077     1.601    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/dly_data_r_reg[7][0]
    SLICE_X117Y113       LUT3 (Prop_lut3_I0_O)        0.028     1.629 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre[0]_i_1__3/O
                         net (fo=1, routed)           0.000     1.629    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre[0]_i_1__3_n_0
    SLICE_X117Y113       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     0.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.053     0.849 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.490     1.339    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.093     1.432 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.308     1.740    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/psincdec_reg
    SLICE_X117Y113       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre_reg[0]/C
                         clock pessimism             -0.305     1.435    
    SLICE_X117Y113       FDRE (Hold_fdre_C_D)         0.060     1.495    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.495    
                         arrival time                           1.629    
  -------------------------------------------------------------------
                         slack                                  0.134    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk_div
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     BUFR/I              n/a            2.221         5.000       2.779      BUFR_X1Y9        mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/I
Max Period        n/a     MMCME2_ADV/CLKOUT2  n/a            213.360       5.000       208.360    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
Low Pulse Width   Slow    MMCME2_ADV/PSCLK    n/a            1.111         2.500       1.389      MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK
High Pulse Width  Slow    MMCME2_ADV/PSCLK    n/a            1.111         2.500       1.389      MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_ref
  To Clock:  ddr3_clk_ref

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.264ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk_ref
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT5 }

Check Type  Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     IDELAYCTRL/REFCLK  n/a            3.225         5.000       1.775      IDELAYCTRL_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK
Max Period  n/a     IDELAYCTRL/REFCLK  n/a            5.264         5.000       0.264      IDELAYCTRL_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_mclk
  To Clock:  ddr3_mclk

Setup :            0  Failing Endpoints,  Worst Slack        0.151ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.043ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.590ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.151ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_early_master_reg_rep/C
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            event_logger_i/status_generate_i/status_generate_only_i/data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             ddr3_mclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (ddr3_mclk rise@6.250ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        4.651ns  (logic 0.435ns (9.352%)  route 4.216ns (90.648%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.147ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.424ns = ( 10.674 - 6.250 ) 
    Source Clock Delay      (SCD):    4.805ns = ( 6.055 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.234ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32797, routed)       1.394     6.055    sync_resets_i/mclk
    SLICE_X54Y96         FDRE                                         r  sync_resets_i/rst_early_master_reg_rep/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y96         FDRE (Prop_fdre_C_Q)         0.282     6.337 f  sync_resets_i/rst_early_master_reg_rep/Q
                         net (fo=1272, routed)        4.216    10.553    event_logger_i/status_generate_i/status_generate_only_i/rst_early_master_reg_rep
    SLICE_X57Y125        LUT5 (Prop_lut5_I2_O)        0.153    10.706 r  event_logger_i/status_generate_i/status_generate_only_i/data[1]_i_1__37/O
                         net (fo=1, routed)           0.000    10.706    event_logger_i/status_generate_i/status_generate_only_i/data_0[1]
    SLICE_X57Y125        FDRE                                         r  event_logger_i/status_generate_i/status_generate_only_i/data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      6.250     6.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     6.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     7.687    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.083     7.770 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.544     9.314    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.113     9.427 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32797, routed)       1.247    10.674    event_logger_i/status_generate_i/status_generate_only_i/mclk
    SLICE_X57Y125        FDRE                                         r  event_logger_i/status_generate_i/status_generate_only_i/data_reg[1]/C
                         clock pessimism              0.234    10.908    
                         clock uncertainty           -0.085    10.823    
    SLICE_X57Y125        FDRE (Setup_fdre_C_D)        0.035    10.858    event_logger_i/status_generate_i/status_generate_only_i/data_reg[1]
  -------------------------------------------------------------------
                         required time                         10.858    
                         arrival time                         -10.706    
  -------------------------------------------------------------------
                         slack                                  0.151    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.043ns  (arrival time - required time)
  Source:                 mcntrl393_test01_i/status_generate_chn2_i/status_generate_only_i/data_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            mcntrl393_test01_i/status_router4_i/status_router2_01_i/fifo_in1_i/ram_reg_0_15_6_8/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             ddr3_mclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_mclk rise@1.250ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        0.208ns  (logic 0.100ns (48.170%)  route 0.108ns (51.830%))
  Logic Levels:           0  
  Clock Path Skew:        0.034ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.246ns = ( 3.496 - 1.250 ) 
    Source Clock Delay      (SCD):    1.757ns = ( 3.007 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.455ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     1.830    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.050     1.880 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.559     2.439    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.465 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32797, routed)       0.542     3.007    mcntrl393_test01_i/status_generate_chn2_i/status_generate_only_i/mclk
    SLICE_X61Y88         FDRE                                         r  mcntrl393_test01_i/status_generate_chn2_i/status_generate_only_i/data_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y88         FDRE (Prop_fdre_C_Q)         0.100     3.107 r  mcntrl393_test01_i/status_generate_chn2_i/status_generate_only_i/data_reg[6]/Q
                         net (fo=1, routed)           0.108     3.215    mcntrl393_test01_i/status_router4_i/status_router2_01_i/fifo_in1_i/ram_reg_0_15_6_8/DIA0
    SLICE_X62Y89         RAMD32                                       r  mcntrl393_test01_i/status_router4_i/status_router2_01_i/fifo_in1_i/ram_reg_0_15_6_8/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     2.046    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.053     2.099 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.623     2.722    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.030     2.752 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32797, routed)       0.744     3.496    mcntrl393_test01_i/status_router4_i/status_router2_01_i/fifo_in1_i/ram_reg_0_15_6_8/WCLK
    SLICE_X62Y89         RAMD32                                       r  mcntrl393_test01_i/status_router4_i/status_router2_01_i/fifo_in1_i/ram_reg_0_15_6_8/RAMA/CLK
                         clock pessimism             -0.455     3.041    
    SLICE_X62Y89         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.131     3.172    mcntrl393_test01_i/status_router4_i/status_router2_01_i/fifo_in1_i/ram_reg_0_15_6_8/RAMA
  -------------------------------------------------------------------
                         required time                         -3.172    
                         arrival time                           3.215    
  -------------------------------------------------------------------
                         slack                                  0.043    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_mclk
Waveform(ns):       { 1.250 3.750 }
Period(ns):         5.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.495         5.000       2.505      RAMB36_X5Y33     sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/sens_hist_ram_snglclk_32_i/ramt_var_w_var_r_even_i/RAMB36E1_i/CLKBWRCLK
Max Period        n/a     MMCME2_ADV/CLKOUT3  n/a            213.360       5.000       208.360    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.910         2.500       1.590      SLICE_X46Y51     compressor393_i/status_router8_i/status_router4_0123_i/status_router2_23_i/fifo_in0_i/ram_reg_0_15_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.910         2.500       1.590      SLICE_X18Y68     sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_i2c_io_i/sensor_i2c_i/fifo_same_clock_i2c_rdata_i/ram_reg_0_15_6_7/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_sdclk
  To Clock:  ddr3_sdclk

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        1.092ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_sdclk
Waveform(ns):       { 0.000 1.250 }
Period(ns):         2.500
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0 }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFIO/I             n/a            1.408         2.500       1.092      BUFIO_X1Y9       mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/iclk_bufio_i/I
Max Period  n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       2.500       210.860    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0



---------------------------------------------------------------------------------------------------
From Clock:  multi_clkfb
  To Clock:  multi_clkfb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       18.751ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         multi_clkfb
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            1.249         20.000      18.751     PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT
Max Period  n/a     PLLE2_ADV/CLKFBIN   n/a            52.633        20.000      32.633     PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  sclk
  To Clock:  sclk

Setup :            0  Failing Endpoints,  Worst Slack        4.271ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.044ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        4.090ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.271ns  (required time - arrival time)
  Source:                 event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
                            (falling edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             sclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (sclk fall@5.000ns - sclk rise@0.000ns)
  Data Path Delay:        0.499ns  (logic 0.246ns (49.268%)  route 0.253ns (50.732%))
  Logic Levels:           0  
  Clock Path Skew:        -0.020ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.052ns = ( 10.052 - 5.000 ) 
    Source Clock Delay      (SCD):    5.415ns
    Clock Pessimism Removal (CPR):    0.343ns
  Clock Uncertainty:      0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.133ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           2.009     3.904    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        1.391     5.415    event_logger_i/i_imu_spi/CLK
    SLICE_X68Y140        FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y140        FDRE (Prop_fdre_C_Q)         0.246     5.661 r  event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/Q
                         net (fo=2, routed)           0.253     5.914    event_logger_i/i_imu_spi/sngl_wire_stb_reg_n_0_[0]
    SLICE_X69Y141        FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sclk fall edge)       5.000     5.000 f  
    BUFGCTRL_X0Y17       BUFG                         0.000     5.000 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     6.672    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.083     6.755 f  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.911     8.666    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.113     8.779 f  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        1.273    10.052    event_logger_i/i_imu_spi/CLK
    SLICE_X69Y141        FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/C  (IS_INVERTED)
                         clock pessimism              0.343    10.395    
                         clock uncertainty           -0.075    10.320    
    SLICE_X69Y141        FDRE (Setup_fdre_C_D)       -0.134    10.186    event_logger_i/i_imu_spi/sngl_wire_r_reg[1]
  -------------------------------------------------------------------
                         required time                         10.186    
                         arrival time                          -5.914    
  -------------------------------------------------------------------
                         slack                                  4.271    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.044ns  (arrival time - required time)
  Source:                 event_logger_i/i_imu_spi/miso_reg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            i_imu_spi/odbuf0_ram_reg_0_31_0_5/RAMC/I
                            (rising edge-triggered cell RAMD32 clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             sclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sclk rise@0.000ns - sclk rise@0.000ns)
  Data Path Delay:        0.146ns  (logic 0.091ns (62.374%)  route 0.055ns (37.626%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.541ns
    Source Clock Delay      (SCD):    2.028ns
    Clock Pessimism Removal (CPR):    0.502ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.771     1.478    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        0.524     2.028    event_logger_i/i_imu_spi/CLK
    SLICE_X59Y137        FDRE                                         r  event_logger_i/i_imu_spi/miso_reg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y137        FDRE (Prop_fdre_C_Q)         0.091     2.119 r  event_logger_i/i_imu_spi/miso_reg_reg[4]/Q
                         net (fo=2, routed)           0.055     2.174    i_imu_spi/odbuf0_ram_reg_0_31_0_5/DIC0
    SLICE_X58Y137        RAMD32                                       r  i_imu_spi/odbuf0_ram_reg_0_31_0_5/RAMC/I
  -------------------------------------------------------------------    -------------------

                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.840     1.782    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        0.729     2.541    i_imu_spi/odbuf0_ram_reg_0_31_0_5/WCLK
    SLICE_X58Y137        RAMD32                                       r  i_imu_spi/odbuf0_ram_reg_0_31_0_5/RAMC/CLK
                         clock pessimism             -0.502     2.039    
    SLICE_X58Y137        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.091     2.130    i_imu_spi/odbuf0_ram_reg_0_31_0_5/RAMC
  -------------------------------------------------------------------
                         required time                         -2.130    
                         arrival time                           2.174    
  -------------------------------------------------------------------
                         slack                                  0.044    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         sclk
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFG/I             n/a            1.600         10.000      8.400      BUFGCTRL_X0Y7   clocks393_i/sync_clk_i/clk1x_i/I
Max Period        n/a     PLLE2_ADV/CLKOUT3  n/a            160.000       10.000      150.000    PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
Low Pulse Width   Slow    RAMD32/CLK         n/a            0.910         5.000       4.090      SLICE_X54Y135   event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_6_11/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK         n/a            0.910         5.000       4.090      SLICE_X52Y142   event_logger_i/i_buf_xclk_mclk16/fifo_4x16_ram_reg_0_3_0_5/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  xclk
  To Clock:  xclk

Setup :            0  Failing Endpoints,  Worst Slack        0.202ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.038ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.875ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.202ns  (required time - arrival time)
  Source:                 compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/k1_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             xclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (xclk rise@4.167ns - xclk rise@0.000ns)
  Data Path Delay:        3.920ns  (logic 1.410ns (35.971%)  route 2.510ns (64.029%))
  Logic Levels:           7  (CARRY4=4 LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.249ns = ( 9.416 - 4.167 ) 
    Source Clock Delay      (SCD):    5.613ns
    Clock Pessimism Removal (CPR):    0.338ns
  Clock Uncertainty:      0.067ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.114ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           2.009     3.904    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13488, routed)       1.589     5.613    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/xclk
    SLICE_X47Y10         FDRE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/k1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y10         FDRE (Prop_fdre_C_Q)         0.269     5.882 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/k1_reg[1]/Q
                         net (fo=67, routed)          0.692     6.574    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[3]_0
    SLICE_X47Y13         LUT5 (Prop_lut5_I3_O)        0.053     6.627 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___114_i_7/O
                         net (fo=1, routed)           0.457     7.084    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___114_i_7_n_0
    SLICE_X45Y14         CARRY4 (Prop_carry4_DI[2]_CO[3])
                                                      0.239     7.323 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___114_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.323    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___114_i_2_n_0
    SLICE_X45Y15         CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.132     7.455 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___121_i_4/CO[2]
                         net (fo=2, routed)           0.453     7.908    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___121_i_4_n_1
    SLICE_X46Y16         LUT4 (Prop_lut4_I3_O)        0.161     8.069 f  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___121_i_2/O
                         net (fo=2, routed)           0.467     8.537    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[14]_3
    SLICE_X46Y16         LUT6 (Prop_lut6_I2_O)        0.053     8.590 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___124_i_1/O
                         net (fo=2, routed)           0.440     9.030    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[14]_2[0]
    SLICE_X47Y16         CARRY4 (Prop_carry4_DI[0]_CO[3])
                                                      0.324     9.354 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[14]_i_1/CO[3]
                         net (fo=1, routed)           0.000     9.354    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[14]_i_1_n_0
    SLICE_X47Y17         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.179     9.533 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]_i_1/CO[0]
                         net (fo=1, routed)           0.000     9.533    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/mm2[15]
    SLICE_X47Y17         FDRE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       4.167     4.167 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     4.167 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     5.839    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.083     5.922 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.911     7.833    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.113     7.946 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13488, routed)       1.470     9.416    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/xclk
    SLICE_X47Y17         FDRE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]/C
                         clock pessimism              0.338     9.754    
                         clock uncertainty           -0.067     9.686    
    SLICE_X47Y17         FDRE (Setup_fdre_C_D)        0.048     9.734    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]
  -------------------------------------------------------------------
                         required time                          9.734    
                         arrival time                          -9.533    
  -------------------------------------------------------------------
                         slack                                  0.202    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/inreg_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/ram_reg_0_15_6_11/RAMB/I
                            (rising edge-triggered cell RAMD32 clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             xclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (xclk rise@0.000ns - xclk rise@0.000ns)
  Data Path Delay:        0.145ns  (logic 0.091ns (62.668%)  route 0.054ns (37.332%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.664ns
    Source Clock Delay      (SCD):    2.136ns
    Clock Pessimism Removal (CPR):    0.517ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.771     1.478    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13488, routed)       0.632     2.136    compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/xclk
    SLICE_X13Y35         FDRE                                         r  compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/inreg_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y35         FDRE (Prop_fdre_C_Q)         0.091     2.227 r  compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/inreg_reg[8]/Q
                         net (fo=1, routed)           0.054     2.281    compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/ram_reg_0_15_6_11/DIB0
    SLICE_X12Y35         RAMD32                                       r  compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/ram_reg_0_15_6_11/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.840     1.782    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13488, routed)       0.852     2.664    compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/ram_reg_0_15_6_11/WCLK
    SLICE_X12Y35         RAMD32                                       r  compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/ram_reg_0_15_6_11/RAMB/CLK
                         clock pessimism             -0.517     2.147    
    SLICE_X12Y35         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.096     2.243    compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/ram_reg_0_15_6_11/RAMB
  -------------------------------------------------------------------
                         required time                         -2.243    
                         arrival time                           2.281    
  -------------------------------------------------------------------
                         slack                                  0.038    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         xclk
Waveform(ns):       { 0.000 2.083 }
Period(ns):         4.167
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     DSP48E1/CLK        n/a            3.292         4.167       0.875      DSP48_X2Y1      compressor393_i/cmprs_channel_block[0].jp_channel_i/focus_sharp393_i/mult_p_r_reg/CLK
Max Period        n/a     PLLE2_ADV/CLKOUT1  n/a            160.000       4.167       155.833    PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
Low Pulse Width   Slow    RAMD32/CLK         n/a            0.910         2.083       1.173      SLICE_X88Y4     compressor393_i/cmprs_channel_block[2].jp_channel_i/dct2d8x8_chen_i/dct1d_chen_reorder_in_i/bufh_ram_reg_0_3_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK         n/a            0.910         2.083       1.173      SLICE_X58Y13    compressor393_i/cmprs_channel_block[3].jp_channel_i/focus_sharp393_i/ram4_reg_0_3_0_4/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  ffclk0
  To Clock:  ffclk0

Setup :            0  Failing Endpoints,  Worst Slack       40.972ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.211ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       10.833ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             40.972ns  (required time - arrival time)
  Source:                 clocks393_i/test_clk_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Destination:            clocks393_i/test_clk_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Path Group:             ffclk0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            41.667ns  (ffclk0 rise@41.667ns - ffclk0 rise@0.000ns)
  Data Path Delay:        0.731ns  (logic 0.361ns (49.417%)  route 0.370ns (50.583%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.390ns = ( 46.057 - 41.667 ) 
    Source Clock Delay      (SCD):    4.689ns
    Clock Pessimism Removal (CPR):    0.299ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.206     3.112    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.120     3.232 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.457     4.689    clocks393_i/clk_in
    SLICE_X20Y91         FDCE                                         r  clocks393_i/test_clk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y91         FDCE (Prop_fdce_C_Q)         0.308     4.997 f  clocks393_i/test_clk_reg[1]/Q
                         net (fo=4, routed)           0.370     5.366    clocks393_i/test_clk_reg
    SLICE_X20Y91         LUT1 (Prop_lut1_I0_O)        0.053     5.419 r  clocks393_i/test_clk[1]_i_1/O
                         net (fo=1, routed)           0.000     5.419    clocks393_i/test_clk[1]_i_1_n_0
    SLICE_X20Y91         FDCE                                         r  clocks393_i/test_clk_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock ffclk0 rise edge)    41.667    41.667 r  
    Y12                                               0.000    41.667 r  ffclk0p (IN)
                         net (fo=0)                   0.000    41.667    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    42.494 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.102    44.596    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.113    44.709 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.348    46.057    clocks393_i/clk_in
    SLICE_X20Y91         FDCE                                         r  clocks393_i/test_clk_reg[1]/C
                         clock pessimism              0.299    46.356    
                         clock uncertainty           -0.035    46.320    
    SLICE_X20Y91         FDCE (Setup_fdce_C_D)        0.071    46.391    clocks393_i/test_clk_reg[1]
  -------------------------------------------------------------------
                         required time                         46.391    
                         arrival time                          -5.419    
  -------------------------------------------------------------------
                         slack                                 40.972    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.211ns  (arrival time - required time)
  Source:                 clocks393_i/test_clk_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Destination:            clocks393_i/test_clk_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Path Group:             ffclk0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ffclk0 rise@0.000ns - ffclk0 rise@0.000ns)
  Data Path Delay:        0.298ns  (logic 0.146ns (49.073%)  route 0.152ns (50.927%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.301ns
    Source Clock Delay      (SCD):    1.949ns
    Clock Pessimism Removal (CPR):    0.352ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.896     1.342    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.026     1.368 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.581     1.949    clocks393_i/clk_in
    SLICE_X20Y91         FDCE                                         r  clocks393_i/test_clk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y91         FDCE (Prop_fdce_C_Q)         0.118     2.067 f  clocks393_i/test_clk_reg[1]/Q
                         net (fo=4, routed)           0.152     2.218    clocks393_i/test_clk_reg
    SLICE_X20Y91         LUT1 (Prop_lut1_I0_O)        0.028     2.246 r  clocks393_i/test_clk[1]_i_1/O
                         net (fo=1, routed)           0.000     2.246    clocks393_i/test_clk[1]_i_1_n_0
    SLICE_X20Y91         FDCE                                         r  clocks393_i/test_clk_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.967     1.488    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.030     1.518 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.783     2.301    clocks393_i/clk_in
    SLICE_X20Y91         FDCE                                         r  clocks393_i/test_clk_reg[1]/C
                         clock pessimism             -0.352     1.949    
    SLICE_X20Y91         FDCE (Hold_fdce_C_D)         0.087     2.036    clocks393_i/test_clk_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.036    
                         arrival time                           2.246    
  -------------------------------------------------------------------
                         slack                                  0.211    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ffclk0
Waveform(ns):       { 0.000 20.833 }
Period(ns):         41.667
Sources:            { ffclk0p }

Check Type        Corner  Lib Pin           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFG/I            n/a            1.600         41.667      40.067     BUFGCTRL_X0Y8   PLLE2_ADV_i_i_1__0/I
Max Period        n/a     PLLE2_ADV/CLKIN1  n/a            52.633        41.667      10.966     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1  n/a            10.000        20.833      10.833     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1  n/a            10.000        20.833      10.833     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  clkfb
  To Clock:  clkfb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       10.966ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clkfb
Waveform(ns):       { 0.000 20.833 }
Period(ns):         41.667
Sources:            { clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            1.249         41.667      40.418     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT
Max Period  n/a     PLLE2_ADV/CLKFBIN   n/a            52.633        41.667      10.966     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  pclk
  To Clock:  pclk

Setup :            0  Failing Endpoints,  Worst Slack       45.389ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.036ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       49.090ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             45.389ns  (required time - arrival time)
  Source:                 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/cs_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i/CE
                            (falling edge-triggered cell ODDR clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Path Group:             pclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (pclk fall@50.000ns - pclk rise@0.000ns)
  Data Path Delay:        4.200ns  (logic 0.371ns (8.834%)  route 3.829ns (91.166%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.294ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    7.936ns = ( 57.936 - 50.000 ) 
    Source Clock Delay      (SCD):    8.070ns
    Clock Pessimism Removal (CPR):    0.428ns
  Clock Uncertainty:      0.166ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.324ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.206     3.112    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.120     3.232 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.609     4.841    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     4.929 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.633     6.562    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     6.682 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5314, routed)        1.388     8.070    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/clk1x
    SLICE_X38Y83         FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/cs_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y83         FDRE (Prop_fdre_C_Q)         0.308     8.378 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/cs_r_reg[0]/Q
                         net (fo=38, routed)          0.959     9.336    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/spi_clken
    SLICE_X33Y82         LUT3 (Prop_lut3_I2_O)        0.063     9.399 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/ODDR_i_i_1__0/O
                         net (fo=1, routed)           2.870    12.269    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ce
    OLOGIC_X0Y11         ODDR                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i/CE
  -------------------------------------------------------------------    -------------------

                         (clock pclk fall edge)      50.000    50.000 f  
    Y12                                               0.000    50.000 f  ffclk0p (IN)
                         net (fo=0)                   0.000    50.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    50.827 f  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.102    52.929    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.113    53.042 f  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.476    54.518    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083    54.601 f  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.550    56.151    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113    56.264 f  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5314, routed)        1.672    57.936    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/clk1x
    OLOGIC_X0Y11         ODDR                                         f  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i/C
                         clock pessimism              0.428    58.364    
                         clock uncertainty           -0.166    58.198    
    OLOGIC_X0Y11         ODDR (Setup_oddr_C_CE)      -0.540    57.658    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i
  -------------------------------------------------------------------
                         required time                         57.658    
                         arrival time                         -12.269    
  -------------------------------------------------------------------
                         slack                                 45.389    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Destination:            sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Path Group:             pclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (pclk rise@0.000ns - pclk rise@0.000ns)
  Data Path Delay:        0.406ns  (logic 0.253ns (62.243%)  route 0.153ns (37.757%))
  Logic Levels:           3  (CARRY4=2 LUT3=1)
  Clock Path Skew:        0.299ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.945ns
    Source Clock Delay      (SCD):    3.202ns
    Clock Pessimism Removal (CPR):    0.444ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.896     1.342    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.026     1.368 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.603     1.971    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.021 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.584     2.605    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     2.631 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5314, routed)        0.571     3.202    sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/clk1x
    SLICE_X109Y149       FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y149       FDRE (Prop_fdre_C_Q)         0.100     3.302 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg[20]/Q
                         net (fo=5, routed)           0.153     3.454    sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg_n_0_[20]
    SLICE_X109Y149       LUT3 (Prop_lut3_I2_O)        0.028     3.482 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X0_carry__3_i_2/O
                         net (fo=1, routed)           0.000     3.482    sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X0_carry__3_i_2_n_0
    SLICE_X109Y149       CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.084     3.566 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X0_carry__3/CO[3]
                         net (fo=1, routed)           0.001     3.567    sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X0_carry__3_n_0
    SLICE_X109Y150       CARRY4 (Prop_carry4_CI_O[0])
                                                      0.041     3.608 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X0_carry__4/O[0]
                         net (fo=1, routed)           0.000     3.608    sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X[21]
    SLICE_X109Y150       FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.967     1.488    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.030     1.518 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.815     2.333    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.386 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.651     3.037    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     3.067 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5314, routed)        0.878     3.945    sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/clk1x
    SLICE_X109Y150       FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg[21]/C
                         clock pessimism             -0.444     3.501    
    SLICE_X109Y150       FDRE (Hold_fdre_C_D)         0.071     3.572    sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg[21]
  -------------------------------------------------------------------
                         required time                         -3.572    
                         arrival time                           3.608    
  -------------------------------------------------------------------
                         slack                                  0.036    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pclk
Waveform(ns):       { 0.000 50.000 }
Period(ns):         100.001
Sources:            { clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     DSP48E1/CLK        n/a            3.124         100.001     96.877     DSP48_X5Y64     sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_gamma_i/table_mult/CLK
Max Period        n/a     PLLE2_ADV/CLKOUT0  n/a            160.000       100.001     59.999     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
Low Pulse Width   Slow    RAMD32/CLK         n/a            0.910         50.000      49.090     SLICE_X70Y165   sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK         n/a            0.910         50.000      49.090     SLICE_X54Y163   sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  gtrefclk
  To Clock:  gtrefclk

Setup :            0  Failing Endpoints,  Worst Slack        3.795ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.269ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.553ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.795ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             gtrefclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (gtrefclk rise@6.666ns - gtrefclk rise@0.000ns)
  Data Path Delay:        2.574ns  (logic 0.414ns (16.087%)  route 2.160ns (83.913%))
  Logic Levels:           2  (LUT3=1 LUT6=1)
  Clock Path Skew:        -0.018ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.442ns = ( 8.108 - 6.666 ) 
    Source Clock Delay      (SCD):    1.565ns
    Clock Pessimism Removal (CPR):    0.105ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
                         net (fo=25, routed)          1.565     1.565    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X62Y42         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y42         FDRE (Prop_fdre_C_Q)         0.308     1.873 r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/Q
                         net (fo=5, routed)           0.844     2.718    sata_top/ahci_sata_layers_i/phy/rst_timer_reg__0[2]
    SLICE_X62Y42         LUT6 (Prop_lut6_I1_O)        0.053     2.771 f  sata_top/ahci_sata_layers_i/phy/sata_areset_i_2/O
                         net (fo=4, routed)           0.709     3.479    sata_top/ahci_sata_layers_i/phy/sata_areset_i_2_n_0
    SLICE_X58Y44         LUT3 (Prop_lut3_I2_O)        0.053     3.532 r  sata_top/ahci_sata_layers_i/phy/rst_timer[7]_i_2/O
                         net (fo=8, routed)           0.607     4.139    sata_top/ahci_sata_layers_i/phy/rst_timer[7]_i_2_n_0
    SLICE_X63Y42         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock gtrefclk rise edge)
                                                      6.666     6.666 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
                         net (fo=25, routed)          1.442     8.108    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X63Y42         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/C
                         clock pessimism              0.105     8.213    
                         clock uncertainty           -0.035     8.178    
    SLICE_X63Y42         FDRE (Setup_fdre_C_CE)      -0.244     7.934    sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]
  -------------------------------------------------------------------
                         required time                          7.934    
                         arrival time                          -4.139    
  -------------------------------------------------------------------
                         slack                                  3.795    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.269ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             gtrefclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gtrefclk rise@0.000ns - gtrefclk rise@0.000ns)
  Data Path Delay:        0.330ns  (logic 0.157ns (47.568%)  route 0.173ns (52.432%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.654ns
    Source Clock Delay      (SCD):    0.451ns
    Clock Pessimism Removal (CPR):    0.203ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
                         net (fo=25, routed)          0.451     0.451    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X65Y38         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y38         FDRE (Prop_fdre_C_Q)         0.091     0.542 r  sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg[4]/Q
                         net (fo=4, routed)           0.173     0.715    sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg__0[4]
    SLICE_X65Y38         LUT5 (Prop_lut5_I1_O)        0.066     0.781 r  sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt[6]_i_2/O
                         net (fo=1, routed)           0.000     0.781    sata_top/ahci_sata_layers_i/phy/p_0_in__2[6]
    SLICE_X65Y38         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
                         net (fo=25, routed)          0.654     0.654    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X65Y38         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg[6]/C
                         clock pessimism             -0.203     0.451    
    SLICE_X65Y38         FDRE (Hold_fdre_C_D)         0.061     0.512    sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg[6]
  -------------------------------------------------------------------
                         required time                         -0.512    
                         arrival time                           0.781    
  -------------------------------------------------------------------
                         slack                                  0.269    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         gtrefclk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.666
Sources:            { sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O }

Check Type        Corner  Lib Pin                  Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/GTREFCLK0  n/a            1.538         6.666       5.128      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/GTREFCLK0
Low Pulse Width   Fast    SRL16E/CLK               n/a            0.780         3.333       2.553      SLICE_X62Y41        sata_top/ahci_sata_layers_i/phy/rxreset_f_r_reg_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK               n/a            0.780         3.333       2.553      SLICE_X62Y41        sata_top/ahci_sata_layers_i/phy/rxreset_f_r_reg_srl2/CLK



---------------------------------------------------------------------------------------------------
From Clock:  rx_clk
  To Clock:  rx_clk

Setup :            0  Failing Endpoints,  Worst Slack        0.588ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.040ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.423ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.588ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E1 clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             rx_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (rx_clk rise@6.666ns - rx_clk rise@0.000ns)
  Data Path Delay:        5.672ns  (logic 1.193ns (21.033%)  route 4.479ns (78.967%))
  Logic Levels:           6  (LUT3=4 LUT6=2)
  Clock Path Skew:        -0.152ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.676ns = ( 9.342 - 6.666 ) 
    Source Clock Delay      (SCD):    2.884ns
    Clock Pessimism Removal (CPR):    0.056ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           1.349     1.349    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.120     1.469 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
                         net (fo=327, routed)         1.415     2.884    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/CLK
    RAMB36_X3Y16         RAMB36E1                                     r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X3Y16         RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[4])
                                                      0.748     3.632 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/DOBDO[4]
                         net (fo=5, routed)           1.549     5.180    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/rxdata_dec_out[12]
    SLICE_X35Y100        LUT6 (Prop_lut6_I5_O)        0.053     5.233 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[15]_i_5/O
                         net (fo=7, routed)           0.482     5.715    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/data_in_r_reg[2]
    SLICE_X32Y100        LUT3 (Prop_lut3_I1_O)        0.065     5.780 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/is_prim_r[11]_i_3/O
                         net (fo=2, routed)           0.326     6.106    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/RAMB36E1_i_0
    SLICE_X32Y100        LUT6 (Prop_lut6_I5_O)        0.168     6.274 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[16]_i_2/O
                         net (fo=4, routed)           0.353     6.627    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r_reg[16]
    SLICE_X33Y103        LUT3 (Prop_lut3_I2_O)        0.053     6.680 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_aligned_r_i_2/O
                         net (fo=5, routed)           0.577     7.257    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/RAMB36E1_i_0
    SLICE_X36Y106        LUT3 (Prop_lut3_I1_O)        0.053     7.310 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/msb_in_r_i_1/O
                         net (fo=2, routed)           0.763     8.072    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/msb_in_r_i_1_n_0
    SLICE_X38Y120        LUT3 (Prop_lut3_I0_O)        0.053     8.125 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/xlnx_opt_LUT_wen_reg[0]_CE_cooolgate_en_gate_1470/O
                         net (fo=6, routed)           0.430     8.556    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]_CE_cooolgate_en_sig_254
    SLICE_X38Y120        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock rx_clk rise edge)     6.666     6.666 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           1.300     7.966    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.113     8.079 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
                         net (fo=327, routed)         1.263     9.342    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/CLK
    SLICE_X38Y120        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]/C
                         clock pessimism              0.056     9.398    
                         clock uncertainty           -0.035     9.363    
    SLICE_X38Y120        FDRE (Setup_fdre_C_CE)      -0.219     9.144    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]
  -------------------------------------------------------------------
                         required time                          9.144    
                         arrival time                          -8.556    
  -------------------------------------------------------------------
                         slack                                  0.588    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.040ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             rx_clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rx_clk rise@0.000ns - rx_clk rise@0.000ns)
  Data Path Delay:        0.306ns  (logic 0.118ns (38.588%)  route 0.188ns (61.412%))
  Logic Levels:           0  
  Clock Path Skew:        0.228ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.374ns
    Source Clock Delay      (SCD):    1.105ns
    Clock Pessimism Removal (CPR):    0.041ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           0.526     0.526    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     0.552 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
                         net (fo=327, routed)         0.553     1.105    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/CLK
    SLICE_X26Y100        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y100        FDRE (Prop_fdre_C_Q)         0.118     1.223 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg[1]/Q
                         net (fo=5, routed)           0.188     1.411    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg_n_0_[1]
    SLICE_X27Y99         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           0.563     0.563    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.030     0.593 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
                         net (fo=327, routed)         0.781     1.374    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/CLK
    SLICE_X27Y99         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg[2]/C
                         clock pessimism             -0.041     1.333    
    SLICE_X27Y99         FDRE (Hold_fdre_C_D)         0.038     1.371    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.371    
                         arrival time                           1.411    
  -------------------------------------------------------------------
                         slack                                  0.040    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         rx_clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.666
Sources:            { sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/RXUSRCLK  n/a            4.000         6.666       2.666      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXUSRCLK
Low Pulse Width   Fast    RAMD32/CLK              n/a            0.910         3.333       2.423      SLICE_X32Y101       sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK              n/a            0.910         3.333       2.423      SLICE_X32Y101       sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  txoutclk
  To Clock:  txoutclk

Setup :            0  Failing Endpoints,  Worst Slack        2.159ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.159ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.666ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.159ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/ADDRARDADDR[6]
                            (rising edge-triggered cell RAMB36E1 clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             txoutclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (txoutclk rise@6.666ns - txoutclk rise@0.000ns)
  Data Path Delay:        4.060ns  (logic 0.246ns (6.060%)  route 3.814ns (93.940%))
  Logic Levels:           0  
  Clock Path Skew:        0.172ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.970ns = ( 9.636 - 6.666 ) 
    Source Clock Delay      (SCD):    2.864ns
    Clock Pessimism Removal (CPR):    0.066ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock txoutclk rise edge)
                                                      0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           1.349     1.349    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.120     1.469 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
                         net (fo=136, routed)         1.395     2.864    sata_top/ahci_sata_layers_i/phy/gtx_wrap/CLK
    SLICE_X44Y96         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y96         FDRE (Prop_fdre_C_Q)         0.246     3.110 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[1]/Q
                         net (fo=1, routed)           3.814     6.924    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/ADDRARDADDR[1]
    RAMB36_X5Y3          RAMB36E1                                     r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/ADDRARDADDR[6]
  -------------------------------------------------------------------    -------------------

                         (clock txoutclk rise edge)
                                                      6.666     6.666 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           1.300     7.966    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.113     8.079 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
                         net (fo=136, routed)         1.557     9.636    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/CLK
    RAMB36_X5Y3          RAMB36E1                                     r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/CLKARDCLK
                         clock pessimism              0.066     9.702    
                         clock uncertainty           -0.035     9.666    
    RAMB36_X5Y3          RAMB36E1 (Setup_ramb36e1_CLKARDCLK_ADDRARDADDR[6])
                                                     -0.584     9.082    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i
  -------------------------------------------------------------------
                         required time                          9.082    
                         arrival time                          -6.924    
  -------------------------------------------------------------------
                         slack                                  2.159    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.159ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXDATA[8]
                            (rising edge-triggered cell GTXE2_CHANNEL clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             txoutclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (txoutclk rise@0.000ns - txoutclk rise@0.000ns)
  Data Path Delay:        0.467ns  (logic 0.100ns (21.400%)  route 0.367ns (78.600%))
  Logic Levels:           0  
  Clock Path Skew:        0.230ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.645ns
    Source Clock Delay      (SCD):    1.186ns
    Clock Pessimism Removal (CPR):    0.229ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock txoutclk rise edge)
                                                      0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           0.526     0.526    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026     0.552 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
                         net (fo=136, routed)         0.634     1.186    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/CLK
    SLICE_X103Y6         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y6         FDRE (Prop_fdre_C_Q)         0.100     1.286 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[10]/Q
                         net (fo=1, routed)           0.367     1.653    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/outdata_l_reg[19][10]
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                                r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXDATA[8]
  -------------------------------------------------------------------    -------------------

                         (clock txoutclk rise edge)
                                                      0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           0.563     0.563    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.030     0.593 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
                         net (fo=136, routed)         1.052     1.645    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/rxreset_f_rr_reg__0
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                                r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXUSRCLK2
                         clock pessimism             -0.229     1.416    
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL (Hold_gtxe2_channel_TXUSRCLK2_TXDATA[8])
                                                      0.078     1.494    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims
  -------------------------------------------------------------------
                         required time                         -1.494    
                         arrival time                           1.653    
  -------------------------------------------------------------------
                         slack                                  0.159    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         txoutclk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.666
Sources:            { sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/TXUSRCLK  n/a            4.000         6.666       2.666      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXUSRCLK
Low Pulse Width   Fast    FDCE/C                  n/a            0.400         3.333       2.933      SLICE_X40Y97        sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/data_out_reg[14]/C
High Pulse Width  Slow    FDRE/C                  n/a            0.350         3.333       2.983      SLICE_X93Y13        sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/table0_r_reg[12]/C



---------------------------------------------------------------------------------------------------
From Clock:  usrclk2
  To Clock:  usrclk2

Setup :            0  Failing Endpoints,  Worst Slack        3.117ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.053ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        5.756ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.117ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Destination:            sata_top/ahci_top_i/datascope_timing_i/h2d_nready_cntr_reg[6]/R
                            (rising edge-triggered cell FDRE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Path Group:             usrclk2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            13.333ns  (usrclk2 rise@13.333ns - usrclk2 rise@0.000ns)
  Data Path Delay:        9.626ns  (logic 0.322ns (3.345%)  route 9.304ns (96.655%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.188ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.904ns = ( 16.237 - 13.333 ) 
    Source Clock Delay      (SCD):    3.347ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X65Y43         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.637     1.637    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.120     1.757 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.590     3.347    sata_top/ahci_sata_layers_i/phy/rxdata_reg[0]__0
    SLICE_X65Y39         FDCE                                         r  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y39         FDCE (Prop_fdce_C_Q)         0.269     3.616 f  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/Q
                         net (fo=2, routed)           0.655     4.271    sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg_n_0_[0]
    SLICE_X62Y41         LUT3 (Prop_lut3_I0_O)        0.053     4.324 r  sata_top/ahci_sata_layers_i/phy/was_rst_i_1/O
                         net (fo=278, routed)         8.649    12.972    sata_top/ahci_top_i/datascope_timing_i/sata_reset_done_r_reg[0]
    SLICE_X44Y160        FDRE                                         r  sata_top/ahci_top_i/datascope_timing_i/h2d_nready_cntr_reg[6]/R
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)   13.333    13.333 r  
    SLICE_X65Y43         FDRE                         0.000    13.333 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.389    14.722    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.113    14.835 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.402    16.237    sata_top/ahci_top_i/datascope_timing_i/usrclk2_r_reg
    SLICE_X44Y160        FDRE                                         r  sata_top/ahci_top_i/datascope_timing_i/h2d_nready_cntr_reg[6]/C
                         clock pessimism              0.255    16.492    
                         clock uncertainty           -0.035    16.456    
    SLICE_X44Y160        FDRE (Setup_fdre_C_R)       -0.367    16.089    sata_top/ahci_top_i/datascope_timing_i/h2d_nready_cntr_reg[6]
  -------------------------------------------------------------------
                         required time                         16.089    
                         arrival time                         -12.972    
  -------------------------------------------------------------------
                         slack                                  3.117    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.053ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/oob_ctrl/oob/txdata_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_0_5/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Path Group:             usrclk2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (usrclk2 rise@0.000ns - usrclk2 rise@0.000ns)
  Data Path Delay:        0.198ns  (logic 0.100ns (50.559%)  route 0.098ns (49.441%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.627ns
    Source Clock Delay      (SCD):    1.293ns
    Clock Pessimism Removal (CPR):    0.320ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X65Y43         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           0.718     0.718    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.026     0.744 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.549     1.293    sata_top/ahci_sata_layers_i/phy/oob_ctrl/oob/usrclk2_r_reg
    SLICE_X39Y98         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/oob_ctrl/oob/txdata_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y98         FDRE (Prop_fdre_C_Q)         0.100     1.393 r  sata_top/ahci_sata_layers_i/phy/oob_ctrl/oob/txdata_reg[0]/Q
                         net (fo=1, routed)           0.098     1.491    sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_0_5/DIA0
    SLICE_X36Y98         RAMD32                                       r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_0_5/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X65Y43         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           0.848     0.848    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.030     0.878 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.749     1.627    sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_0_5/WCLK
    SLICE_X36Y98         RAMD32                                       r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_0_5/RAMA/CLK
                         clock pessimism             -0.320     1.307    
    SLICE_X36Y98         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.131     1.438    sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_0_5/RAMA
  -------------------------------------------------------------------
                         required time                         -1.438    
                         arrival time                           1.491    
  -------------------------------------------------------------------
                         slack                                  0.053    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         usrclk2
Waveform(ns):       { 0.000 6.666 }
Period(ns):         13.333
Sources:            { sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.183         13.333      11.150     RAMB36_X2Y24   sata_top/ahci_top_i/ahci_dma_i/ct_data_ram_reg_bram_0/CLKARDCLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.910         6.667       5.757      SLICE_X34Y133  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/fifo0_ram_reg_0_7_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.910         6.666       5.756      SLICE_X34Y133  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/fifo0_ram_reg_0_7_0_5/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_div
  To Clock:  ddr3_clk

Setup :            0  Failing Endpoints,  Worst Slack        0.319ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.215ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.319ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
                            (rising edge-triggered cell FDSE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/oserdes_i/T1
                            (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk  {rise@0.000ns fall@1.250ns period=2.500ns})
  Path Group:             ddr3_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.500ns  (ddr3_clk rise@2.500ns - ddr3_clk_div rise@0.000ns)
  Data Path Delay:        1.292ns  (logic 0.269ns (20.815%)  route 1.023ns (79.185%))
  Logic Levels:           0  
  Clock Path Skew:        -0.004ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.643ns = ( 6.143 - 2.500 ) 
    Source Clock Delay      (SCD):    3.790ns
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     1.575    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.088     1.663 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.106     2.769    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.377     3.146 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.644     3.790    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
    SLICE_X116Y124       FDSE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X116Y124       FDSE (Prop_fdse_C_Q)         0.269     4.059 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/Q
                         net (fo=23, routed)          1.023     5.082    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/in_tri_r_reg
    OLOGIC_X1Y103        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/oserdes_i/T1
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk rise edge)
                                                      2.500     2.500 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     2.500 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     3.937    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.083     4.020 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.016     5.036    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_pre
    BUFR_X1Y8            BUFR (Prop_bufr_I_O)         0.370     5.406 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/O
                         net (fo=75, routed)          0.737     6.143    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/clk
    OLOGIC_X1Y103        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/oserdes_i/CLK
                         clock pessimism              0.143     6.286    
                         clock uncertainty           -0.205     6.081    
    OLOGIC_X1Y103        OSERDESE2 (Setup_oserdese2_CLK_T1)
                                                     -0.679     5.402    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/oserdes_i
  -------------------------------------------------------------------
                         required time                          5.402    
                         arrival time                          -5.082    
  -------------------------------------------------------------------
                         slack                                  0.319    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.215ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
                            (rising edge-triggered cell FDSE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[7].cmda_addr_i/oserdes_i/oserdes_i/T1
                            (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk  {rise@0.000ns fall@1.250ns period=2.500ns})
  Path Group:             ddr3_clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_clk rise@0.000ns - ddr3_clk_div rise@0.000ns)
  Data Path Delay:        0.479ns  (logic 0.100ns (20.888%)  route 0.379ns (79.112%))
  Logic Levels:           0  
  Clock Path Skew:        0.162ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.796ns
    Source Clock Delay      (SCD):    1.415ns
    Clock Pessimism Removal (CPR):    0.219ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     0.580    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.050     0.630 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.433     1.063    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.090     1.153 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.262     1.415    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
    SLICE_X116Y124       FDSE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X116Y124       FDSE (Prop_fdse_C_Q)         0.100     1.515 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/Q
                         net (fo=23, routed)          0.379     1.894    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[7].cmda_addr_i/oserdes_i/in_tri_r_reg
    OLOGIC_X1Y112        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[7].cmda_addr_i/oserdes_i/oserdes_i/T1
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     0.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     0.849 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.490     1.339    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_pre
    BUFR_X1Y8            BUFR (Prop_bufr_I_O)         0.093     1.432 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/O
                         net (fo=75, routed)          0.364     1.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[7].cmda_addr_i/oserdes_i/clk
    OLOGIC_X1Y112        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[7].cmda_addr_i/oserdes_i/oserdes_i/CLK
                         clock pessimism             -0.219     1.577    
                         clock uncertainty            0.205     1.782    
    OLOGIC_X1Y112        OSERDESE2 (Hold_oserdese2_CLK_T1)
                                                     -0.104     1.678    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[7].cmda_addr_i/oserdes_i/oserdes_i
  -------------------------------------------------------------------
                         required time                         -1.678    
                         arrival time                           1.894    
  -------------------------------------------------------------------
                         slack                                  0.215    





---------------------------------------------------------------------------------------------------
From Clock:  ddr3_mclk
  To Clock:  ddr3_clk_div

Setup :            0  Failing Endpoints,  Worst Slack        0.080ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        1.433ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.080ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK
                            (rising edge-triggered cell RAMB36E1 clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a_r_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.750ns  (ddr3_clk_div rise@5.000ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        2.261ns  (logic 0.854ns (37.772%)  route 1.407ns (62.228%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -1.239ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.527ns = ( 8.527 - 5.000 ) 
    Source Clock Delay      (SCD):    4.909ns = ( 6.159 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32797, routed)       1.498     6.159    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/CLK
    RAMB36_X7Y19         RAMB36E1                                     r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X7Y19         RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[13])
                                                      0.748     6.907 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/DOADO[13]
                         net (fo=1, routed)           0.773     7.679    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_0[12]
    SLICE_X112Y104       LUT4 (Prop_lut4_I3_O)        0.053     7.732 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/in_a_r[29]_i_4/O
                         net (fo=24, routed)          0.634     8.367    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/phy_cmd_word[13]
    SLICE_X115Y102       LUT6 (Prop_lut6_I4_O)        0.053     8.420 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/in_a_r[27]_i_1/O
                         net (fo=1, routed)           0.000     8.420    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a[12]
    SLICE_X115Y102       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a_r_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      5.000     5.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     5.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     6.437    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.083     6.520 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.016     7.536    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.370     7.906 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.621     8.527    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
    SLICE_X115Y102       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a_r_reg[27]/C
                         clock pessimism              0.143     8.670    
                         clock uncertainty           -0.205     8.465    
    SLICE_X115Y102       FDRE (Setup_fdre_C_D)        0.035     8.500    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a_r_reg[27]
  -------------------------------------------------------------------
                         required time                          8.500    
                         arrival time                          -8.420    
  -------------------------------------------------------------------
                         slack                                  0.080    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.433ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/deser_r_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            -1.250ns  (ddr3_clk_div rise@0.000ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        0.207ns  (logic 0.100ns (48.240%)  route 0.107ns (51.760%))
  Logic Levels:           0  
  Clock Path Skew:        -0.219ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.780ns
    Source Clock Delay      (SCD):    1.780ns = ( 3.030 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.219ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     1.830    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.050     1.880 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.559     2.439    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.465 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32797, routed)       0.565     3.030    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/CLK
    SLICE_X98Y103        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/deser_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y103        FDRE (Prop_fdre_C_Q)         0.100     3.130 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/deser_r_reg[5]/Q
                         net (fo=1, routed)           0.107     3.237    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/deser_r_reg[6][5]
    SLICE_X98Y101        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     0.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.053     0.849 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.490     1.339    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.093     1.432 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.348     1.780    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div
    SLICE_X98Y101        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[5]/C
                         clock pessimism             -0.219     1.561    
                         clock uncertainty            0.205     1.766    
    SLICE_X98Y101        FDRE (Hold_fdre_C_D)         0.038     1.804    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[5]
  -------------------------------------------------------------------
                         required time                         -1.804    
                         arrival time                           3.237    
  -------------------------------------------------------------------
                         slack                                  1.433    





---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_div
  To Clock:  ddr3_mclk

Setup :            0  Failing Endpoints,  Worst Slack        3.006ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.162ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.006ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[4].dq_i/iserdes_mem_i/iserdes_i/CLKDIV
                            (rising edge-triggered cell ISERDESE2 clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata_r_reg[60]/D
                            (falling edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             ddr3_mclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.750ns  (ddr3_mclk fall@3.750ns - ddr3_clk_div rise@0.000ns)
  Data Path Delay:        1.427ns  (logic 0.573ns (40.141%)  route 0.854ns (59.859%))
  Logic Levels:           0  
  Clock Path Skew:        0.902ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.557ns = ( 8.307 - 3.750 ) 
    Source Clock Delay      (SCD):    3.798ns
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     1.575    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.088     1.663 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.106     2.769    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.377     3.146 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.652     3.798    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[4].dq_i/iserdes_mem_i/psincdec_reg
    ILOGIC_X1Y134        ISERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[4].dq_i/iserdes_mem_i/iserdes_i/CLKDIV
  -------------------------------------------------------------------    -------------------
    ILOGIC_X1Y134        ISERDESE2 (Prop_iserdese2_CLKDIV_Q1)
                                                      0.573     4.371 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[4].dq_i/iserdes_mem_i/iserdes_i/Q1
                         net (fo=1, routed)           0.854     5.225    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata[60]
    SLICE_X114Y125       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata_r_reg[60]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk fall edge)
                                                      3.750     3.750 f  
    BUFGCTRL_X0Y17       BUFG                         0.000     3.750 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     5.187    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.083     5.270 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.544     6.814    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.113     6.927 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32797, routed)       1.380     8.307    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/CLK
    SLICE_X114Y125       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata_r_reg[60]/C  (IS_INVERTED)
                         clock pessimism              0.143     8.450    
                         clock uncertainty           -0.205     8.245    
    SLICE_X114Y125       FDRE (Setup_fdre_C_D)       -0.013     8.232    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata_r_reg[60]
  -------------------------------------------------------------------
                         required time                          8.232    
                         arrival time                          -5.225    
  -------------------------------------------------------------------
                         slack                                  3.006    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.162ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[1]/C
                            (falling edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             ddr3_mclk
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            -1.250ns  (ddr3_mclk rise@1.250ns - ddr3_clk_div fall@2.500ns)
  Data Path Delay:        0.426ns  (logic 0.218ns (51.120%)  route 0.208ns (48.880%))
  Logic Levels:           0  
  Clock Path Skew:        1.136ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.862ns = ( 6.112 - 1.250 ) 
    Source Clock Delay      (SCD):    3.583ns = ( 6.083 - 2.500 ) 
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div fall edge)
                                                      2.500     2.500 f  
    BUFGCTRL_X0Y17       BUFG                         0.000     2.500 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     3.937    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.083     4.020 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.016     5.036    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.370     5.406 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.677     6.083    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div
    SLICE_X98Y102        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[1]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y102        FDRE (Prop_fdre_C_Q)         0.218     6.301 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[1]/Q
                         net (fo=1, routed)           0.208     6.509    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1[1]
    SLICE_X94Y102        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32797, routed)       1.451     6.112    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/CLK
    SLICE_X94Y102        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]/C
                         clock pessimism             -0.143     5.969    
                         clock uncertainty            0.205     6.174    
    SLICE_X94Y102        FDRE (Hold_fdre_C_D)         0.173     6.347    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]
  -------------------------------------------------------------------
                         required time                         -6.347    
                         arrival time                           6.509    
  -------------------------------------------------------------------
                         slack                                  0.162    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  axihp_clk
  To Clock:  axihp_clk

Setup :            0  Failing Endpoints,  Worst Slack        1.159ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.727ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.159ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            mult_saxi_wr_i/status_wr_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            6.667ns  (axihp_clk rise@6.667ns - axihp_clk rise@0.000ns)
  Data Path Delay:        5.183ns  (logic 0.308ns (5.942%)  route 4.875ns (94.058%))
  Logic Levels:           0  
  Clock Path Skew:        -0.061ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.173ns = ( 11.840 - 6.667 ) 
    Source Clock Delay      (SCD):    5.479ns
    Clock Pessimism Removal (CPR):    0.245ns
  Clock Uncertainty:      0.071ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.124ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     3.904    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        1.455     5.479    sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk
    SLICE_X26Y94         FDRE                                         r  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y94         FDRE (Prop_fdre_C_Q)         0.308     5.787 f  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=335, routed)         4.875    10.662    mult_saxi_wr_i/status_wr_i/rst[0]
    SLICE_X36Y171        FDCE                                         f  mult_saxi_wr_i/status_wr_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      6.667     6.667 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     6.667 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     8.339    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083     8.422 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    10.333    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.113    10.446 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        1.394    11.840    mult_saxi_wr_i/status_wr_i/hclk
    SLICE_X36Y171        FDCE                                         r  mult_saxi_wr_i/status_wr_i/in_reg_reg/C
                         clock pessimism              0.245    12.085    
                         clock uncertainty           -0.071    12.013    
    SLICE_X36Y171        FDCE (Recov_fdce_C_CLR)     -0.192    11.821    mult_saxi_wr_i/status_wr_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         11.821    
                         arrival time                         -10.662    
  -------------------------------------------------------------------
                         slack                                  1.159    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.727ns  (arrival time - required time)
  Source:                 sata_top/nhrst_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/flush_mclk_i/in_reg_reg/CLR
                            (removal check against rising-edge clock axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (axihp_clk rise@0.000ns - axihp_clk rise@0.000ns)
  Data Path Delay:        0.713ns  (logic 0.128ns (17.957%)  route 0.585ns (82.043%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.544ns
    Source Clock Delay      (SCD):    2.027ns
    Clock Pessimism Removal (CPR):    0.481ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.478    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        0.523     2.027    sata_top/hclk
    SLICE_X45Y129        FDCE                                         r  sata_top/nhrst_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y129        FDCE (Prop_fdce_C_Q)         0.100     2.127 r  sata_top/nhrst_r_reg[2]/Q
                         net (fo=30, routed)          0.379     2.506    sata_top/ahci_top_i/ahci_dma_i/cmd_abort_hclk_i/nhrst_r_reg[2][0]
    SLICE_X36Y134        LUT2 (Prop_lut2_I1_O)        0.028     2.534 f  sata_top/ahci_top_i/ahci_dma_i/cmd_abort_hclk_i/mrst_hclk_i_1/O
                         net (fo=9, routed)           0.206     2.740    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/flush_mclk_i/out_reg_reg[2]_0
    SLICE_X38Y133        FDCE                                         f  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/flush_mclk_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.782    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        0.732     2.544    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/flush_mclk_i/hclk
    SLICE_X38Y133        FDCE                                         r  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/flush_mclk_i/in_reg_reg/C
                         clock pessimism             -0.481     2.063    
    SLICE_X38Y133        FDCE (Remov_fdce_C_CLR)     -0.050     2.013    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/flush_mclk_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -2.013    
                         arrival time                           2.740    
  -------------------------------------------------------------------
                         slack                                  0.727    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  ddr3_mclk
  To Clock:  ddr3_mclk

Setup :            0  Failing Endpoints,  Worst Slack        0.741ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.274ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.741ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_early_master_reg_replica_4/C
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            event_logger_i/i_we_config_gps_xclk/in_reg_reg/CLR
                            (recovery check against rising-edge clock ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (ddr3_mclk rise@6.250ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        3.888ns  (logic 0.269ns (6.918%)  route 3.619ns (93.082%))
  Logic Levels:           0  
  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.445ns = ( 10.695 - 6.250 ) 
    Source Clock Delay      (SCD):    4.798ns = ( 6.048 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.323ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32797, routed)       1.387     6.048    sync_resets_i/mclk
    SLICE_X71Y134        FDRE                                         r  sync_resets_i/rst_early_master_reg_replica_4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y134        FDRE (Prop_fdre_C_Q)         0.269     6.317 f  sync_resets_i/rst_early_master_reg_replica_4/Q
                         net (fo=314, routed)         3.619     9.936    event_logger_i/i_we_config_gps_xclk/rst[0]_repN_4_alias
    SLICE_X60Y148        FDCE                                         f  event_logger_i/i_we_config_gps_xclk/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      6.250     6.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     6.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     7.687    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.083     7.770 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.544     9.314    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.113     9.427 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32797, routed)       1.268    10.695    event_logger_i/i_we_config_gps_xclk/mclk
    SLICE_X60Y148        FDCE                                         r  event_logger_i/i_we_config_gps_xclk/in_reg_reg/C
                         clock pessimism              0.323    11.018    
                         clock uncertainty           -0.085    10.933    
    SLICE_X60Y148        FDCE (Recov_fdce_C_CLR)     -0.255    10.678    event_logger_i/i_we_config_gps_xclk/in_reg_reg
  -------------------------------------------------------------------
                         required time                         10.678    
                         arrival time                          -9.936    
  -------------------------------------------------------------------
                         slack                                  0.741    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.274ns  (arrival time - required time)
  Source:                 compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_raw_buf_iface_i/nmrst_reg/C
                            (falling edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_raw_buf_iface_i/reset_page_rd_i/in_reg_reg/CLR
                            (removal check against rising-edge clock ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_mclk fall@3.750ns - ddr3_mclk fall@3.750ns)
  Data Path Delay:        0.476ns  (logic 0.107ns (22.479%)  route 0.369ns (77.521%))
  Logic Levels:           0  
  Clock Path Skew:        0.263ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.318ns = ( 6.068 - 3.750 ) 
    Source Clock Delay      (SCD):    1.760ns = ( 5.510 - 3.750 ) 
    Clock Pessimism Removal (CPR):    0.295ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk fall edge)
                                                      3.750     3.750 f  
    BUFGCTRL_X0Y17       BUFG                         0.000     3.750 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     4.330    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.050     4.380 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.559     4.939    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     4.965 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32797, routed)       0.545     5.510    compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_raw_buf_iface_i/mclk
    SLICE_X63Y55         FDRE                                         r  compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_raw_buf_iface_i/nmrst_reg/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y55         FDRE (Prop_fdre_C_Q)         0.107     5.617 f  compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_raw_buf_iface_i/nmrst_reg/Q
                         net (fo=4, routed)           0.369     5.986    compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_raw_buf_iface_i/reset_page_rd_i/nmrst
    SLICE_X63Y39         FDCE                                         f  compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_raw_buf_iface_i/reset_page_rd_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk fall edge)
                                                      3.750     3.750 f  
    BUFGCTRL_X0Y17       BUFG                         0.000     3.750 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     4.546    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.053     4.599 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.623     5.222    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.030     5.252 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32797, routed)       0.816     6.068    compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_raw_buf_iface_i/reset_page_rd_i/src_clk0
    SLICE_X63Y39         FDCE                                         r  compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_raw_buf_iface_i/reset_page_rd_i/in_reg_reg/C  (IS_INVERTED)
                         clock pessimism             -0.295     5.773    
    SLICE_X63Y39         FDCE (Remov_fdce_C_CLR)     -0.061     5.712    compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_raw_buf_iface_i/reset_page_rd_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -5.712    
                         arrival time                           5.986    
  -------------------------------------------------------------------
                         slack                                  0.274    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  pclk
  To Clock:  pclk

Setup :            0  Failing Endpoints,  Worst Slack       89.858ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.318ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             89.858ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Destination:            sensors393_i/sensor_channel_block[0].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            100.001ns  (pclk rise@100.001ns - pclk rise@0.000ns)
  Data Path Delay:        9.694ns  (logic 0.399ns (4.116%)  route 9.295ns (95.884%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.091ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    7.545ns = ( 107.545 - 100.001 ) 
    Source Clock Delay      (SCD):    8.136ns
    Clock Pessimism Removal (CPR):    0.500ns
  Clock Uncertainty:      0.166ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.324ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.206     3.112    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.120     3.232 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.609     4.841    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     4.929 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.633     6.562    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     6.682 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5314, routed)        1.454     8.136    sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/CLK
    SLICE_X27Y91         FDRE                                         r  sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y91         FDRE (Prop_fdre_C_Q)         0.246     8.382 f  sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=57, routed)          4.463    12.845    sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/Q[0]
    SLICE_X69Y151        LUT2 (Prop_lut2_I0_O)        0.153    12.998 f  sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/sr[0]_i_1__10/O
                         net (fo=100, routed)         4.832    17.830    sensors393_i/sensor_channel_block[0].sensor_channel_i/pulse_cross_clock_eof_mclk_i/prsts
    SLICE_X50Y93         FDCE                                         f  sensors393_i/sensor_channel_block[0].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock pclk rise edge)     100.001   100.001 r  
    Y12                                               0.000   100.001 r  ffclk0p (IN)
                         net (fo=0)                   0.000   100.001    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827   100.827 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.102   102.929    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.113   103.042 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.476   104.518    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083   104.601 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.550   106.151    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113   106.264 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5314, routed)        1.281   107.545    sensors393_i/sensor_channel_block[0].sensor_channel_i/pulse_cross_clock_eof_mclk_i/clk1x
    SLICE_X50Y93         FDCE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/C
                         clock pessimism              0.500   108.046    
                         clock uncertainty           -0.166   107.880    
    SLICE_X50Y93         FDCE (Recov_fdce_C_CLR)     -0.192   107.688    sensors393_i/sensor_channel_block[0].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                        107.688    
                         arrival time                         -17.830    
  -------------------------------------------------------------------
                         slack                                 89.858    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.318ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/en_pclk_reg/C
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/CLR
                            (removal check against rising-edge clock pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (pclk rise@0.000ns - pclk rise@0.000ns)
  Data Path Delay:        0.464ns  (logic 0.157ns (33.839%)  route 0.307ns (66.161%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.215ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.810ns
    Source Clock Delay      (SCD):    3.159ns
    Clock Pessimism Removal (CPR):    0.436ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.896     1.342    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.026     1.368 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.603     1.971    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.021 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.584     2.605    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     2.631 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5314, routed)        0.528     3.159    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/clk1x
    SLICE_X61Y100        FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/en_pclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y100        FDRE (Prop_fdre_C_Q)         0.091     3.250 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/en_pclk_reg/Q
                         net (fo=1, routed)           0.116     3.365    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/en_pclk
    SLICE_X61Y100        LUT1 (Prop_lut1_I0_O)        0.066     3.431 f  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_i_2__2/O
                         net (fo=2, routed)           0.191     3.622    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/rst0
    SLICE_X59Y99         FDCE                                         f  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.967     1.488    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.030     1.518 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.815     2.333    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.386 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.651     3.037    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     3.067 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5314, routed)        0.743     3.810    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/clk1x
    SLICE_X59Y99         FDCE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/C
                         clock pessimism             -0.436     3.374    
    SLICE_X59Y99         FDCE (Remov_fdce_C_CLR)     -0.069     3.305    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -3.305    
                         arrival time                           3.622    
  -------------------------------------------------------------------
                         slack                                  0.318    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  sclk
  To Clock:  sclk

Setup :            0  Failing Endpoints,  Worst Slack        6.877ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.201ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             6.877ns  (required time - arrival time)
  Source:                 timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/sync_zer_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            timing393_i/camsync393_i/i_ts_stb_mclk2/in_reg_reg/CLR
                            (recovery check against rising-edge clock sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (sclk rise@10.000ns - sclk rise@0.000ns)
  Data Path Delay:        2.681ns  (logic 0.404ns (15.068%)  route 2.277ns (84.932%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.111ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.053ns = ( 15.053 - 10.000 ) 
    Source Clock Delay      (SCD):    5.409ns
    Clock Pessimism Removal (CPR):    0.245ns
  Clock Uncertainty:      0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.133ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           2.009     3.904    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        1.385     5.409    timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/CLK
    SLICE_X69Y116        FDRE                                         r  timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/sync_zer_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y116        FDRE (Prop_fdre_C_Q)         0.246     5.655 r  timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/sync_zer_reg[1]/Q
                         net (fo=3, routed)           0.660     6.315    sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/sync_zer_reg[1]_0[0]
    SLICE_X66Y119        LUT2 (Prop_lut2_I1_O)        0.158     6.473 f  sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/in_reg_i_1__121/O
                         net (fo=17, routed)          1.617     8.090    timing393_i/camsync393_i/i_ts_stb_mclk2/regs_reg[1]
    SLICE_X63Y80         FDCE                                         f  timing393_i/camsync393_i/i_ts_stb_mclk2/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sclk rise edge)      10.000    10.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000    10.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672    11.672    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.083    11.755 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.911    13.666    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.113    13.779 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        1.274    15.053    timing393_i/camsync393_i/i_ts_stb_mclk2/CLK
    SLICE_X63Y80         FDCE                                         r  timing393_i/camsync393_i/i_ts_stb_mclk2/in_reg_reg/C
                         clock pessimism              0.245    15.298    
                         clock uncertainty           -0.075    15.223    
    SLICE_X63Y80         FDCE (Recov_fdce_C_CLR)     -0.255    14.968    timing393_i/camsync393_i/i_ts_stb_mclk2/in_reg_reg
  -------------------------------------------------------------------
                         required time                         14.968    
                         arrival time                          -8.090    
  -------------------------------------------------------------------
                         slack                                  6.877    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.201ns  (arrival time - required time)
  Source:                 sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/CLR
                            (removal check against rising-edge clock sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (sclk rise@0.000ns - sclk rise@0.000ns)
  Data Path Delay:        0.348ns  (logic 0.118ns (33.929%)  route 0.230ns (66.071%))
  Logic Levels:           0  
  Clock Path Skew:        0.197ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.532ns
    Source Clock Delay      (SCD):    2.019ns
    Clock Pessimism Removal (CPR):    0.316ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.771     1.478    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        0.515     2.019    sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/pwrdwn_clk_reg[0]
    SLICE_X58Y126        FDRE                                         r  sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y126        FDRE (Prop_fdre_C_Q)         0.118     2.137 f  sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=3, routed)           0.230     2.367    timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/rst[0]
    SLICE_X54Y126        FDCE                                         f  timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.840     1.782    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        0.720     2.532    timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/CLK
    SLICE_X54Y126        FDCE                                         r  timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/C
                         clock pessimism             -0.316     2.216    
    SLICE_X54Y126        FDCE (Remov_fdce_C_CLR)     -0.050     2.166    timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg
  -------------------------------------------------------------------
                         required time                         -2.166    
                         arrival time                           2.367    
  -------------------------------------------------------------------
                         slack                                  0.201    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  usrclk2
  To Clock:  usrclk2

Setup :            0  Failing Endpoints,  Worst Slack        3.039ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.785ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.039ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Destination:            sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            13.333ns  (usrclk2 rise@13.333ns - usrclk2 rise@0.000ns)
  Data Path Delay:        9.815ns  (logic 0.322ns (3.281%)  route 9.493ns (96.719%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.188ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.904ns = ( 16.237 - 13.333 ) 
    Source Clock Delay      (SCD):    3.347ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X65Y43         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.637     1.637    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.120     1.757 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.590     3.347    sata_top/ahci_sata_layers_i/phy/rxdata_reg[0]__0
    SLICE_X65Y39         FDCE                                         r  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y39         FDCE (Prop_fdce_C_Q)         0.269     3.616 r  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/Q
                         net (fo=2, routed)           0.655     4.271    sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg_n_0_[0]
    SLICE_X62Y41         LUT3 (Prop_lut3_I0_O)        0.053     4.324 f  sata_top/ahci_sata_layers_i/phy/was_rst_i_1/O
                         net (fo=278, routed)         8.838    13.162    sata_top/ahci_sata_layers_i/dbg_was_link5_i/sata_reset_done_r_reg[0]
    SLICE_X40Y161        FDCE                                         f  sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)   13.333    13.333 r  
    SLICE_X65Y43         FDRE                         0.000    13.333 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.389    14.722    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.113    14.835 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.402    16.237    sata_top/ahci_sata_layers_i/dbg_was_link5_i/usrclk2_r_reg
    SLICE_X40Y161        FDCE                                         r  sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg/C
                         clock pessimism              0.255    16.492    
                         clock uncertainty           -0.035    16.456    
    SLICE_X40Y161        FDCE (Recov_fdce_C_CLR)     -0.255    16.201    sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         16.201    
                         arrival time                         -13.162    
  -------------------------------------------------------------------
                         slack                                  3.039    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.785ns  (arrival time - required time)
  Source:                 sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/C
                            (rising edge-triggered cell FDRE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Destination:            sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/CLR
                            (removal check against rising-edge clock usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (usrclk2 rise@0.000ns - usrclk2 rise@0.000ns)
  Data Path Delay:        0.730ns  (logic 0.128ns (17.534%)  route 0.602ns (82.466%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.607ns
    Source Clock Delay      (SCD):    1.267ns
    Clock Pessimism Removal (CPR):    0.326ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X65Y43         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           0.718     0.718    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.026     0.744 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.523     1.267    sata_top/ahci_top_i/ahci_dma_i/usrclk2_r_reg
    SLICE_X41Y128        FDRE                                         r  sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y128        FDRE (Prop_fdre_C_Q)         0.100     1.367 f  sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/Q
                         net (fo=18, routed)          0.215     1.582    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/abort_busy_mclk_reg
    SLICE_X40Y124        LUT2 (Prop_lut2_I0_O)        0.028     1.610 f  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/dout_vld_r[1]_i_1/O
                         net (fo=15, routed)          0.387     1.997    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/abort_busy_mclk_reg
    SLICE_X40Y130        FDCE                                         f  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X65Y43         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           0.848     0.848    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.030     0.878 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.729     1.607    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/usrclk2_r_reg
    SLICE_X40Y130        FDCE                                         r  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/C
                         clock pessimism             -0.326     1.281    
    SLICE_X40Y130        FDCE (Remov_fdce_C_CLR)     -0.069     1.212    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -1.212    
                         arrival time                           1.997    
  -------------------------------------------------------------------
                         slack                                  0.785    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  xclk
  To Clock:  xclk

Setup :            0  Failing Endpoints,  Worst Slack        0.821ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.388ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.821ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            4.167ns  (xclk rise@4.167ns - xclk rise@0.000ns)
  Data Path Delay:        2.856ns  (logic 0.269ns (9.419%)  route 2.587ns (90.581%))
  Logic Levels:           0  
  Clock Path Skew:        -0.231ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.128ns = ( 9.295 - 4.167 ) 
    Source Clock Delay      (SCD):    5.614ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Uncertainty:      0.067ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.114ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           2.009     3.904    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13488, routed)       1.590     5.614    sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/pwrdwn_clk_reg[0]
    SLICE_X61Y44         FDRE                                         r  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y44         FDRE (Prop_fdre_C_Q)         0.269     5.883 f  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=116, routed)         2.587     8.470    compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/regs_reg[1][0]
    SLICE_X18Y57         FDCE                                         f  compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       4.167     4.167 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     4.167 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     5.839    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.083     5.922 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.911     7.833    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.113     7.946 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13488, routed)       1.349     9.295    compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/xclk
    SLICE_X18Y57         FDCE                                         r  compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/in_reg_reg/C
                         clock pessimism              0.255     9.550    
                         clock uncertainty           -0.067     9.482    
    SLICE_X18Y57         FDCE (Recov_fdce_C_CLR)     -0.192     9.290    compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                          9.290    
                         arrival time                          -8.470    
  -------------------------------------------------------------------
                         slack                                  0.821    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.388ns  (arrival time - required time)
  Source:                 sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_macroblock_buf_iface_i/multipulse_cross_clock_i/pulse_cross_clock_i/busy_r_reg/CLR
                            (removal check against rising-edge clock xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (xclk rise@0.000ns - xclk rise@0.000ns)
  Data Path Delay:        0.332ns  (logic 0.100ns (30.141%)  route 0.232ns (69.859%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.625ns
    Source Clock Delay      (SCD):    2.098ns
    Clock Pessimism Removal (CPR):    0.514ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.771     1.478    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13488, routed)       0.594     2.098    sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/pwrdwn_clk_reg[0]
    SLICE_X61Y44         FDRE                                         r  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y44         FDRE (Prop_fdre_C_Q)         0.100     2.198 f  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=116, routed)         0.232     2.430    compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_macroblock_buf_iface_i/multipulse_cross_clock_i/pulse_cross_clock_i/Q[0]
    SLICE_X60Y40         FDCE                                         f  compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_macroblock_buf_iface_i/multipulse_cross_clock_i/pulse_cross_clock_i/busy_r_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.840     1.782    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13488, routed)       0.813     2.625    compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_macroblock_buf_iface_i/multipulse_cross_clock_i/pulse_cross_clock_i/xclk
    SLICE_X60Y40         FDCE                                         r  compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_macroblock_buf_iface_i/multipulse_cross_clock_i/pulse_cross_clock_i/busy_r_reg/C
                         clock pessimism             -0.514     2.111    
    SLICE_X60Y40         FDCE (Remov_fdce_C_CLR)     -0.069     2.042    compressor393_i/cmprs_channel_block[3].jp_channel_i/cmprs_macroblock_buf_iface_i/multipulse_cross_clock_i/pulse_cross_clock_i/busy_r_reg
  -------------------------------------------------------------------
                         required time                         -2.042    
                         arrival time                           2.430    
  -------------------------------------------------------------------
                         slack                                  0.388