[*] [*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI [*] Sun Mar 1 04:57:51 2015 [*] [dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150228214141868.lxt" [dumpfile_mtime] "Sun Mar 1 04:56:21 2015" [dumpfile_size] 860951462 [savefile] "/home/andrey/git/x393/x393_testbench01.sav" [timestart] 0 [size] 1823 1180 [pos] 2062 0 *-24.698502 12942500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] x393_testbench01. [treeopen] x393_testbench01.x393_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_deser_32bit_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_deser_32bit_i.genblk4. [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4. [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4. [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4. [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i. [treeopen] x393_testbench01.x393_i.mcntrl393_test01_i. [treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i. [sst_width] 373 [signals_width] 465 [sst_expanded] 1 [sst_vpaned_height] 631 @800200 -top_simulation @28 x393_testbench01.CLK[0] x393_testbench01.WAITING_STATUS[0] x393_testbench01.AXI_RD_EMPTY[0] x393_testbench01.SIMUL_AXI_EMPTY[0] x393_testbench01.SIMUL_AXI_FULL[0] @22 x393_testbench01.SIMUL_AXI_ADDR[15:0] x393_testbench01.SIMUL_AXI_READ[31:0] @c00200 -top_extra @22 x393_testbench01.NUM_WORDS_READ[31:0] x393_testbench01.NUM_WORDS_EXPECTED[31:0] @28 x393_testbench01.rstb[0] @22 x393_testbench01.rdata[31:0] x393_testbench01.SIMUL_AXI_ADDR_W[15:0] @c00022 x393_testbench01.registered_rdata[31:0] @28 (0)x393_testbench01.registered_rdata[31:0] (1)x393_testbench01.registered_rdata[31:0] (2)x393_testbench01.registered_rdata[31:0] (3)x393_testbench01.registered_rdata[31:0] (4)x393_testbench01.registered_rdata[31:0] (5)x393_testbench01.registered_rdata[31:0] (6)x393_testbench01.registered_rdata[31:0] (7)x393_testbench01.registered_rdata[31:0] (8)x393_testbench01.registered_rdata[31:0] (9)x393_testbench01.registered_rdata[31:0] (10)x393_testbench01.registered_rdata[31:0] (11)x393_testbench01.registered_rdata[31:0] (12)x393_testbench01.registered_rdata[31:0] (13)x393_testbench01.registered_rdata[31:0] (14)x393_testbench01.registered_rdata[31:0] (15)x393_testbench01.registered_rdata[31:0] (16)x393_testbench01.registered_rdata[31:0] (17)x393_testbench01.registered_rdata[31:0] (18)x393_testbench01.registered_rdata[31:0] (19)x393_testbench01.registered_rdata[31:0] (20)x393_testbench01.registered_rdata[31:0] (21)x393_testbench01.registered_rdata[31:0] (22)x393_testbench01.registered_rdata[31:0] (23)x393_testbench01.registered_rdata[31:0] (24)x393_testbench01.registered_rdata[31:0] (25)x393_testbench01.registered_rdata[31:0] (26)x393_testbench01.registered_rdata[31:0] (27)x393_testbench01.registered_rdata[31:0] (28)x393_testbench01.registered_rdata[31:0] (29)x393_testbench01.registered_rdata[31:0] (30)x393_testbench01.registered_rdata[31:0] (31)x393_testbench01.registered_rdata[31:0] @1401200 -group_end @22 x393_testbench01.read_and_wait_status.address[7:0] x393_testbench01.x393_i.status_rdata[31:0] @c00022 x393_testbench01.x393_i.axird_rdata[31:0] @28 (0)x393_testbench01.x393_i.axird_rdata[31:0] (1)x393_testbench01.x393_i.axird_rdata[31:0] (2)x393_testbench01.x393_i.axird_rdata[31:0] (3)x393_testbench01.x393_i.axird_rdata[31:0] (4)x393_testbench01.x393_i.axird_rdata[31:0] (5)x393_testbench01.x393_i.axird_rdata[31:0] (6)x393_testbench01.x393_i.axird_rdata[31:0] (7)x393_testbench01.x393_i.axird_rdata[31:0] (8)x393_testbench01.x393_i.axird_rdata[31:0] (9)x393_testbench01.x393_i.axird_rdata[31:0] (10)x393_testbench01.x393_i.axird_rdata[31:0] (11)x393_testbench01.x393_i.axird_rdata[31:0] (12)x393_testbench01.x393_i.axird_rdata[31:0] (13)x393_testbench01.x393_i.axird_rdata[31:0] (14)x393_testbench01.x393_i.axird_rdata[31:0] (15)x393_testbench01.x393_i.axird_rdata[31:0] (16)x393_testbench01.x393_i.axird_rdata[31:0] (17)x393_testbench01.x393_i.axird_rdata[31:0] (18)x393_testbench01.x393_i.axird_rdata[31:0] (19)x393_testbench01.x393_i.axird_rdata[31:0] (20)x393_testbench01.x393_i.axird_rdata[31:0] (21)x393_testbench01.x393_i.axird_rdata[31:0] (22)x393_testbench01.x393_i.axird_rdata[31:0] (23)x393_testbench01.x393_i.axird_rdata[31:0] (24)x393_testbench01.x393_i.axird_rdata[31:0] (25)x393_testbench01.x393_i.axird_rdata[31:0] (26)x393_testbench01.x393_i.axird_rdata[31:0] (27)x393_testbench01.x393_i.axird_rdata[31:0] (28)x393_testbench01.x393_i.axird_rdata[31:0] (29)x393_testbench01.x393_i.axird_rdata[31:0] (30)x393_testbench01.x393_i.axird_rdata[31:0] (31)x393_testbench01.x393_i.axird_rdata[31:0] @1401200 -group_end @22 x393_testbench01.target_phase[7:0] x393_testbench01.read_and_wait_status.address[7:0] @28 x393_testbench01.x393_i.status_selected[0] x393_testbench01.x393_i.mcntrl_axird_selected[0] @22 x393_testbench01.x393_i.mcntrl_axird_rdata[31:0] @200 - @28 x393_testbench01.x393_i.axird_start_burst[0] x393_testbench01.x393_i.axird_ren[0] x393_testbench01.x393_i.axird_regen[0] @1401200 -top_extra @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mclk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_page_nxt[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rpage_nxt[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_wpage_nxt[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_run0[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_run2[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_run3[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_wr_chn4[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_run4[0] @200 - @c00200 -read_block_buf_chn @22 x393_testbench01.read_block_buf_chn.num_read[31:0] @28 x393_testbench01.read_block_buf_chn.page[1:0] @22 x393_testbench01.read_block_buf_chn.start_addr[29:0] @1401200 -read_block_buf_chn @c00200 -simul_axi_read @28 x393_testbench01.simul_axi_read_i.burst[0] x393_testbench01.simul_axi_read_i.burst_r[0] x393_testbench01.simul_axi_read_i.clk[0] x393_testbench01.simul_axi_read_i.data_stb[0] x393_testbench01.simul_axi_read_i.err_out[0] x393_testbench01.simul_axi_read_i.error_w[0] x393_testbench01.simul_axi_read_i.fifo_in_rdy[0] x393_testbench01.simul_axi_read_i.fifo_valid[0] x393_testbench01.simul_axi_read_i.generated_last[0] x393_testbench01.simul_axi_read_i.last[0] @22 x393_testbench01.simul_axi_read_i.left_plus_1[3:0] @28 x393_testbench01.simul_axi_read_i.rcmd[0] x393_testbench01.simul_axi_read_i.reset[0] @22 x393_testbench01.simul_axi_read_i.rlen[3:0] x393_testbench01.simul_axi_read_i.rlen_fifo[3:0] @28 x393_testbench01.simul_axi_read_i.start_burst[0] @1401200 -simul_axi_read @c00200 -WAIT_STATUS_CONDITION -write_control_reg @22 x393_testbench01.write_contol_register.data[31:0] x393_testbench01.write_contol_register.reg_addr[29:0] @1401200 -write_control_reg @22 x393_testbench01.registered_rdata[31:0] @28 x393_testbench01.wait_status_condition.invert_match[0] @22 x393_testbench01.wait_status_condition.mask[25:0] @28 x393_testbench01.wait_status_condition.match[0] @22 x393_testbench01.wait_status_condition.pattern[25:0] x393_testbench01.wait_status_condition.seq_num[5:0] x393_testbench01.wait_status_condition.status_address[7:0] x393_testbench01.wait_status_condition.status_control_address[29:0] @28 x393_testbench01.wait_status_condition.status_mode[1:0] @1401200 -WAIT_STATUS_CONDITION @1000200 -top_simulation @c00200 -axi @28 x393_testbench01.x393_i.axi_aclk[0] @22 x393_testbench01.x393_i.axi_araddr[31:0] @28 x393_testbench01.x393_i.axi_arburst[1:0] @22 x393_testbench01.x393_i.axi_arid[11:0] x393_testbench01.x393_i.axi_arlen[3:0] @28 x393_testbench01.x393_i.axi_arready[0] x393_testbench01.x393_i.axi_arsize[1:0] x393_testbench01.x393_i.axi_arvalid[0] @22 x393_testbench01.x393_i.axi_awaddr[31:0] @28 x393_testbench01.x393_i.axi_awburst[1:0] @22 x393_testbench01.x393_i.axi_awid[11:0] x393_testbench01.x393_i.axi_awlen[3:0] @28 x393_testbench01.x393_i.axi_awready[0] x393_testbench01.x393_i.axi_awsize[1:0] x393_testbench01.x393_i.axi_awvalid[0] @22 x393_testbench01.x393_i.axi_bid[11:0] @28 x393_testbench01.x393_i.axi_bready[0] x393_testbench01.x393_i.axi_bresp[1:0] x393_testbench01.x393_i.axi_bvalid[0] @22 x393_testbench01.x393_i.axi_rdata[31:0] x393_testbench01.x393_i.axi_rid[11:0] @28 x393_testbench01.x393_i.axi_rlast[0] x393_testbench01.x393_i.axi_rready[0] x393_testbench01.x393_i.axi_rresp[1:0] x393_testbench01.x393_i.axi_rst[0] x393_testbench01.x393_i.axi_rst_pre[0] x393_testbench01.x393_i.axi_rvalid[0] @22 x393_testbench01.x393_i.axi_wdata[31:0] x393_testbench01.x393_i.axi_wid[11:0] @28 x393_testbench01.x393_i.axi_wlast[0] x393_testbench01.x393_i.axi_wready[0] @22 x393_testbench01.x393_i.axi_wstb[3:0] @28 x393_testbench01.x393_i.axi_wvalid[0] x393_testbench01.x393_i.axird_bram_rclk[0] x393_testbench01.x393_i.axird_dev_busy[0] x393_testbench01.x393_i.axird_dev_ready[0] @22 x393_testbench01.x393_i.axird_rdata[31:0] @28 x393_testbench01.x393_i.axird_regen[0] x393_testbench01.x393_i.axird_ren[0] x393_testbench01.x393_i.axird_start_burst[0] @22 x393_testbench01.x393_i.axiwr_bram_wstb[3:0] @28 x393_testbench01.x393_i.axiwr_dev_busy[0] x393_testbench01.x393_i.axiwr_dev_ready[0] x393_testbench01.x393_i.axiwr_start_burst[0] x393_testbench01.x393_i.axiwr_wclk[0] @22 x393_testbench01.x393_i.axiwr_wdata[31:0] @28 x393_testbench01.x393_i.axiwr_wen[0] @1401200 -axi @c00200 -cmd_mux @22 x393_testbench01.x393_i.cmd_root_ad[7:0] @28 x393_testbench01.x393_i.cmd_root_stb[0] x393_testbench01.x393_i.cmd_mux_i.ad_stb[0] x393_testbench01.x393_i.cmd_mux_i.ad_stb_r[0] x393_testbench01.x393_i.cmd_mux_i.axi_clk[0] x393_testbench01.x393_i.cmd_mux_i.busy[0] x393_testbench01.x393_i.cmd_mux_i.busy_r[0] @22 x393_testbench01.x393_i.cmd_mux_i.byte_ad[7:0] @28 x393_testbench01.x393_i.cmd_mux_i.can_start_w[0] x393_testbench01.x393_i.cmd_mux_i.cmdseq_full_r[0] x393_testbench01.x393_i.cmd_mux_i.cseq_ackn[0] @22 x393_testbench01.x393_i.cmd_mux_i.cseq_wdata[31:0] x393_testbench01.x393_i.cmd_mux_i.cseq_wdata_r[31:0] @28 x393_testbench01.x393_i.cmd_mux_i.cseq_wr_en[0] x393_testbench01.x393_i.cmd_mux_i.fifo_half_empty[0] x393_testbench01.x393_i.cmd_mux_i.fifo_nempty[0] x393_testbench01.x393_i.cmd_mux_i.mclk[0] @22 x393_testbench01.x393_i.cmd_mux_i.par_ad[47:0] x393_testbench01.x393_i.cmd_mux_i.par_data[31:0] @28 x393_testbench01.x393_i.cmd_mux_i.rst[0] x393_testbench01.x393_i.cmd_mux_i.selected[0] x393_testbench01.x393_i.cmd_mux_i.selected_w[0] @800022 x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0] @28 (0)x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0] (1)x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0] (2)x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0] (3)x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0] (4)x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0] @1001200 -group_end @22 x393_testbench01.x393_i.cmd_mux_i.seq_length[3:0] x393_testbench01.x393_i.cmd_mux_i.seq_length_rom_a[3:0] @28 x393_testbench01.x393_i.cmd_mux_i.ss[0] x393_testbench01.x393_i.cmd_mux_i.start_axi_w[0] x393_testbench01.x393_i.cmd_mux_i.start_w[0] x393_testbench01.x393_i.cmd_mux_i.start_wburst[0] @22 x393_testbench01.x393_i.cmd_mux_i.wdata[31:0] x393_testbench01.x393_i.cmd_mux_i.wdata_fifo_out[31:0] @28 x393_testbench01.x393_i.cmd_mux_i.wr_en[0] @1401200 -cmd_mux @c00200 -status_read @22 x393_testbench01.x393_i.status_read_i.ad[7:0] @28 x393_testbench01.x393_i.status_read_i.axi_clk[0] @22 x393_testbench01.x393_i.status_read_i.axi_status_rdata[31:0] x393_testbench01.x393_i.status_read_i.axi_status_rdata_r[31:0] x393_testbench01.x393_i.status_read_i.axird_raddr[7:0] x393_testbench01.x393_i.status_read_i.axird_rdata[31:0] @28 x393_testbench01.x393_i.status_read_i.axird_regen[0] x393_testbench01.x393_i.status_read_i.axird_ren[0] x393_testbench01.x393_i.status_read_i.axird_selected[0] x393_testbench01.x393_i.status_read_i.axird_start_burst[0] x393_testbench01.x393_i.status_read_i.clk[0] @22 x393_testbench01.x393_i.status_read_i.dstb[3:0] @28 x393_testbench01.x393_i.status_read_i.rd[0] x393_testbench01.x393_i.status_read_i.regen[0] x393_testbench01.x393_i.status_read_i.rq[0] x393_testbench01.x393_i.status_read_i.rq_r[0] x393_testbench01.x393_i.status_read_i.rst[0] x393_testbench01.x393_i.status_read_i.select_d[0] x393_testbench01.x393_i.status_read_i.select_r[0] x393_testbench01.x393_i.status_read_i.select_w[0] x393_testbench01.x393_i.status_read_i.start[0] @22 x393_testbench01.x393_i.status_read_i.waddr[7:0] x393_testbench01.x393_i.status_read_i.wdata[31:0] @28 x393_testbench01.x393_i.status_read_i.we[0] @1401200 -status_read @c00200 -status_router_top @28 x393_testbench01.x393_i.status_router2_top_i.chn_sel_w[0] x393_testbench01.x393_i.status_router2_top_i.current_chn_r[0] x393_testbench01.x393_i.status_router2_top_i.clk[0] x393_testbench01.x393_i.status_router2_top_i.rq_in0[0] x393_testbench01.x393_i.status_router2_top_i.start_in0[0] @22 x393_testbench01.x393_i.status_router2_top_i.db_in0[7:0] @28 x393_testbench01.x393_i.status_router2_top_i.rq_in1[0] x393_testbench01.x393_i.status_router2_top_i.start_in1[0] @22 x393_testbench01.x393_i.status_router2_top_i.db_in1[7:0] @28 x393_testbench01.x393_i.status_router2_top_i.rq_out[0] x393_testbench01.x393_i.status_router2_top_i.start_out[0] @22 x393_testbench01.x393_i.status_router2_top_i.db_out[7:0] @28 x393_testbench01.x393_i.status_router2_top_i.early_chn[0] @22 x393_testbench01.x393_i.status_router2_top_i.fifo0_out[7:0] x393_testbench01.x393_i.status_router2_top_i.fifo1_out[7:0] @800028 x393_testbench01.x393_i.status_router2_top_i.fifo_half_full[1:0] @28 (0)x393_testbench01.x393_i.status_router2_top_i.fifo_half_full[1:0] (1)x393_testbench01.x393_i.status_router2_top_i.fifo_half_full[1:0] @1001200 -group_end @28 x393_testbench01.x393_i.status_router2_top_i.fifo_last_byte[1:0] x393_testbench01.x393_i.status_router2_top_i.fifo_nempty[1:0] x393_testbench01.x393_i.status_router2_top_i.fifo_re[1:0] x393_testbench01.x393_i.status_router2_top_i.next_chn[0] @800028 x393_testbench01.x393_i.status_router2_top_i.rcv_rest_r[1:0] @28 (0)x393_testbench01.x393_i.status_router2_top_i.rcv_rest_r[1:0] (1)x393_testbench01.x393_i.status_router2_top_i.rcv_rest_r[1:0] @1001200 -group_end @c00028 x393_testbench01.x393_i.status_router2_top_i.rq_in[1:0] @28 (0)x393_testbench01.x393_i.status_router2_top_i.rq_in[1:0] (1)x393_testbench01.x393_i.status_router2_top_i.rq_in[1:0] @1401200 -group_end @28 x393_testbench01.x393_i.status_router2_top_i.rst[0] x393_testbench01.x393_i.status_router2_top_i.snd_last_byte[0] x393_testbench01.x393_i.status_router2_top_i.snd_pre_start[0] x393_testbench01.x393_i.status_router2_top_i.snd_rest_r[0] @800028 x393_testbench01.x393_i.status_router2_top_i.start_rcv[1:0] @28 (0)x393_testbench01.x393_i.status_router2_top_i.start_rcv[1:0] (1)x393_testbench01.x393_i.status_router2_top_i.start_rcv[1:0] @1001200 -group_end @1401200 -status_router_top @c00200 -status_router16_mctrl_top @28 x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in0[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in1[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in2[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in3[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in4[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in5[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in6[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in7[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in8[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in9[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in10[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in11[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in12[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in13[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in14[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_in15[7:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.db_out[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in0[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in1[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in2[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in3[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in4[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in5[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in6[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in7[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in8[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in9[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in10[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in11[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in12[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in13[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in14[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_in15[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_int[1:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rq_out[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.rst[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in0[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in1[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in2[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in3[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in4[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in5[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in6[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in7[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in8[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in9[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in10[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in11[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in12[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in13[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in14[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_in15[0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_int[1:0] x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_out[0] @1401200 -status_router16_mctrl_top @c00200 -memcntrl16_status_router2_top @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.chn_sel_w[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.current_chn_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.early_chn[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.clk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rq_in0[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.start_in0[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.db_in0[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rq_in1[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.start_in1[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.db_in1[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rq_out[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.start_out[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.db_out[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.snd_last_byte[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.snd_rest_r[0] (1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty_pre[1:0] (0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty_pre[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo0_out[7:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo1_out[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_half_full[1:0] @800028 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_last_byte[1:0] @28 (0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_last_byte[1:0] (1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_last_byte[1:0] @1001200 -group_end @800028 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty[1:0] @28 (0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty[1:0] (1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty[1:0] @1001200 -group_end @800028 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty_pre[1:0] @1001200 -group_end @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_re[1:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.next_chn[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rcv_rest_r[1:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rq_in[1:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rst[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.snd_pre_start[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.start_rcv[1:0] @1401200 -memcntrl16_status_router2_top @c00200 -mcontr_sequencer_status_generate @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.dly_ready[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.dci_ready[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.locked_mmcm[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.locked_pll[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_busy[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.locked[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ps_rdy[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ps_out[7:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.ad[7:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.aligned_status[17:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.clk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.cmd_pend[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.data[23:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.mode[1:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.mode_w[1:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.need_to_send[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.rq[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.rq_r[2:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.rst[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.seq[5:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.snd_rest[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.start[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.status[14:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.status_changed_r[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.status_r[14:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.wd[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.we[0] @1401200 -mcontr_sequencer_status_generate @c00200 -mcontr_cmd_deser_16bit @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.addr[2:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.data[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.rst[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.stb[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.we[0] @1401200 -mcontr_cmd_deser_16bit @c00200 -mcont_cmd_deser_16bit_multi @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.addr[2:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.data[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.deser_r[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.match_high[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.match_low[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.rst[0] @800028 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.sr[2:0] @28 (0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.sr[2:0] (1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.sr[2:0] (2)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.sr[2:0] @1001200 -group_end @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.stb[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.stb_d[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.we[0] @1401200 -mcont_cmd_deser_16bit_multi @c00200 -test01_status_router4 @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.clk[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_in0[7:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_in1[7:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_in2[7:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_in3[7:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_out[7:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_in0[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_in1[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_in2[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_in3[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_int[1:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_out[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rst[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_in0[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_in1[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_in2[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_in3[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_int[1:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_out[0] @1401200 -test01_status_router4 @c00200 -test01_status_router2_top @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.clk[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rq_in[1:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rq_in0[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.start_in0[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rq_in1[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.start_in1[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rq_out[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.chn_sel_w[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.start_out[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.current_chn_r[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.db_in0[7:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.db_in1[7:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.db_out[7:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.early_chn[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo0_out[7:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo1_out[7:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_half_full[1:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_last_byte[1:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_nempty[1:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_nempty_pre[1:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_re[1:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.next_chn[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rcv_rest_r[1:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rst[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.set_other_only_w[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.snd_last_byte[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.snd_pre_start[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.snd_rest_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.start_rcv[1:0] @1401200 -test01_status_router2_top @c00200 -test01_status_router2_01 @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.chn_sel_w[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.clk[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.current_chn_r[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.db_in0[7:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.db_in1[7:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.db_out[7:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.early_chn[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo0_out[7:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo1_out[7:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_half_full[1:0] @800028 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_last_byte[1:0] @28 (0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_last_byte[1:0] (1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_last_byte[1:0] @1001200 -group_end @800028 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty[1:0] @28 (0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty[1:0] (1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty[1:0] @1001200 -group_end @800028 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty_pre[1:0] @28 (0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty_pre[1:0] (1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty_pre[1:0] @1001200 -group_end @800028 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_re[1:0] @28 (0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_re[1:0] (1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_re[1:0] @1001200 -group_end @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.next_chn[0] @800028 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rcv_rest_r[1:0] @28 (0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rcv_rest_r[1:0] (1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rcv_rest_r[1:0] @1001200 -group_end @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in0[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in1[0] @800028 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in[1:0] @28 (0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in[1:0] (1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in[1:0] @1001200 -group_end @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_out[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rst[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.set_other_only_w[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.snd_last_byte[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.snd_pre_start[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.snd_rest_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_in0[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_in1[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_out[0] @800028 x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_rcv[1:0] @28 (0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_rcv[1:0] (1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_rcv[1:0] @1001200 -group_end @1401200 -test01_status_router2_01 @c00200 -axibram_read @28 x393_testbench01.x393_i.axibram_read_i.aclk[0] x393_testbench01.x393_i.axibram_read_i.ar_half_full[0] x393_testbench01.x393_i.axibram_read_i.ar_nempty[0] @22 x393_testbench01.x393_i.axibram_read_i.araddr[31:0] @28 x393_testbench01.x393_i.axibram_read_i.arburst[1:0] x393_testbench01.x393_i.axibram_read_i.arburst_out[1:0] @22 x393_testbench01.x393_i.axibram_read_i.arid[11:0] x393_testbench01.x393_i.axibram_read_i.arid_out[11:0] x393_testbench01.x393_i.axibram_read_i.arlen[3:0] x393_testbench01.x393_i.axibram_read_i.arlen_out[3:0] @28 x393_testbench01.x393_i.axibram_read_i.arready[0] x393_testbench01.x393_i.axibram_read_i.arsize[1:0] x393_testbench01.x393_i.axibram_read_i.arsize_out[1:0] x393_testbench01.x393_i.axibram_read_i.arvalid[0] x393_testbench01.x393_i.axibram_read_i.bram_rclk[0] @22 x393_testbench01.x393_i.axibram_read_i.bram_rdata[31:0] @28 x393_testbench01.x393_i.axibram_read_i.bram_reg_re_0[0] x393_testbench01.x393_i.axibram_read_i.bram_reg_re_w[0] x393_testbench01.x393_i.axibram_read_i.bram_regen[0] x393_testbench01.x393_i.axibram_read_i.bram_ren[0] x393_testbench01.x393_i.axibram_read_i.dev_ready[0] x393_testbench01.x393_i.axibram_read_i.last_in_burst_0[0] x393_testbench01.x393_i.axibram_read_i.last_in_burst_1[0] x393_testbench01.x393_i.axibram_read_i.last_in_burst_d_w[0] x393_testbench01.x393_i.axibram_read_i.last_in_burst_w[0] x393_testbench01.x393_i.axibram_read_i.pre_last_in_burst_r[0] x393_testbench01.x393_i.axibram_read_i.pre_left_zero_w[0] @22 x393_testbench01.x393_i.axibram_read_i.pre_rid0[11:0] x393_testbench01.x393_i.axibram_read_i.pre_rid[11:0] @28 x393_testbench01.x393_i.axibram_read_i.pre_rvalid_w[0] x393_testbench01.x393_i.axibram_read_i.rburst[1:0] @22 x393_testbench01.x393_i.axibram_read_i.rdata[31:0] @28 x393_testbench01.x393_i.axibram_read_i.read_in_progress[0] x393_testbench01.x393_i.axibram_read_i.read_in_progress_d[0] x393_testbench01.x393_i.axibram_read_i.read_in_progress_d_w[0] x393_testbench01.x393_i.axibram_read_i.read_in_progress_or[0] x393_testbench01.x393_i.axibram_read_i.read_in_progress_w[0] @22 x393_testbench01.x393_i.axibram_read_i.read_left[3:0] x393_testbench01.x393_i.axibram_read_i.rid[11:0] @28 x393_testbench01.x393_i.axibram_read_i.rlast[0] @22 x393_testbench01.x393_i.axibram_read_i.rlen[3:0] @28 x393_testbench01.x393_i.axibram_read_i.rready[0] x393_testbench01.x393_i.axibram_read_i.rresp[1:0] x393_testbench01.x393_i.axibram_read_i.rst[0] x393_testbench01.x393_i.axibram_read_i.rvalid[0] x393_testbench01.x393_i.axibram_read_i.start_burst[0] x393_testbench01.x393_i.axibram_read_i.start_read_burst_0[0] x393_testbench01.x393_i.axibram_read_i.start_read_burst_1[0] x393_testbench01.x393_i.axibram_read_i.start_read_burst_w[0] @200 - @28 x393_testbench01.x393_i.axibram_read_i.dev_ready[0] x393_testbench01.x393_i.axibram_read_i.read_in_progress[0] x393_testbench01.x393_i.axibram_read_i.read_in_progress_d[0] x393_testbench01.x393_i.axibram_read_i.read_in_progress_or[0] @200 - @28 x393_testbench01.x393_i.axibram_read_i.bram_reg_re_w[0] x393_testbench01.x393_i.axibram_read_i.pre_last_in_burst_r[0] x393_testbench01.x393_i.axibram_read_i.bram_ren[0] x393_testbench01.x393_i.axibram_read_i.bram_regen[0] @200 - @28 x393_testbench01.x393_i.axibram_read_i.read_in_progress[0] x393_testbench01.x393_i.axibram_read_i.bram_ren[0] @200 - @1401200 -axibram_read @c00200 -refresh @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.sel_refresh_w[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_seq_w[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.sequencer_run_busy[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.clk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.cry[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.en[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.en_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.en_refresh[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.grant[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.need[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.over[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.pending_rq[4:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.period_cntr[7:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.pre_div[3:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.refresh_due[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.refresh_period[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.rst[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.set[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.want[0] @1401200 -refresh @800200 -DDR3 @28 x393_testbench01.x393_i.SDRST[0] x393_testbench01.x393_i.SDCKE[0] x393_testbench01.x393_i.SDCLK[0] @22 x393_testbench01.x393_i.SDA[14:0] x393_testbench01.x393_i.SDBA[2:0] @28 x393_testbench01.x393_i.SDRAS[0] x393_testbench01.x393_i.SDCAS[0] x393_testbench01.x393_i.SDWE[0] x393_testbench01.x393_i.DQSL[0] x393_testbench01.x393_i.DQSU[0] x393_testbench01.x393_i.NDQSL[0] x393_testbench01.x393_i.NDQSU[0] x393_testbench01.x393_i.SDDML[0] x393_testbench01.x393_i.SDDMU[0] @22 x393_testbench01.x393_i.SDD[15:0] x393_testbench01.x393_i.SDODT[0] @1000200 -DDR3 @c00200 -mcntrl393_test01 @22 x393_testbench01.x393_i.mcntrl393_test01_i.cmd_a[3:0] x393_testbench01.x393_i.mcntrl393_test01_i.cmd_ad[7:0] x393_testbench01.x393_i.mcntrl393_test01_i.cmd_data[7:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.cmd_frame_start_w[0] x393_testbench01.x393_i.mcntrl393_test01_i.cmd_next_page_w[0] x393_testbench01.x393_i.mcntrl393_test01_i.cmd_stb[0] x393_testbench01.x393_i.mcntrl393_test01_i.cmd_suspend_w[0] x393_testbench01.x393_i.mcntrl393_test01_i.cmd_we[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn2[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn3[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn4[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn2[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn3[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn4[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn2[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn2_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn3[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn3_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn4[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn4_r[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn2[15:0] x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn3[15:0] x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn4[15:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.mclk[0] x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn2[0] x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn2_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn3[0] x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn3_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn4[0] x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn4_r[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.page_chn2[3:0] x393_testbench01.x393_i.mcntrl393_test01_i.page_chn3[3:0] x393_testbench01.x393_i.mcntrl393_test01_i.page_chn4[3:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn2[0] x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn3[0] x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn4[0] x393_testbench01.x393_i.mcntrl393_test01_i.rst[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.status_ad[7:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2[21:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2_ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2_rq[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2_start[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3_ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3_rq[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3_start[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4[21:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4_ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4_rq[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4_start[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_rq[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_start[0] x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn2[0] x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn2_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn3[0] x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn3_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4[0] x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4_r[0] @1401200 -mcntrl393_test01 @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_rd[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ext_buf_rd[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ext_buf_rrun[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rd_cur[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rd[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.sequence_done[0] @200 - - @c00200 -test01 @22 x393_testbench01.x393_i.mcntrl393_test01_i.cmd_a[3:0] x393_testbench01.x393_i.mcntrl393_test01_i.cmd_ad[7:0] x393_testbench01.x393_i.mcntrl393_test01_i.cmd_data[7:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.cmd_frame_start_w[0] x393_testbench01.x393_i.mcntrl393_test01_i.cmd_next_page_w[0] x393_testbench01.x393_i.mcntrl393_test01_i.cmd_stb[0] x393_testbench01.x393_i.mcntrl393_test01_i.cmd_suspend_w[0] x393_testbench01.x393_i.mcntrl393_test01_i.cmd_we[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn1[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn2[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn3[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn4[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn1[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn2[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn3[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn4[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_finished_chn1[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_finished_chn2[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_finished_chn3[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_finished_chn4[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn1[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn1_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn2[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn2_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn3[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn3_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn4[0] x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn4_r[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn1[15:0] x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn2[15:0] x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn3[15:0] x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn4[15:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.mclk[0] x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn1[0] x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn1_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn2[0] x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn2_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn3[0] x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn3_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn4[0] x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn4_r[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.page_chn1[3:0] x393_testbench01.x393_i.mcntrl393_test01_i.page_chn2[3:0] x393_testbench01.x393_i.mcntrl393_test01_i.page_chn3[3:0] x393_testbench01.x393_i.mcntrl393_test01_i.page_chn4[3:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn1[0] x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn2[0] x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn3[0] x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn4[0] x393_testbench01.x393_i.mcntrl393_test01_i.rst[0] x393_testbench01.x393_i.mcntrl393_test01_i.set_chn1_mode[0] x393_testbench01.x393_i.mcntrl393_test01_i.set_chn1_status[0] x393_testbench01.x393_i.mcntrl393_test01_i.set_chn2_mode[0] x393_testbench01.x393_i.mcntrl393_test01_i.set_chn2_status[0] x393_testbench01.x393_i.mcntrl393_test01_i.set_chn3_mode[0] x393_testbench01.x393_i.mcntrl393_test01_i.set_chn3_status[0] x393_testbench01.x393_i.mcntrl393_test01_i.set_chn4_mode[0] x393_testbench01.x393_i.mcntrl393_test01_i.set_chn4_status[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.status_ad[7:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn1[21:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn1_ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_chn1_rq[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn1_start[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2[21:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2_ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2_rq[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2_start[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3_ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3_rq[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3_start[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4[21:0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4_ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4_rq[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4_start[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_rq[0] x393_testbench01.x393_i.mcntrl393_test01_i.status_start[0] x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn1[0] x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn1_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn2[0] x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn2_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn3[0] x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn3_r[0] x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4[0] x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4_r[0] @1401200 -test01 @c00201 -vivado_debug @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_div_pre[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_div[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.rst[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.sdclk_pre[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.sdclk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk[0] @200 - @1401201 -vivado_debug @200 - @c00200 -byte_lane_0 @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk_div[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dq[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dq_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dqs[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dqs_r[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din[31:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_dm[3:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_dm_r[3:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_dqs[3:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_dqs_r[3:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_r[31:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dly_addr[4:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dly_data[7:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dly_data_r[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dm[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dout[31:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_read[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.iclk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.inv_clk_div[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_delay[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_idly[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_idly_dqs[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_odly[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_odly_dm[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_odly_dqs[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ndqs[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.rst[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.set[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.set_r[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dq[3:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dq_r[3:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dqs[3:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dqs_r[3:0] @1401200 -byte_lane_0 @c00200 -index_max16 @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.index[3:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.mask[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.mask_changed[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.mask_prev[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.max0809101112131415[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.max0001020304050607[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.max0001[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.max0203[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.max0405[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.max0607[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.max0809[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.max1011[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.max1213[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.max1415[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.max00010203[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.max04050607[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.max08091011[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.max12131415[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.need_dly[3:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.need_in[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.need_out[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel0809101112131415[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel0809101112131415_r[2:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel0001020304050607[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel0001020304050607_r[2:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel0001[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel0001_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel0203[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel0203_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel0405[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel0405_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel0607[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel0607_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel0809[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel0809_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel1011[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel1011_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel1213[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel1213_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel1415[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel1415_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel00010203[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel00010203_r[1:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel04050607[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel04050607_r[1:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel08091011[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel08091011_r[1:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel12131415[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel12131415_r[1:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.sel[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.valid[0] @800022 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.valid_dly[3:0] @28 (0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.valid_dly[3:0] (1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.valid_dly[3:0] (2)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.valid_dly[3:0] (3)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.valid_dly[3:0] @1001200 -group_end @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.values[255:0] @1401200 -index_max16 @200 - @c00200 -enc4mux @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_cmd0[31:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_cmd1[31:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_cmd2[31:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_cmd3[31:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_cmd[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_done0[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_done1[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_done2[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_done3[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_wr0[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_wr1[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_wr2[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_wr3[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.enc_wr[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.rst[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.select[3:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.start0[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.start1[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.start2[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.start3[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.start[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.start_w[0] @1401200 -enc4mux @c00200 -PS_PIO -PS_PIO_STATUS @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.aligned_status[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.clk[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.cmd_pend[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.data[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.mode[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.mode_w[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.need_to_send[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.rq[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.rq_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.rst[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.seq[5:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.snd_rest[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.start[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.status[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.status_changed_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.status_r[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.wd[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.we[0] @1401200 -PS_PIO_STATUS @c00200 -PS_PIO_CHN0 -64w_32r @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32r_i.data_in[63:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32r_i.data_out[31:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32r_i.raddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32r_i.rclk[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32r_i.regen[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32r_i.ren[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32r_i.waddr[8:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32r_i.wclk[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32r_i.we[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32r_i.web[7:0] @1401200 -64w_32r @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.data_in[63:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_data_out[31:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_raddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_rd[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_regen[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.page[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.page_next[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.page_r[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.waddr[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wclk[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.we[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_in[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_set[0] @1401200 -PS_PIO_CHN0 @800200 -other_m393 @28 x393_testbench01.x393_i.mcntrl393_i.select_buf0wr_w[0] x393_testbench01.x393_i.mcntrl393_i.select_buf1wr_w[0] x393_testbench01.x393_i.mcntrl393_i.select_buf2wr_w[0] x393_testbench01.x393_i.mcntrl393_i.select_buf3wr_w[0] x393_testbench01.x393_i.mcntrl393_i.select_buf4wr_w[0] x393_testbench01.x393_i.mcntrl393_i.select_buf0wr[0] x393_testbench01.x393_i.mcntrl393_i.select_buf1wr[0] x393_testbench01.x393_i.mcntrl393_i.select_buf2wr[0] x393_testbench01.x393_i.mcntrl393_i.select_buf3wr[0] x393_testbench01.x393_i.mcntrl393_i.select_buf4wr[0] x393_testbench01.x393_i.mcntrl393_i.axiwr_wen[0] x393_testbench01.x393_i.mcntrl393_i.buf0wr_we[0] @1000200 -other_m393 @200 - @c00200 -PS_PIO_RD @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.data_in[63:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_data_out[31:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_raddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_rd[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_regen[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.page[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.page_next[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.page_r[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.waddr[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wclk[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.we[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_in[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_set[0] @1401200 -PS_PIO_RD @200 - @c00200 -PS_PIO_WR @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.data_out[63:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_data_in[31:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_waddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_we[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page_next[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page_r[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.raddr[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rclk[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rd[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.regen[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_in[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_set[0] @1401200 -PS_PIO_WR @200 - @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_rd[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_rdata[63:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_rpage_nxt[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_run[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_wdata[63:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_wpage_nxt[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_wr[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_wrun[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.busy[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.channel_pgm_en[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn_en[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn_rst[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_a[4:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_ad[7:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_data[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_half_full[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_need[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_nempty[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_out[14:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_page[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_seq_a[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_set[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_set_d[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_stb[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_wait[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_wait_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_we[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_wr[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_wr_out[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.en_page_w_set[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.en_reset[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.mclk[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.need_rq[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.nreset_page_fifo[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.nreset_page_fifo_neg[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_out[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_out_r[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_out_r_negedge[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_r_set[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_w_set_early[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_w_set_early_negedge[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_w_set_negedge[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.pending_pages[3:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port0_addr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port0_clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port0_data[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port0_re[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port0_regen[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port1_addr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port1_clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port1_data[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port1_we[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.rst[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_data[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_done[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_set[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.set_cmd_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.set_en_rst[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.set_status_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.short_busy[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.start[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_data[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_rq[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_start[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq[0] @1401200 -PS_PIO @c00200 -LINEAR_CH1 @200 - @c00200 -status_gen @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.aligned_status[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.clk[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.cmd_pend[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.data[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.mode[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.mode_w[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.need_to_send[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.rq[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.rq_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.rst[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.seq[5:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.snd_rest[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.start[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.status[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.status_changed_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.status_r[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.wd[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.we[0] @1401200 -status_gen @c00200 -chn1wr @22 x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.data_out[63:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.ext_clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.ext_data_in[31:0] x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.ext_waddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.ext_we[0] x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.page[1:0] x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.page_next[0] x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.page_r[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.raddr[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.rclk[0] x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.rd[0] x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.regen[0] x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.rpage_in[1:0] x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.rpage_set[0] @1401200 -chn1wr @800200 -chn1rd @22 x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.data_in[63:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.ext_clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.ext_data_out[31:0] x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.ext_raddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.ext_rd[0] x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.ext_regen[0] x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.page[1:0] x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.page_next[0] x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.page_r[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.waddr[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.wclk[0] x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.we[0] x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.wpage_in[1:0] x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.wpage_set[0] @1000200 -chn1rd @c00200 -encod_lin_wr @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.start[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.start_d[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.gen_run[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.jump_gen_addr[3:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.gen_addr[3:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.num128[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.cut_buf_rd[0] @800022 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_r[11:0] @28 (0)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_r[11:0] (1)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_r[11:0] (2)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_r[11:0] (3)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_r[11:0] (4)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_r[11:0] (5)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_r[11:0] (6)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_r[11:0] (7)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_r[11:0] (8)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_r[11:0] (9)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_r[11:0] (10)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_r[11:0] (11)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_r[11:0] @1001200 -group_end @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.pre_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_wr[0] @c00022 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] @28 (0)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (1)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (2)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (3)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (4)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (5)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (6)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (7)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (8)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (9)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (10)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (11)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (12)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (13)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (14)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (15)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (16)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (17)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (18)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (19)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (20)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (21)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (22)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (23)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (24)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (25)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (26)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (27)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (28)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (29)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (30)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] (31)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] @1401200 -group_end @200 - @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.bank[2:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.bank_in[2:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.clk[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.col[6:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.cut_buf_rd[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_wr[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.full_cmd[2:0] @c00022 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.gen_addr[3:0] @28 (0)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.gen_addr[3:0] (1)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.gen_addr[3:0] (2)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.gen_addr[3:0] (3)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.gen_addr[3:0] @1401200 -group_end @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.gen_run[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.jump_gen_addr[3:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.next_zero_w[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.num128[6:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.num128_in[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.pre_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_cmd[1:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_skip[1:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.row[14:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.row_in[14:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rst[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.skip_next_page[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.skip_next_page_in[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.start[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.start_col[6:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.start_d[0] @1401200 -encod_lin_wr @c00200 -encod_lin_rd @200 - @800200 -read_block_buf_chn @22 x393_testbench01.read_block_buf_chn.chn[3:0] x393_testbench01.read_block_buf_chn.num_read[31:0] @28 x393_testbench01.read_block_buf_chn.page[1:0] @22 x393_testbench01.read_block_buf_chn.start_addr[29:0] @28 x393_testbench01.read_block_buf_chn.wait_done[0] @1000200 -read_block_buf_chn @800200 -debug_buf_wpage_nxt @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_wr[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_rd[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_wr_ndly[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.mem_read_mode[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_rst[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_rst_d[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_wpage_nxt[0] x393_testbench01.x393_i.mcntrl393_i.buf_wpage_nxt_chn1[0] @1000200 -debug_buf_wpage_nxt @200 - @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.bank[2:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.bank_in[2:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.col[6:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_wr[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.full_cmd[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.gen_addr[3:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.gen_run[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.num128[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.num128_in[5:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.pre_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.rom_cmd[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.rom_r[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.rom_skip[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.row[14:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.row_in[14:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.rst[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.skip_next_page[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.skip_next_page_in[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.start[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.start_col[6:0] @1401200 -encod_lin_rd @200 - @c00200 -test_scanline_rd @22 x393_testbench01.test_scanline_read.channel[3:0] @28 x393_testbench01.test_scanline_read.extra_pages[1:0] @22 x393_testbench01.test_scanline_read.ii[31:0] x393_testbench01.test_scanline_read.mode[31:0] @28 x393_testbench01.test_scanline_read.show_data[0] @22 x393_testbench01.test_scanline_read.start_addr[29:0] x393_testbench01.test_scanline_read.status_address[7:0] x393_testbench01.test_scanline_read.status_control_address[29:0] x393_testbench01.test_scanline_read.test_mode_address[29:0] @1401200 -test_scanline_rd @c00200 -scanline_want_need @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.busy_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_start[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.next_page[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.page_cntr[2:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.pre_want[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_want[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_need[0] @1401200 -scanline_want_need @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_num128_r[6:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_deser_32bit_i.addr[3:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_stb[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_we[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.next_page[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_start[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_r[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.curr_x[12:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.next_y[16:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.curr_y[15:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_x[12:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_y[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.calc_valid[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.want_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_in_row_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_row_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.pending_xfers[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.page_cntr[2:0] x393_testbench01.x393_i.mcntrl393_i.page_ready_chn1[0] @22 x393_testbench01.x393_i.mcntrl393_test01_i.page_chn1[3:0] @200 - @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.busy_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.calc_valid[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.chn_en[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.chn_rst[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.chn_rst_d[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_a[3:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_ad[7:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_data[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_extra_pages[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_stb[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_we[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_wrmem[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.continued_xfer[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.curr_x[12:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.curr_y[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_done[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_done_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_finished[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_finished_r[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_full_width[13:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_full_width_r[13:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_start[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_x[12:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_y8_r[12:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_y[15:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.i[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_block[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_in_row[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_in_row_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_row_w[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.leftover[5:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.lim_by_xfer[6:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.line_start_addr[21:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.line_start_page_left[6:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.line_unfinished[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.lsw13_zero[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mclk[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mem_page_left[7:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mode_reg[4:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.msw_zero[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mul_rslt[21:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mul_rslt_w[26:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.need_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.next_page[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.next_y[16:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.page_cntr[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.par_mod_r[8:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.pending_xfers[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.pgm_param_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.pre_want[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.remainder_in_xfer[7:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.row_col_r[21:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.row_left[13:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.rst[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_frame_width_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_mode_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_start_addr_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_status_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_window_start_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_window_wh_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_window_x0y0_w[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.start_addr[21:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.start_addr_r[21:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.start_not_partial[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.start_x[12:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.start_y[15:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_data[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_rq[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_start[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.suspend[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.want_r[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.window_height[16:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.window_width[13:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.window_x0[12:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.window_y0[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_bank[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_col[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_done[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_done_d[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_grant[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_limited_by_mem_page[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_limited_by_mem_page_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_need[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_num128[5:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_num128_r[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_page_rst_neg[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_page_rst_pos[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_page_rst_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_page_rst_rd[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_page_rst_wr[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_partial[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_row[14:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_r[2:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_rd[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_rd_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_want[0] @1401200 -LINEAR_CH1 @c00200 -TILED_CH2 -ch2wr @22 x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.data_out[63:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.ext_clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.ext_data_in[31:0] x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.ext_waddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.ext_we[0] x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.page[1:0] x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.page_next[0] x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.page_r[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.raddr[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.rclk[0] x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.rd[0] x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.regen[0] x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.rpage_in[1:0] x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.rpage_set[0] @1401200 -ch2wr @c00200 -ch2rd @22 x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.data_in[63:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_data_out[31:0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_raddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_rd[0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_regen[0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page[1:0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page_next[0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page_r[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.waddr[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wclk[0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.we[0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wpage_in[1:0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wpage_set[0] @1401200 -ch2rd @c00200 -encod_tiled_wr @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.gen_run[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.gen_addr[3:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.rom_r[11:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.pre_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.loop_continue[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enc_cmd[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enc_wr[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enc_done[0] @200 - @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.bank[2:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.clk[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.col[6:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.col_bank[9:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enable_act[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enable_autopre[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enc_cmd[31:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enc_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enc_wr[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.first_col[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.full_cmd[2:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.gen_addr[3:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.gen_run[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.keep_open[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.keep_open_in[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.last_col[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.last_row[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.loop_continue[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.next_bank_w[2:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.next_rowcol_w[21:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.num_cols128_m1[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.num_cols_in_m1[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.num_rows_in_m1[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.num_rows_m1[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.pre_act[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.pre_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.pre_write[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.rom_cmd[1:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.rom_r[11:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.rom_skip[1:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.row[14:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.row_col_bank[24:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.row_col_bank_next_w[24:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.rowcol_inc[13:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.rowcol_inc_in[13:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.rst[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.scan_col[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.scan_row[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.skip_next_page[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.skip_next_page_in[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.start[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.start_bank[2:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.start_col[6:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.start_d[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.start_row[14:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.top_rc[21:0] @1401200 -encod_tiled_wr @c00200 -encod_tiled_rd @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.gen_run[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.gen_addr[3:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.rom_r[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.pre_done[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enc_cmd[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enc_wr[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enc_done[0] @200 - @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.bank[2:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.col[6:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.col_bank[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enable_act[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enable_autopre[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enc_cmd[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enc_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enc_wr[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.first_col[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.full_cmd[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.gen_addr[3:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.gen_run[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.keep_open[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.keep_open_in[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.last_col[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.last_row[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.loop_continue[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.next_bank_w[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.next_rowcol_w[21:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.num_cols128_m1[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.num_cols_in_m1[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.num_rows_in_m1[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.num_rows_m1[5:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.pre_act[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.pre_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.pre_read[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.rom_cmd[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.rom_r[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.rom_skip[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.row[14:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.row_col_bank[24:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.row_col_bank_next_w[24:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.rowcol_inc[13:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.rowcol_inc_in[13:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.rst[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.scan_col[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.scan_row[5:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.skip_next_page[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.skip_next_page_in[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.start[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.start_bank[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.start_col[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.start_d[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.start_row[14:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.top_rc[21:0] @1401200 -encod_tiled_rd @c00200 -ch2rd @22 x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.data_in[63:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_data_out[31:0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_raddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_rd[0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_regen[0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page[1:0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page_next[0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page_r[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.waddr[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wclk[0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.we[0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wpage_in[1:0] x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wpage_set[0] @1401200 -ch2rd -TILED_CH2 @c00200 -TILED32_CH4 -ch4wr @22 x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.data_out[63:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.ext_clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.ext_data_in[31:0] x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.ext_waddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.ext_we[0] x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.page[1:0] x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.page_next[0] x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.page_r[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.raddr[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.rclk[0] x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.rd[0] x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.regen[0] x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.rpage_in[1:0] x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.rpage_set[0] @1401200 -ch4wr @c00200 -ch4rd @22 x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.data_in[63:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.ext_clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.ext_data_out[31:0] x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.ext_raddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.ext_rd[0] x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.ext_regen[0] x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.page[1:0] x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.page_next[0] x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.page_r[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.waddr[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.wclk[0] x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.we[0] x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.wpage_in[1:0] x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.wpage_set[0] @1401200 -ch4rd @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.gen_run[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.gen_addr[3:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.rom_r[12:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.pre_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_wr[0] @800022 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_cmd[31:0] @28 (29)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_cmd[31:0] (30)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_cmd[31:0] (31)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_cmd[31:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_done[0] @1001200 -group_end @200 - @c00200 -encod_tiled_wr32 @200 - @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.bank[2:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.col[6:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.col_bank[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enable_act[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enable_autopre[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_cmd[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_wr[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.first_col[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.full_cmd[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.gen_addr[3:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.gen_run[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.keep_open[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.keep_open_in[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.last_col[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.last_row[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.loop_continue[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.next_bank_w[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.next_rowcol_w[21:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.num_cols128_m1[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.num_cols_in_m1[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.num_rows_in_m1[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.num_rows_m1[5:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.pre_act[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.pre_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.pre_write[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.rom_cmd[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.rom_r[12:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.rom_skip[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.row[14:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.row_col_bank[24:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.row_col_bank_next_w[24:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.rowcol_inc[13:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.rowcol_inc_in[13:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.rst[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.scan_col[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.scan_row[5:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.skip_next_page[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.skip_next_page_in[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.start[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.start_bank[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.start_col[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.start_d[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.start_row[14:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.top_rc[21:0] @1401200 -encod_tiled_wr32 @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.gen_run[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.gen_addr[3:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.rom_r[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.pre_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_wr[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_cmd[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_done[0] @200 - @c00200 -encod_tiled_rd32 @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.bank[2:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.col[6:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.col_bank[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enable_act[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enable_autopre[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_cmd[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_wr[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.first_col[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.full_cmd[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.gen_addr[3:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.gen_run[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.keep_open[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.keep_open_in[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.last_col[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.last_row[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.loop_continue[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.next_bank_w[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.next_rowcol_w[21:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.num_cols128_m2[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.num_cols_in_m1[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.num_rows_in_m1[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.num_rows_m1[5:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.pre_act[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.pre_done[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.pre_read[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.rom_cmd[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.rom_r[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.rom_skip[1:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.row[14:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.row_col_bank[24:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.row_col_bank_next_w[24:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.rowcol_inc[13:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.rowcol_inc_in[13:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.rst[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.scan_col[5:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.scan_row[5:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.skip_next_page[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.skip_next_page_in[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.start[0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.start_bank[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.start_col[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.start_d[0] @22 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.start_row[14:0] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.top_rc[21:0] @1401200 -encod_tiled_rd32 @c00200 -tiled_ch4 @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.busy_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.byte32[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.calc_valid[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.chn_en[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.chn_rst[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.chn_rst_d[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_a[3:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_ad[7:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_data[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_extra_pages[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_stb[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_we[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_wrmem[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.continued_tile[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.curr_x[12:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.curr_y[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_done[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_done_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_finished[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_finished_r[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_full_width[13:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_full_width_r[13:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_start[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_x[12:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_y8_r[12:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_y[15:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.i[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.keep_open[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_block[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_in_row[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_in_row_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_row_w[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.leftover_cols[5:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.lim_by_tile_width[6:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_start_addr[21:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_start_page_left[6:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_unfinished[15:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_unfinished_r0[15:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_unfinished_r1[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.lsw13_zero[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mclk[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mem_page_left[7:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mode_reg[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.msw_zero[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mul_rslt[21:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mul_rslt_w[26:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.need_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.next_page[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.next_y[16:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_cols_m1[5:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_cols_m1_w[6:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_cols_r[6:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_rows_m1[5:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_rows_m1_w[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.page_cntr[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.par_mod_r[8:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.pending_xfers[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.pgm_param_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.pre_want[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.remainder_tile_width[7:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.row_col_r[21:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.row_left[13:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.rowcol_inc[13:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.rst[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_frame_width_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_mode_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_start_addr_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_status_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_tile_whs_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_window_start_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_window_wh_w[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_window_x0y0_w[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_addr[21:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_addr_r[21:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_not_partial[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_x[12:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_y[15:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.status_ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.status_data[1:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.status_rq[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.status_start[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.suspend[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_cols[6:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_vstep[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_vstep_zero[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_width_zero[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.want_r[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_height[16:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_width[13:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_x0[12:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_y0[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_bank[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_col[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_grant[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_limited_by_mem_page[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_limited_by_mem_page_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_need[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_done[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_done_d[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_rst_neg[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_rst_pos[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_rst_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_rst_rd[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_rst_wr[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_partial[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_row[14:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start32_rd[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start32_rd_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start32_wr[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start32_wr_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_r[2:0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_rd[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_rd_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_wr[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_wr_r[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_want[0] @1401200 -tiled_ch4 -TILED32_CH4 @c00200 -mmcm_phase_cntr @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfb_stopped[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfbin[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfbout[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfboutb[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkin[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkin_stopped[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout0[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout0b[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout1[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout1b[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout2[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout2b[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout3[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout3b[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout4[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout5[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout6[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.diff[8:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.locked[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_busy[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_din[7:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_dout[7:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_dout_r[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_ready[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_start0[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_start[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_target[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_we[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.psclk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.psdone[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.psen[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.psincdec[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.pwrdwn[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.rst[0] @1401200 -mmcm_phase_cntr @c00200 -memcntrl16_0 @200 - - @c00200 -debug_ch2_ch4 @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.set_tile_whs_w[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.tile_cols[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_we[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.match_low[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.match_high[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.stb[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.stb_d[0] @c00022 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0] @28 (0)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0] (1)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0] (2)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0] (3)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0] (4)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0] @1401200 -group_end @200 - @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_tile_whs_w[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_cols[6:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_we[0] @22 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.match_low[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.match_high[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.stb[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.stb_d[0] @c00022 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0] @28 (0)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0] (1)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0] (2)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0] (3)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0] (4)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0] @1401200 -group_end -debug_ch2_ch4 @200 - @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_16bit_we[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_16bit_data[15:0] @c00200 -cmd_deser_16bit_i @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_deser_16bit_i.ad[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_deser_16bit_i.addr[2:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_deser_16bit_i.clk[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_deser_16bit_i.data[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_deser_16bit_i.rst[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_deser_16bit_i.stb[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_deser_16bit_i.we[0] @1401200 -cmd_deser_16bit_i @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rchn_late[3:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rd_late[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rpage_nxt[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rchn[3:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rdata[63:0] @200 - @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.mclk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_enabled[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_data[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_set[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_fill[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_full[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.en_schedul[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_chn_w[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_seq_w[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.sel_refresh_w[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_wr[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_run[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.grant_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_set[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_addr_start[10:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_done0[0] @200 - @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_addr[10:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_busy[0] @800200 -memcntr_sequencer @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_nop[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_addr_in[14:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_bank_in[2:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw_pos[2:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_odt_in[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cke_dis[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_sel_in[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_en_in[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_en_in[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_toggle_en[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_en_in[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_wr[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rd[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cmd_add_pause[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rst[0] @1000200 -memcntr_sequencer @200 - @800200 -cmd0_buf @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.data_in[31:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.data_out[31:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.raddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.rclk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.regen[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.ren[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.waddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.wclk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.we[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.web[3:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rrefresh[0] @1000200 -cmd0_buf @1401200 -memcntrl16_0 @c00200 -scheduler @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_enabled[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_fill[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_full[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_wr_chn[3:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_set[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_set[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.en_schedul[0] @200 - @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.chn_en[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.clk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.en_schedul[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_chn[3:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_chn_r[3:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_sent[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_w[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.index[3:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.index_valid[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_conf[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_r[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_set[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_some[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_want_conf[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_want_conf_d[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.next_need_conf[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.next_want_conf[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_addr[3:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_data[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_en[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pri_reg[255:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.rst[0] @c00022 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] @28 (0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (2)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (3)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (4)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (5)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (6)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (7)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (8)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (9)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (10)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (11)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (12)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (13)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (14)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (15)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (16)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (17)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (18)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (19)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (20)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (21)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (22)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (23)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (24)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (25)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (26)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (27)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (28)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (29)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (30)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (31)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (32)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (33)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (34)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (35)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (36)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (37)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (38)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (39)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (40)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (41)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (42)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (43)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (44)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (45)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (46)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (47)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (48)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (49)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (50)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (51)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (52)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (53)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (54)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (55)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (56)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (57)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (58)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (59)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (60)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (61)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (62)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (63)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (64)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (65)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (66)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (67)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (68)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (69)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (70)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (71)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (72)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (73)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (74)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (75)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (76)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (77)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (78)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (79)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (80)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (81)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (82)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (83)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (84)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (85)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (86)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (87)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (88)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (89)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (90)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (91)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (92)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] (93)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0] 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(1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] (2)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] (3)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] (4)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] (5)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] (6)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] (7)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] (8)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] (9)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] (10)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] (11)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] (12)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] (13)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] (14)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] (15)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0] @1401200 -group_end @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0] @1401200 -scheduler @c00200 -phy_cmd @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.mclk[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.pause_len[9:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_addr[29:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_addr_calm[14:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_addr_in[14:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_addr_prev[14:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_bank[5:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_bank_calm[2:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_bank_in[2:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_bank_prev[2:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rd[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rd_cur[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rst[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rst_cur[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_wr[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_wr_cur[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cke[1:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cke_dis[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cke_dis_cur[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cke_in[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cmd_add_pause[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cmd_nop[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cmd_word[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dci_dis_dq[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dci_dis_dqs[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dci_en_cur[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dci_en_in[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dci_in[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dci_ready[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dly_ready[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_en_cur[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_en_in[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_tri[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_tri_in[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_en_cur[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_en_in[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_toggle_cur[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_toggle_en[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_tri[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_tri_in[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_locked_mmcm[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_locked_pll[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_odt[1:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_odt_cur[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_odt_in[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_ps_out[7:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_ps_rdy[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw[5:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw_cur[2:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw_in[2:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw_pos[2:0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rdata[63:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rdata_r[63:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_sel_cur[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_sel_in[0] @1401200 -phy_cmd @800200 -cmd1_buf @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_sel[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_done[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.pause[0] @800022 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0] @28 (0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0] (1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0] (2)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0] @1001200 -group_end @200 - @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.data_in[31:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.data_out[31:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.raddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.rclk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.regen[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.ren[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.waddr[9:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.wclk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.we[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.web[3:0] @1000200 -cmd1_buf @c00200 -max_0001 @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.a[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.b[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.clk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.mask_a[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.mask_b[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.max[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.s[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.s_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.s_w[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001.valid[0] @1401200 -max_0001 @c00200 -max_00010203 @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.a[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.b[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.clk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.mask_a[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.mask_b[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.max[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.s[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.s_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.s_w[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg00010203.valid[0] @1401200 -max_00010203 @c00200 -max_0001020304050607 @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.a[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.b[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.clk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.mask_a[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.mask_b[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.max[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.s[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.s_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.s_w[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg0001020304050607.valid[0] @1401200 -max_0001020304050607 @c00200 -max_00__15 @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.a[15:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.b[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.clk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.mask_a[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.mask_b[0] @22 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.max[15:0] @28 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.s[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.s_r[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.s_w[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.i_masked_max_reg.valid[0] @1401200 -max_00__15 [pattern_trace] 1 [pattern_trace] 0