Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Wed Mar 31 22:29:58 2021
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_timing_summary -file vivado_build/x393_boson.timing_summary_impl
| Design : x393
| Device : 7z030-fbg484
| Speed File : -1 PRODUCTION 1.11 2014-09-11
-----------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : false
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There are 16 register/latch pins with no clock driven by root clock pin: DQSL (HIGH)
There are 16 register/latch pins with no clock driven by root clock pin: DQSU (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: ffclk1p (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: memclk (HIGH)
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 20 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There are 78 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 91 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
0.100 0.000 0 154323 0.015 0.000 0 154323 0.001 0.000 0 62737
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
axi_aclk {0.000 10.000} 20.000 50.000
axihp_clk {0.000 3.333} 6.667 150.000
clk_fb {0.000 10.000} 20.000 50.000
ddr3_clk {0.000 1.250} 2.500 400.000
ddr3_clk_div {0.000 2.500} 5.000 200.000
ddr3_clk_ref {0.000 2.500} 5.000 200.000
ddr3_mclk {1.250 3.750} 5.000 200.000
ddr3_sdclk {0.000 1.250} 2.500 400.000
multi_clkfb {0.000 10.000} 20.000 50.000
sclk {0.000 5.000} 10.000 100.000
xclk {0.000 2.083} 4.167 240.000
clk_boson0 {0.000 18.518} 37.037 27.000
clk_fb_pre {0.000 18.518} 37.037 27.000
iclk0 {-7.253 11.265} 37.037 27.000
iclk1x0 {-7.253 0.154} 14.815 67.500
iclk2x0 {-7.253 -3.549} 7.407 135.000
clk_boson1 {0.000 18.518} 37.037 27.000
clk_fb_pre_1 {0.000 18.518} 37.037 27.000
iclk1 {-7.253 11.265} 37.037 27.000
iclk1x1 {-7.253 0.154} 14.815 67.500
iclk2x1 {-7.253 -3.549} 7.407 135.000
clk_boson2 {0.000 18.518} 37.037 27.000
clk_fb_pre_2 {0.000 18.518} 37.037 27.000
iclk1x2 {-7.253 0.154} 14.815 67.500
iclk2 {-7.253 11.265} 37.037 27.000
iclk2x2 {-7.253 -3.549} 7.407 135.000
clk_boson3 {0.000 18.518} 37.037 27.000
clk_fb_pre_3 {0.000 18.518} 37.037 27.000
iclk1x3 {-7.253 0.154} 14.815 67.500
iclk2x3 {-7.253 -3.549} 7.407 135.000
iclk3 {-7.253 11.265} 37.037 27.000
ffclk0 {0.000 20.833} 41.667 24.000
gtrefclk {0.000 3.333} 6.666 150.015
rx_clk {0.000 3.333} 6.666 150.015
txoutclk {0.000 3.333} 6.666 150.015
usrclk2 {0.000 6.666} 13.333 75.002
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
axi_aclk 13.447 0.000 0 2685 0.057 0.000 0 2685 7.000 0.000 0 737
axihp_clk 0.473 0.000 0 10276 0.044 0.000 0 10276 0.267 0.000 0 3866
clk_fb 18.751 0.000 0 2
ddr3_clk 0.279 0.000 0 45
ddr3_clk_div 0.250 0.000 0 2158 0.135 0.000 0 2158 1.389 0.000 0 755
ddr3_clk_ref 0.264 0.000 0 5
ddr3_mclk 0.217 0.000 0 86792 0.015 0.000 0 86792 0.001 0.000 0 34865
ddr3_sdclk 1.092 0.000 0 3
multi_clkfb 18.751 0.000 0 2
sclk 4.281 0.000 0 2920 0.051 0.000 0 2920 4.090 0.000 0 1451
xclk 0.156 0.000 0 33131 0.042 0.000 0 33131 0.875 0.000 0 13493
clk_boson0 13.518 0.000 0 1
clk_fb_pre 35.788 0.000 0 2
iclk0 30.657 0.000 0 2326 0.055 0.000 0 2326 17.608 0.000 0 1178
iclk1x0 12.312 0.000 0 82 0.140 0.000 0 82 7.007 0.000 0 60
iclk2x0 6.000 0.000 0 8
clk_boson1 13.518 0.000 0 1
clk_fb_pre_1 15.596 0.000 0 2
iclk1 29.797 0.000 0 2326 0.042 0.000 0 2326 17.608 0.000 0 1178
iclk1x1 12.646 0.000 0 82 0.138 0.000 0 82 7.007 0.000 0 60
iclk2x1 5.807 0.000 0 8
clk_boson2 13.518 0.000 0 1
clk_fb_pre_2 35.788 0.000 0 2
iclk1x2 12.219 0.000 0 82 0.120 0.000 0 82 7.007 0.000 0 60
iclk2 29.813 0.000 0 2326 0.061 0.000 0 2326 17.608 0.000 0 1178
iclk2x2 6.000 0.000 0 8
clk_boson3 13.518 0.000 0 1
clk_fb_pre_3 15.596 0.000 0 2
iclk1x3 12.029 0.000 0 82 0.150 0.000 0 82 7.007 0.000 0 60
iclk2x3 5.807 0.000 0 8
iclk3 29.987 0.000 0 2326 0.085 0.000 0 2326 17.608 0.000 0 1178
ffclk0 39.562 0.000 0 1 0.843 0.000 0 1 20.483 0.000 0 1
gtrefclk 4.424 0.000 0 45 0.233 0.000 0 45 2.553 0.000 0 25
rx_clk 0.839 0.000 0 917 0.058 0.000 0 917 2.423 0.000 0 329
txoutclk 0.968 0.000 0 232 0.100 0.000 0 232 2.666 0.000 0 138
usrclk2 3.391 0.000 0 4579 0.029 0.000 0 4579 5.756 0.000 0 2024
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
ddr3_clk_div ddr3_clk 0.100 0.000 0 23 0.172 0.000 0 23
ddr3_mclk ddr3_clk_div 0.188 0.000 0 146 1.426 0.000 0 146
ddr3_clk_div ddr3_mclk 2.610 0.000 0 76 0.544 0.000 0 76
iclk1x0 iclk0 5.510 0.000 0 28 0.147 0.000 0 28
iclk0 iclk1x0 2.547 0.000 0 1 3.577 0.000 0 1
iclk1x1 iclk1 5.033 0.000 0 28 0.147 0.000 0 28
iclk1 iclk1x1 2.549 0.000 0 1 3.350 0.000 0 1
iclk2 iclk1x2 2.827 0.000 0 1 3.461 0.000 0 1
iclk1x2 iclk2 5.486 0.000 0 28 0.102 0.000 0 28
iclk3 iclk1x3 2.725 0.000 0 1 3.318 0.000 0 1
iclk1x3 iclk3 5.084 0.000 0 28 0.146 0.000 0 28
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
**async_default** axihp_clk axihp_clk 2.567 0.000 0 23 0.489 0.000 0 23
**async_default** ddr3_mclk ddr3_mclk 0.577 0.000 0 453 0.303 0.000 0 453
**async_default** iclk0 iclk0 34.838 0.000 0 5 0.578 0.000 0 5
**async_default** iclk1x0 iclk0 2.308 0.000 0 1 3.676 0.000 0 1
**async_default** iclk1 iclk1 35.328 0.000 0 5 0.486 0.000 0 5
**async_default** iclk1x1 iclk1 2.093 0.000 0 1 3.530 0.000 0 1
**async_default** iclk1x2 iclk2 2.279 0.000 0 1 3.700 0.000 0 1
**async_default** iclk2 iclk2 33.682 0.000 0 5 0.517 0.000 0 5
**async_default** iclk1x3 iclk3 2.272 0.000 0 1 3.482 0.000 0 1
**async_default** iclk3 iclk3 34.122 0.000 0 5 0.445 0.000 0 5
**async_default** sclk sclk 5.990 0.000 0 16 0.396 0.000 0 16
**async_default** usrclk2 usrclk2 4.953 0.000 0 7 0.715 0.000 0 7
**async_default** xclk xclk 1.004 0.000 0 72 0.398 0.000 0 72
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: axi_aclk
To Clock: axi_aclk
Setup : 0 Failing Endpoints, Worst Slack 13.447ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.057ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 13.447ns (required time - arrival time)
Source: mcntrl393_i/select_buf2rd_reg/C
(rising edge-triggered cell FDRE clocked by axi_aclk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: ps7_i/MAXIGP0RDATA[7]
(rising edge-triggered cell PS7 clocked by axi_aclk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: axi_aclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (axi_aclk rise@20.000ns - axi_aclk rise@0.000ns)
Data Path Delay: 5.742ns (logic 0.428ns (7.454%) route 5.314ns (92.546%))
Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1)
Clock Path Skew: -0.226ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.336ns = ( 21.336 - 20.000 )
Source Clock Delay (SCD): 1.572ns
Clock Pessimism Removal (CPR): 0.010ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axi_aclk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.572 1.572 mcntrl393_i/axi_clk
SLICE_X37Y155 FDRE r mcntrl393_i/select_buf2rd_reg/C
------------------------------------------------------------------- -------------------
SLICE_X37Y155 FDRE (Prop_fdre_C_Q) 0.269 1.841 r mcntrl393_i/select_buf2rd_reg/Q
net (fo=34, routed) 2.110 3.951 cmd_readback_i/lopt_1
SLICE_X70Y156 LUT4 (Prop_lut4_I1_O) 0.053 4.004 r cmd_readback_i/xlnx_opt_LUT_ps7_i_i_54/O
net (fo=1, routed) 1.066 5.069 cmd_readback_i/xlnx_opt_MAXIGP0RDATA[7]_1
SLICE_X55Y157 LUT5 (Prop_lut5_I4_O) 0.053 5.122 r cmd_readback_i/xlnx_opt_LUT_ps7_i_i_54_1/O
net (fo=1, routed) 0.878 6.000 cmd_readback_i/xlnx_opt_MAXIGP0RDATA[7]
SLICE_X55Y161 LUT6 (Prop_lut6_I5_O) 0.053 6.053 r cmd_readback_i/xlnx_opt_LUT_ps7_i_i_54_2/O
net (fo=1, routed) 1.261 7.314 axird_rdata[7]
PS7_X0Y0 PS7 r ps7_i/MAXIGP0RDATA[7]
------------------------------------------------------------------- -------------------
(clock axi_aclk rise edge)
20.000 20.000 r
BUFGCTRL_X0Y17 BUFG 0.000 20.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.336 21.336 axi_aclk
PS7_X0Y0 PS7 r ps7_i/MAXIGP0ACLK
clock pessimism 0.010 21.346
clock uncertainty -0.035 21.311
PS7_X0Y0 PS7 (Setup_ps7_MAXIGP0ACLK_MAXIGP0RDATA[7])
-0.550 20.761 ps7_i
-------------------------------------------------------------------
required time 20.761
arrival time -7.314
-------------------------------------------------------------------
slack 13.447
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.057ns (arrival time - required time)
Source: axibram_write_i/waddr_i/inreg_reg[21]/C
(rising edge-triggered cell FDRE clocked by axi_aclk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: axibram_write_i/waddr_i/ram_reg_0_15_18_21/RAMB_D1/I
(rising edge-triggered cell RAMD32 clocked by axi_aclk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: axi_aclk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (axi_aclk rise@0.000ns - axi_aclk rise@0.000ns)
Data Path Delay: 0.205ns (logic 0.100ns (48.867%) route 0.105ns (51.133%))
Logic Levels: 0
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 0.838ns
Source Clock Delay (SCD): 0.612ns
Clock Pessimism Removal (CPR): 0.193ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axi_aclk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.612 0.612 axibram_write_i/waddr_i/axi_clk
SLICE_X33Y153 FDRE r axibram_write_i/waddr_i/inreg_reg[21]/C
------------------------------------------------------------------- -------------------
SLICE_X33Y153 FDRE (Prop_fdre_C_Q) 0.100 0.712 r axibram_write_i/waddr_i/inreg_reg[21]/Q
net (fo=1, routed) 0.105 0.817 axibram_write_i/waddr_i/ram_reg_0_15_18_21/DIB1
SLICE_X34Y153 RAMD32 r axibram_write_i/waddr_i/ram_reg_0_15_18_21/RAMB_D1/I
------------------------------------------------------------------- -------------------
(clock axi_aclk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.838 0.838 axibram_write_i/waddr_i/ram_reg_0_15_18_21/WCLK
SLICE_X34Y153 RAMD32 r axibram_write_i/waddr_i/ram_reg_0_15_18_21/RAMB_D1/CLK
clock pessimism -0.193 0.645
SLICE_X34Y153 RAMD32 (Hold_ramd32_CLK_I)
0.115 0.760 axibram_write_i/waddr_i/ram_reg_0_15_18_21/RAMB_D1
-------------------------------------------------------------------
required time -0.760
arrival time 0.817
-------------------------------------------------------------------
slack 0.057
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: axi_aclk
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { clocks393_i/bufg_axi_aclk_i/O }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 20.000 17.817 RAMB36_X3Y33 cmd_readback_i/ram_reg_0/CLKBWRCLK
Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X1Y1 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X1Y1 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X1Y1 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
---------------------------------------------------------------------------------------------------
From Clock: axihp_clk
To Clock: axihp_clk
Setup : 0 Failing Endpoints, Worst Slack 0.473ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.044ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 0.267ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.473ns (required time - arrival time)
Source: sync_resets_i/rst_block[9].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/C
(rising edge-triggered cell FDRE clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns})
Destination: sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register1_r_reg[15]/R
(rising edge-triggered cell FDRE clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns})
Path Group: axihp_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 6.667ns (axihp_clk rise@6.667ns - axihp_clk rise@0.000ns)
Data Path Delay: 5.687ns (logic 0.269ns (4.730%) route 5.418ns (95.270%))
Logic Levels: 0
Clock Path Skew: -0.068ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.751ns = ( 11.418 - 6.667 )
Source Clock Delay (SCD): 5.048ns
Clock Pessimism Removal (CPR): 0.229ns
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.124ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.610 1.610 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.088 1.698 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.621 3.319 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.120 3.439 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3871, routed) 1.609 5.048 sync_resets_i/rst_block[9].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk
SLICE_X29Y154 FDRE r sync_resets_i/rst_block[9].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/C
------------------------------------------------------------------- -------------------
SLICE_X29Y154 FDRE (Prop_fdre_C_Q) 0.269 5.317 r sync_resets_i/rst_block[9].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/Q
net (fo=335, routed) 5.418 10.735 sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/regs_reg[4][0]
SLICE_X107Y5 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register1_r_reg[15]/R
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
6.667 6.667 r
BUFGCTRL_X0Y17 BUFG 0.000 6.667 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.476 8.143 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.083 8.226 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.538 9.764 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.113 9.877 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3871, routed) 1.541 11.418 sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/hclk
SLICE_X107Y5 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register1_r_reg[15]/C
clock pessimism 0.229 11.647
clock uncertainty -0.071 11.575
SLICE_X107Y5 FDRE (Setup_fdre_C_R) -0.367 11.208 sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register1_r_reg[15]
-------------------------------------------------------------------
required time 11.208
arrival time -10.735
-------------------------------------------------------------------
slack 0.473
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.044ns (arrival time - required time)
Source: mult_saxi_wr_i/fifo_same_clock_i/inreg_reg[22]/C
(rising edge-triggered cell FDRE clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns})
Destination: mult_saxi_wr_i/fifo_same_clock_i/ram_reg_0_15_18_23/RAMC/I
(rising edge-triggered cell RAMD32 clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns})
Path Group: axihp_clk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (axihp_clk rise@0.000ns - axihp_clk rise@0.000ns)
Data Path Delay: 0.146ns (logic 0.091ns (62.374%) route 0.055ns (37.626%))
Logic Levels: 0
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.396ns
Source Clock Delay (SCD): 1.887ns
Clock Pessimism Removal (CPR): 0.498ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.604 0.604 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.050 0.654 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.577 1.231 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.257 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3871, routed) 0.630 1.887 mult_saxi_wr_i/fifo_same_clock_i/hclk
SLICE_X31Y186 FDRE r mult_saxi_wr_i/fifo_same_clock_i/inreg_reg[22]/C
------------------------------------------------------------------- -------------------
SLICE_X31Y186 FDRE (Prop_fdre_C_Q) 0.091 1.978 r mult_saxi_wr_i/fifo_same_clock_i/inreg_reg[22]/Q
net (fo=1, routed) 0.055 2.033 mult_saxi_wr_i/fifo_same_clock_i/ram_reg_0_15_18_23/DIC0
SLICE_X30Y186 RAMD32 r mult_saxi_wr_i/fifo_same_clock_i/ram_reg_0_15_18_23/RAMC/I
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.816 0.816 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.053 0.869 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.643 1.512 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 1.542 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3871, routed) 0.854 2.396 mult_saxi_wr_i/fifo_same_clock_i/ram_reg_0_15_18_23/WCLK
SLICE_X30Y186 RAMD32 r mult_saxi_wr_i/fifo_same_clock_i/ram_reg_0_15_18_23/RAMC/CLK
clock pessimism -0.498 1.898
SLICE_X30Y186 RAMD32 (Hold_ramd32_CLK_I)
0.091 1.989 mult_saxi_wr_i/fifo_same_clock_i/ram_reg_0_15_18_23/RAMC
-------------------------------------------------------------------
required time -1.989
arrival time 2.033
-------------------------------------------------------------------
slack 0.044
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: axihp_clk
Waveform(ns): { 0.000 3.333 }
Period(ns): 6.667
Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 6.400 6.667 0.267 GTXE2_CHANNEL_X0Y0 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/DRPCLK
Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 6.667 153.333 PLLE2_ADV_X1Y1 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
Low Pulse Width Slow RAMD32/CLK n/a 0.910 3.333 2.423 SLICE_X34Y143 sata_top/ahci_top_i/axi_ahci_regs_i/ahci_regs_set_i/ram_reg_0_15_6_11/RAMA/CLK
High Pulse Width Slow RAMD32/CLK n/a 0.910 3.333 2.423 SLICE_X42Y134 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_ram_reg_0_7_12_17/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: clk_fb
To Clock: clk_fb
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 18.751ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_fb
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 20.000 80.000 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: ddr3_clk
To Clock: ddr3_clk
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 0.279ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_clk
Waveform(ns): { 0.000 1.250 }
Period(ns): 2.500
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFR/I n/a 2.221 2.500 0.279 BUFR_X1Y8 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/I
Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 2.500 210.860 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1
---------------------------------------------------------------------------------------------------
From Clock: ddr3_clk_div
To Clock: ddr3_clk_div
Setup : 0 Failing Endpoints, Worst Slack 0.250ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.135ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 1.389ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.250ns (required time - arrival time)
Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/C
(rising edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[3].dq_i/oserdes_i/oserdes_i/RST
(rising edge-triggered cell OSERDESE2 clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: ddr3_clk_div
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (ddr3_clk_div rise@5.000ns - ddr3_clk_div rise@0.000ns)
Data Path Delay: 3.878ns (logic 0.269ns (6.937%) route 3.609ns (93.063%))
Logic Levels: 0
Clock Path Skew: -0.042ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.639ns = ( 8.639 - 5.000 )
Source Clock Delay (SCD): 3.937ns
Clock Pessimism Removal (CPR): 0.256ns
Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.156ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.575 1.575 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.088 1.663 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.106 2.769 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.377 3.146 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.791 3.937 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/CLK
SLICE_X71Y100 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/C
------------------------------------------------------------------- -------------------
SLICE_X71Y100 FDRE (Prop_fdre_C_Q) 0.269 4.206 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/Q
net (fo=786, routed) 3.609 7.815 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[3].dq_i/oserdes_i/tin
OLOGIC_X1Y135 OSERDESE2 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[3].dq_i/oserdes_i/oserdes_i/RST
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
5.000 5.000 r
BUFGCTRL_X0Y17 BUFG 0.000 5.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.437 6.437 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.083 6.520 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.016 7.536 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.370 7.906 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.733 8.639 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[3].dq_i/oserdes_i/psincdec_reg_0
OLOGIC_X1Y135 OSERDESE2 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[3].dq_i/oserdes_i/oserdes_i/CLKDIV
clock pessimism 0.256 8.895
clock uncertainty -0.085 8.810
OLOGIC_X1Y135 OSERDESE2 (Setup_oserdese2_CLKDIV_RST)
-0.745 8.065 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[3].dq_i/oserdes_i/oserdes_i
-------------------------------------------------------------------
required time 8.065
arrival time -7.815
-------------------------------------------------------------------
slack 0.250
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.135ns (arrival time - required time)
Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/ld_idly_reg[7]/C
(rising edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[7].dq_i/dq_in_dly_i/fdly_pre_reg[0]/D
(rising edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: ddr3_clk_div
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (ddr3_clk_div rise@0.000ns - ddr3_clk_div rise@0.000ns)
Data Path Delay: 0.233ns (logic 0.128ns (55.008%) route 0.105ns (44.992%))
Logic Levels: 1 (LUT3=1)
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.738ns
Source Clock Delay (SCD): 1.423ns
Clock Pessimism Removal (CPR): 0.304ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.580 0.580 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.050 0.630 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.433 1.063 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.090 1.153 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.270 1.423 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/psincdec_reg_0
SLICE_X119Y116 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/ld_idly_reg[7]/C
------------------------------------------------------------------- -------------------
SLICE_X119Y116 FDRE (Prop_fdre_C_Q) 0.100 1.523 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/ld_idly_reg[7]/Q
net (fo=5, routed) 0.105 1.628 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[7].dq_i/dq_in_dly_i/ld_idly_reg[7][0]
SLICE_X118Y116 LUT3 (Prop_lut3_I1_O) 0.028 1.656 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[7].dq_i/dq_in_dly_i/fdly_pre[0]_i_1__6/O
net (fo=1, routed) 0.000 1.656 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[7].dq_i/dq_in_dly_i/fdly_pre[0]_i_1__6_n_0
SLICE_X118Y116 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[7].dq_i/dq_in_dly_i/fdly_pre_reg[0]/D
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.796 0.796 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.053 0.849 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.490 1.339 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.093 1.432 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.306 1.738 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[7].dq_i/dq_in_dly_i/psincdec_reg
SLICE_X118Y116 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[7].dq_i/dq_in_dly_i/fdly_pre_reg[0]/C
clock pessimism -0.304 1.434
SLICE_X118Y116 FDRE (Hold_fdre_C_D) 0.087 1.521 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[7].dq_i/dq_in_dly_i/fdly_pre_reg[0]
-------------------------------------------------------------------
required time -1.521
arrival time 1.656
-------------------------------------------------------------------
slack 0.135
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_clk_div
Waveform(ns): { 0.000 2.500 }
Period(ns): 5.000
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFR/I n/a 2.221 5.000 2.779 BUFR_X1Y9 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/I
Max Period n/a MMCME2_ADV/CLKOUT2 n/a 213.360 5.000 208.360 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
Low Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.111 2.500 1.389 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK
High Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.111 2.500 1.389 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK
---------------------------------------------------------------------------------------------------
From Clock: ddr3_clk_ref
To Clock: ddr3_clk_ref
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_clk_ref
Waveform(ns): { 0.000 2.500 }
Period(ns): 5.000
Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT5 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a IDELAYCTRL/REFCLK n/a 3.225 5.000 1.775 IDELAYCTRL_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK
Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK
---------------------------------------------------------------------------------------------------
From Clock: ddr3_mclk
To Clock: ddr3_mclk
Setup : 0 Failing Endpoints, Worst Slack 0.217ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.015ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 0.001ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.217ns (required time - arrival time)
Source: sync_resets_i/rst_early_master_reg_rep__0/C
(rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Destination: compressor393_i/cmprs_afi0_mux_i/cmprs_afi_mux_status_i/status_generate0_i/status_generate_only_i/status_r_reg[10]/D
(rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Path Group: ddr3_mclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (ddr3_mclk rise@6.250ns - ddr3_mclk rise@1.250ns)
Data Path Delay: 4.760ns (logic 0.361ns (7.585%) route 4.399ns (92.415%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: 0.027ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.590ns = ( 10.840 - 6.250 )
Source Clock Delay (SCD): 4.807ns = ( 6.057 - 1.250 )
Clock Pessimism Removal (CPR): 0.244ns
Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.156ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y17 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.575 2.825 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.088 2.913 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 1.628 4.541 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.120 4.661 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=34863, routed) 1.396 6.057 sync_resets_i/mclk
SLICE_X58Y93 FDRE r sync_resets_i/rst_early_master_reg_rep__0/C
------------------------------------------------------------------- -------------------
SLICE_X58Y93 FDRE (Prop_fdre_C_Q) 0.308 6.365 f sync_resets_i/rst_early_master_reg_rep__0/Q
net (fo=1219, routed) 4.399 10.764 compressor393_i/cmprs_afi0_mux_i/cmprs_afi_mux_status_i/status_generate0_i/status_generate_only_i/rst_early_master_reg_rep__0
SLICE_X3Y92 LUT2 (Prop_lut2_I1_O) 0.053 10.817 r compressor393_i/cmprs_afi0_mux_i/cmprs_afi_mux_status_i/status_generate0_i/status_generate_only_i/status_r[10]_i_1__6/O
net (fo=1, routed) 0.000 10.817 compressor393_i/cmprs_afi0_mux_i/cmprs_afi_mux_status_i/status_generate0_i/status_generate_only_i/p_1_in[10]
SLICE_X3Y92 FDRE r compressor393_i/cmprs_afi0_mux_i/cmprs_afi_mux_status_i/status_generate0_i/status_generate_only_i/status_r_reg[10]/D
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
6.250 6.250 r
BUFGCTRL_X0Y17 BUFG 0.000 6.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.437 7.687 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.083 7.770 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 1.544 9.314 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.113 9.427 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=34863, routed) 1.413 10.840 compressor393_i/cmprs_afi0_mux_i/cmprs_afi_mux_status_i/status_generate0_i/status_generate_only_i/mclk
SLICE_X3Y92 FDRE r compressor393_i/cmprs_afi0_mux_i/cmprs_afi_mux_status_i/status_generate0_i/status_generate_only_i/status_r_reg[10]/C
clock pessimism 0.244 11.084
clock uncertainty -0.085 10.999
SLICE_X3Y92 FDRE (Setup_fdre_C_D) 0.035 11.034 compressor393_i/cmprs_afi0_mux_i/cmprs_afi_mux_status_i/status_generate0_i/status_generate_only_i/status_r_reg[10]
-------------------------------------------------------------------
required time 11.034
arrival time -10.817
-------------------------------------------------------------------
slack 0.217
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.015ns (arrival time - required time)
Source: mcntrl393_i/sens_comp_block[1].mcntrl_linear_wr_sensor_i/frame_start_r_reg[0]/C
(rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Destination: mcntrl393_i/sens_comp_block[1].mcntrl_linear_wr_sensor_i/page_cntr_reg[2]/D
(rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Path Group: ddr3_mclk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (ddr3_mclk rise@1.250ns - ddr3_mclk rise@1.250ns)
Data Path Delay: 0.291ns (logic 0.128ns (43.999%) route 0.163ns (56.001%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: 0.189ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.278ns = ( 3.528 - 1.250 )
Source Clock Delay (SCD): 1.802ns = ( 3.052 - 1.250 )
Clock Pessimism Removal (CPR): 0.287ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y17 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.580 1.830 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.050 1.880 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 0.559 2.439 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 2.465 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=34863, routed) 0.587 3.052 mcntrl393_i/sens_comp_block[1].mcntrl_linear_wr_sensor_i/clk
SLICE_X105Y99 FDRE r mcntrl393_i/sens_comp_block[1].mcntrl_linear_wr_sensor_i/frame_start_r_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X105Y99 FDRE (Prop_fdre_C_Q) 0.100 3.152 r mcntrl393_i/sens_comp_block[1].mcntrl_linear_wr_sensor_i/frame_start_r_reg[0]/Q
net (fo=57, routed) 0.163 3.315 mcntrl393_i/sens_comp_block[1].mcntrl_linear_wr_sensor_i/Q[0]
SLICE_X104Y100 LUT6 (Prop_lut6_I3_O) 0.028 3.343 r mcntrl393_i/sens_comp_block[1].mcntrl_linear_wr_sensor_i/page_cntr[2]_i_1__7/O
net (fo=1, routed) 0.000 3.343 mcntrl393_i/sens_comp_block[1].mcntrl_linear_wr_sensor_i/page_cntr[2]_i_1__7_n_0
SLICE_X104Y100 FDRE r mcntrl393_i/sens_comp_block[1].mcntrl_linear_wr_sensor_i/page_cntr_reg[2]/D
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y17 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.796 2.046 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.053 2.099 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 0.623 2.722 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.030 2.752 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=34863, routed) 0.776 3.528 mcntrl393_i/sens_comp_block[1].mcntrl_linear_wr_sensor_i/clk
SLICE_X104Y100 FDRE r mcntrl393_i/sens_comp_block[1].mcntrl_linear_wr_sensor_i/page_cntr_reg[2]/C
clock pessimism -0.287 3.241
SLICE_X104Y100 FDRE (Hold_fdre_C_D) 0.087 3.328 mcntrl393_i/sens_comp_block[1].mcntrl_linear_wr_sensor_i/page_cntr_reg[2]
-------------------------------------------------------------------
required time -3.328
arrival time 3.343
-------------------------------------------------------------------
slack 0.015
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_mclk
Waveform(ns): { 1.250 3.750 }
Period(ns): 5.000
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a PLLE2_ADV/DCLK n/a 4.999 5.000 0.001 PLLE2_ADV_X0Y1 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/DCLK
Max Period n/a MMCME2_ADV/CLKOUT3 n/a 213.360 5.000 208.360 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
Low Pulse Width Slow PLLE2_ADV/DCLK n/a 2.500 2.500 0.001 PLLE2_ADV_X0Y0 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/DCLK
High Pulse Width Slow PLLE2_ADV/DCLK n/a 2.500 2.500 0.001 PLLE2_ADV_X0Y1 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/DCLK
---------------------------------------------------------------------------------------------------
From Clock: ddr3_sdclk
To Clock: ddr3_sdclk
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 1.092ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_sdclk
Waveform(ns): { 0.000 1.250 }
Period(ns): 2.500
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFIO/I n/a 1.408 2.500 1.092 BUFIO_X1Y9 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/iclk_bufio_i/I
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 2.500 210.860 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
---------------------------------------------------------------------------------------------------
From Clock: multi_clkfb
To Clock: multi_clkfb
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 18.751ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: multi_clkfb
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X1Y1 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT
Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X1Y1 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: sclk
To Clock: sclk
Setup : 0 Failing Endpoints, Worst Slack 4.281ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.051ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 4.090ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 4.281ns (required time - arrival time)
Source: event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
(rising edge-triggered cell FDRE clocked by sclk {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
(falling edge-triggered cell FDRE clocked by sclk {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: sclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (sclk fall@5.000ns - sclk rise@0.000ns)
Data Path Delay: 0.622ns (logic 0.269ns (43.242%) route 0.353ns (56.758%))
Logic Levels: 0
Clock Path Skew: -0.017ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.671ns = ( 9.671 - 5.000 )
Source Clock Delay (SCD): 5.063ns
Clock Pessimism Removal (CPR): 0.375ns
Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.133ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sclk rise edge) 0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.610 1.610 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
0.088 1.698 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
net (fo=1, routed) 1.621 3.319 clocks393_i/sync_clk_i/sync_clk_pre
BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.120 3.439 r clocks393_i/sync_clk_i/clk1x_i/O
net (fo=1449, routed) 1.624 5.063 event_logger_i/i_imu_spi/camsync_clk
SLICE_X99Y168 FDRE r event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X99Y168 FDRE (Prop_fdre_C_Q) 0.269 5.332 r event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/Q
net (fo=2, routed) 0.353 5.685 event_logger_i/i_imu_spi/sngl_wire_stb_reg_n_0_[0]
SLICE_X100Y167 FDRE r event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
------------------------------------------------------------------- -------------------
(clock sclk fall edge) 5.000 5.000 f
BUFGCTRL_X0Y17 BUFG 0.000 5.000 f clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.476 6.476 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
0.083 6.559 f clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
net (fo=1, routed) 1.538 8.097 clocks393_i/sync_clk_i/sync_clk_pre
BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.113 8.210 f clocks393_i/sync_clk_i/clk1x_i/O
net (fo=1449, routed) 1.461 9.671 event_logger_i/i_imu_spi/camsync_clk
SLICE_X100Y167 FDRE r event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/C (IS_INVERTED)
clock pessimism 0.375 10.046
clock uncertainty -0.075 9.971
SLICE_X100Y167 FDRE (Setup_fdre_C_D) -0.004 9.967 event_logger_i/i_imu_spi/sngl_wire_r_reg[1]
-------------------------------------------------------------------
required time 9.967
arrival time -5.685
-------------------------------------------------------------------
slack 4.281
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.051ns (arrival time - required time)
Source: timing393_i/camsync393_i/dly_cntr_chn3_reg[19]/C
(rising edge-triggered cell FDRE clocked by sclk {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: timing393_i/camsync393_i/dly_cntr_chn3_reg[24]/D
(rising edge-triggered cell FDRE clocked by sclk {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: sclk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (sclk rise@0.000ns - sclk rise@0.000ns)
Data Path Delay: 0.441ns (logic 0.291ns (65.948%) route 0.150ns (34.052%))
Logic Levels: 4 (CARRY4=3 LUT3=1)
Clock Path Skew: 0.298ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.449ns
Source Clock Delay (SCD): 1.858ns
Clock Pessimism Removal (CPR): 0.293ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sclk rise edge) 0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.604 0.604 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
0.050 0.654 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
net (fo=1, routed) 0.577 1.231 clocks393_i/sync_clk_i/sync_clk_pre
BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.026 1.257 r clocks393_i/sync_clk_i/clk1x_i/O
net (fo=1449, routed) 0.601 1.858 timing393_i/camsync393_i/camsync_clk
SLICE_X114Y148 FDRE r timing393_i/camsync393_i/dly_cntr_chn3_reg[19]/C
------------------------------------------------------------------- -------------------
SLICE_X114Y148 FDRE (Prop_fdre_C_Q) 0.118 1.976 f timing393_i/camsync393_i/dly_cntr_chn3_reg[19]/Q
net (fo=2, routed) 0.150 2.126 timing393_i/camsync393_i/dly_cntr_chn3_reg[19]
SLICE_X114Y148 LUT3 (Prop_lut3_I1_O) 0.028 2.154 r timing393_i/camsync393_i/dly_cntr_chn3[16]_i_2/O
net (fo=1, routed) 0.000 2.154 timing393_i/camsync393_i/dly_cntr_chn3[16]_i_2_n_0
SLICE_X114Y148 CARRY4 (Prop_carry4_S[3]_CO[3])
0.077 2.231 r timing393_i/camsync393_i/dly_cntr_chn3_reg[16]_i_1/CO[3]
net (fo=1, routed) 0.000 2.231 timing393_i/camsync393_i/dly_cntr_chn3_reg[16]_i_1_n_0
SLICE_X114Y149 CARRY4 (Prop_carry4_CI_CO[3])
0.027 2.258 r timing393_i/camsync393_i/dly_cntr_chn3_reg[20]_i_1/CO[3]
net (fo=1, routed) 0.001 2.258 timing393_i/camsync393_i/dly_cntr_chn3_reg[20]_i_1_n_0
SLICE_X114Y150 CARRY4 (Prop_carry4_CI_O[0])
0.041 2.299 r timing393_i/camsync393_i/dly_cntr_chn3_reg[24]_i_1/O[0]
net (fo=1, routed) 0.000 2.299 timing393_i/camsync393_i/dly_cntr_chn3_reg[24]_i_1_n_7
SLICE_X114Y150 FDRE r timing393_i/camsync393_i/dly_cntr_chn3_reg[24]/D
------------------------------------------------------------------- -------------------
(clock sclk rise edge) 0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.816 0.816 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
0.053 0.869 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
net (fo=1, routed) 0.643 1.512 clocks393_i/sync_clk_i/sync_clk_pre
BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.030 1.542 r clocks393_i/sync_clk_i/clk1x_i/O
net (fo=1449, routed) 0.907 2.449 timing393_i/camsync393_i/camsync_clk
SLICE_X114Y150 FDRE r timing393_i/camsync393_i/dly_cntr_chn3_reg[24]/C
clock pessimism -0.293 2.156
SLICE_X114Y150 FDRE (Hold_fdre_C_D) 0.092 2.248 timing393_i/camsync393_i/dly_cntr_chn3_reg[24]
-------------------------------------------------------------------
required time -2.248
arrival time 2.299
-------------------------------------------------------------------
slack 0.051
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: sclk
Waveform(ns): { 0.000 5.000 }
Period(ns): 10.000
Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 1.600 10.000 8.400 BUFGCTRL_X0Y10 clocks393_i/sync_clk_i/clk1x_i/I
Max Period n/a PLLE2_ADV/CLKOUT3 n/a 160.000 10.000 150.000 PLLE2_ADV_X1Y1 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
Low Pulse Width Fast RAMD32/CLK n/a 0.910 5.000 4.090 SLICE_X90Y176 event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_6_11/RAMA/CLK
High Pulse Width Slow RAMD32/CLK n/a 0.910 5.000 4.090 SLICE_X86Y174 event_logger_i/i_nmea_decoder/odbuf2_ram_reg_0_31_0_3/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: xclk
To Clock: xclk
Setup : 0 Failing Endpoints, Worst Slack 0.156ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.042ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 0.875ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.156ns (required time - arrival time)
Source: compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/k1_reg[1]/C
(rising edge-triggered cell FDRE clocked by xclk {rise@0.000ns fall@2.083ns period=4.167ns})
Destination: compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]/D
(rising edge-triggered cell FDRE clocked by xclk {rise@0.000ns fall@2.083ns period=4.167ns})
Path Group: xclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 4.167ns (xclk rise@4.167ns - xclk rise@0.000ns)
Data Path Delay: 3.971ns (logic 1.433ns (36.090%) route 2.538ns (63.910%))
Logic Levels: 9 (CARRY4=5 LUT4=1 LUT5=2 LUT6=1)
Clock Path Skew: -0.021ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.690ns = ( 8.857 - 4.167 )
Source Clock Delay (SCD): 5.033ns
Clock Pessimism Removal (CPR): 0.322ns
Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.114ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock xclk rise edge) 0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.610 1.610 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
0.088 1.698 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
net (fo=1, routed) 1.621 3.319 clocks393_i/xclk_i/xclk_pre
BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.120 3.439 r clocks393_i/xclk_i/clk1x_i/O
net (fo=13491, routed) 1.594 5.033 compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/xclk
SLICE_X68Y44 FDRE r compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/k1_reg[1]/C
------------------------------------------------------------------- -------------------
SLICE_X68Y44 FDRE (Prop_fdre_C_Q) 0.269 5.302 r compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/k1_reg[1]/Q
net (fo=67, routed) 0.890 6.192 compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/k1_reg_n_0_[1]
SLICE_X73Y44 LUT5 (Prop_lut5_I3_O) 0.053 6.245 r compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2[6]_i_9__1/O
net (fo=1, routed) 0.344 6.589 compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2[6]_i_9__1_n_0
SLICE_X72Y45 CARRY4 (Prop_carry4_DI[2]_CO[3])
0.239 6.828 r compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[6]_i_3/CO[3]
net (fo=1, routed) 0.000 6.828 compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[6]_i_3_n_0
SLICE_X72Y46 CARRY4 (Prop_carry4_CI_O[0])
0.139 6.967 r compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[14]_i_15/O[0]
net (fo=2, routed) 0.495 7.462 compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[14]_i_15_n_7
SLICE_X69Y44 LUT4 (Prop_lut4_I3_O) 0.155 7.617 f compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2[10]_i_11__1/O
net (fo=3, routed) 0.387 8.004 compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2[10]_i_11__1_n_0
SLICE_X71Y46 LUT6 (Prop_lut6_I2_O) 0.053 8.057 r compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2[10]_i_3__2/O
net (fo=2, routed) 0.422 8.479 compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2[10]_i_3__2_n_0
SLICE_X69Y46 LUT5 (Prop_lut5_I0_O) 0.053 8.532 r compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2[10]_i_7__1/O
net (fo=1, routed) 0.000 8.532 compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2[10]_i_7__1_n_0
SLICE_X69Y46 CARRY4 (Prop_carry4_S[2]_CO[3])
0.235 8.767 r compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[10]_i_1/CO[3]
net (fo=1, routed) 0.000 8.767 compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[10]_i_1_n_0
SLICE_X69Y47 CARRY4 (Prop_carry4_CI_CO[3])
0.058 8.825 r compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[14]_i_1/CO[3]
net (fo=1, routed) 0.000 8.825 compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[14]_i_1_n_0
SLICE_X69Y48 CARRY4 (Prop_carry4_CI_CO[0])
0.179 9.004 r compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]_i_1/CO[0]
net (fo=1, routed) 0.000 9.004 compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/mm2[15]
SLICE_X69Y48 FDRE r compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]/D
------------------------------------------------------------------- -------------------
(clock xclk rise edge) 4.167 4.167 r
BUFGCTRL_X0Y17 BUFG 0.000 4.167 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.476 5.643 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
0.083 5.726 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
net (fo=1, routed) 1.538 7.264 clocks393_i/xclk_i/xclk_pre
BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.113 7.377 r clocks393_i/xclk_i/clk1x_i/O
net (fo=13491, routed) 1.480 8.857 compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/xclk
SLICE_X69Y48 FDRE r compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]/C
clock pessimism 0.322 9.179
clock uncertainty -0.067 9.111
SLICE_X69Y48 FDRE (Setup_fdre_C_D) 0.048 9.159 compressor393_i/cmprs_channel_block[3].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]
-------------------------------------------------------------------
required time 9.159
arrival time -9.004
-------------------------------------------------------------------
slack 0.156
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.042ns (arrival time - required time)
Source: compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[3].dly01_16_i/sr_reg[0]/C
(rising edge-triggered cell FDRE clocked by xclk {rise@0.000ns fall@2.083ns period=4.167ns})
Destination: compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[3].dly01_16_i/sr_reg[2]_srl2/D
(rising edge-triggered cell SRL16E clocked by xclk {rise@0.000ns fall@2.083ns period=4.167ns})
Path Group: xclk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (xclk rise@0.000ns - xclk rise@0.000ns)
Data Path Delay: 0.155ns (logic 0.100ns (64.432%) route 0.055ns (35.568%))
Logic Levels: 0
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.353ns
Source Clock Delay (SCD): 1.848ns
Clock Pessimism Removal (CPR): 0.494ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock xclk rise edge) 0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.604 0.604 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
0.050 0.654 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
net (fo=1, routed) 0.577 1.231 clocks393_i/xclk_i/xclk_pre
BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.257 r clocks393_i/xclk_i/clk1x_i/O
net (fo=13491, routed) 0.591 1.848 compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[3].dly01_16_i/xclk
SLICE_X63Y14 FDRE r compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[3].dly01_16_i/sr_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X63Y14 FDRE (Prop_fdre_C_Q) 0.100 1.948 r compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[3].dly01_16_i/sr_reg[0]/Q
net (fo=1, routed) 0.055 2.003 compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[3].dly01_16_i/sr_reg_n_0_[0]
SLICE_X62Y14 SRL16E r compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[3].dly01_16_i/sr_reg[2]_srl2/D
------------------------------------------------------------------- -------------------
(clock xclk rise edge) 0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.816 0.816 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
0.053 0.869 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
net (fo=1, routed) 0.643 1.512 clocks393_i/xclk_i/xclk_pre
BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.542 r clocks393_i/xclk_i/clk1x_i/O
net (fo=13491, routed) 0.811 2.353 compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[3].dly01_16_i/xclk
SLICE_X62Y14 SRL16E r compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[3].dly01_16_i/sr_reg[2]_srl2/CLK
clock pessimism -0.494 1.859
SLICE_X62Y14 SRL16E (Hold_srl16e_CLK_D)
0.102 1.961 compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[3].dly01_16_i/sr_reg[2]_srl2
-------------------------------------------------------------------
required time -1.961
arrival time 2.003
-------------------------------------------------------------------
slack 0.042
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: xclk
Waveform(ns): { 0.000 2.083 }
Period(ns): 4.167
Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a DSP48E1/CLK n/a 3.292 4.167 0.875 DSP48_X3Y5 compressor393_i/cmprs_channel_block[0].jp_channel_i/focus_sharp393_i/mult_p_r_reg/CLK
Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 4.167 155.833 PLLE2_ADV_X1Y1 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
Low Pulse Width Slow RAMD32/CLK n/a 0.910 2.083 1.173 SLICE_X58Y51 compressor393_i/cmprs_channel_block[3].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[0].fifo_same_clock_i/ram_reg_0_15_6_8/RAMA/CLK
High Pulse Width Fast RAMD32/CLK n/a 0.910 2.083 1.173 SLICE_X58Y51 compressor393_i/cmprs_channel_block[3].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[0].fifo_same_clock_i/ram_reg_0_15_6_8/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: clk_boson0
To Clock: clk_boson0
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 13.518ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_boson0
Waveform(ns): { 0.000 18.518 }
Period(ns): 37.037
Sources: { sns1_clkp }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 37.037 35.788 MMCME2_ADV_X0Y0 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKIN1
Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 37.037 62.963 MMCME2_ADV_X0Y0 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKIN1
Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 5.000 18.518 13.518 MMCME2_ADV_X0Y0 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKIN1
High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 5.000 18.518 13.518 MMCME2_ADV_X0Y0 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKIN1
---------------------------------------------------------------------------------------------------
From Clock: clk_fb_pre
To Clock: clk_fb_pre
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 35.788ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_fb_pre
Waveform(ns): { 0.000 18.518 }
Period(ns): 37.037
Sources: { sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 37.037 35.788 MMCME2_ADV_X0Y0 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKFBOUT
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 37.037 62.963 MMCME2_ADV_X0Y0 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: iclk0
To Clock: iclk0
Setup : 0 Failing Endpoints, Worst Slack 30.657ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.055ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 17.608ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 30.657ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/mul1_p_reg/CLK
(rising edge-triggered cell DSP48E1 clocked by iclk0 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/mul2_p_reg/B[11]
(rising edge-triggered cell DSP48E1 clocked by iclk0 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 37.037ns (iclk0 rise@66.821ns - iclk0 rise@29.784ns)
Data Path Delay: 5.830ns (logic 2.036ns (34.922%) route 3.794ns (65.078%))
Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1)
Clock Path Skew: -0.013ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.918ns = ( 70.739 - 66.821 )
Source Clock Delay (SCD): 4.334ns = ( 34.118 - 29.784 )
Clock Pessimism Removal (CPR): 0.402ns
Clock Uncertainty: 0.156ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk0 rise edge) 29.784 29.784 r
AA10 0.000 29.784 r sns1_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.910 30.694 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.085 31.779 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.088 31.867 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 1.106 32.973 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y1 BUFR (Prop_bufr_I_O) 0.377 33.350 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.767 34.118 sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/rst_early_master_reg
DSP48_X0Y10 DSP48E1 r sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/mul1_p_reg/CLK
------------------------------------------------------------------- -------------------
DSP48_X0Y10 DSP48E1 (Prop_dsp48e1_CLK_P[27])
1.877 35.995 r sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/mul1_p_reg/P[27]
net (fo=8, routed) 1.183 37.177 sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/mul1_p_reg_n_78
SLICE_X8Y30 LUT6 (Prop_lut6_I1_O) 0.053 37.230 r sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_85/O
net (fo=3, routed) 0.685 37.915 sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_85_n_0
SLICE_X6Y29 LUT5 (Prop_lut5_I2_O) 0.053 37.968 r sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_43/O
net (fo=13, routed) 1.361 39.329 sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_43_n_0
SLICE_X13Y27 LUT4 (Prop_lut4_I1_O) 0.053 39.382 r sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_7/O
net (fo=1, routed) 0.566 39.948 sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/mult_first_scaled[11]
DSP48_X0Y12 DSP48E1 r sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/mul2_p_reg/B[11]
------------------------------------------------------------------- -------------------
(clock iclk0 rise edge) 66.821 66.821 r
AA10 0.000 66.821 r sns1_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.831 67.652 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.887 68.539 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.083 68.622 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 1.016 69.638 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y1 BUFR (Prop_bufr_I_O) 0.370 70.008 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.731 70.739 sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/rst_early_master_reg
DSP48_X0Y12 DSP48E1 r sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/mul2_p_reg/CLK
clock pessimism 0.402 71.142
clock uncertainty -0.156 70.985
DSP48_X0Y12 DSP48E1 (Setup_dsp48e1_CLK_B[11])
-0.381 70.604 sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/mul2_p_reg
-------------------------------------------------------------------
required time 70.604
arrival time -39.948
-------------------------------------------------------------------
slack 30.657
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.055ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/pxd_out_reg[10]/C
(rising edge-triggered cell FDRE clocked by iclk0 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_gamma_i/gamma_table1_i/ram_i/RAMB36E1_i/ADDRARDADDR[6]
(rising edge-triggered cell RAMB36E1 clocked by iclk0 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (iclk0 rise@29.784ns - iclk0 rise@29.784ns)
Data Path Delay: 0.285ns (logic 0.118ns (41.442%) route 0.167ns (58.558%))
Logic Levels: 0
Clock Path Skew: 0.047ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.085ns = ( 31.869 - 29.784 )
Source Clock Delay (SCD): 1.775ns = ( 31.559 - 29.784 )
Clock Pessimism Removal (CPR): 0.263ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk0 rise edge) 29.784 29.784 r
AA10 0.000 29.784 r sns1_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.412 30.196 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.487 30.683 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.050 30.733 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 0.433 31.166 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y1 BUFR (Prop_bufr_I_O) 0.090 31.256 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.303 31.559 sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/rst_early_master_reg
SLICE_X22Y32 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/pxd_out_reg[10]/C
------------------------------------------------------------------- -------------------
SLICE_X22Y32 FDRE (Prop_fdre_C_Q) 0.118 31.677 r sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/pxd_out_reg[10]/Q
net (fo=4, routed) 0.167 31.844 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_gamma_i/gamma_table1_i/ram_i/ADDRARDADDR[2]
RAMB36_X1Y6 RAMB36E1 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_gamma_i/gamma_table1_i/ram_i/RAMB36E1_i/ADDRARDADDR[6]
------------------------------------------------------------------- -------------------
(clock iclk0 rise edge) 29.784 29.784 r
AA10 0.000 29.784 r sns1_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.481 30.265 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.593 30.858 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.053 30.911 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 0.490 31.401 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y1 BUFR (Prop_bufr_I_O) 0.093 31.494 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.375 31.869 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_gamma_i/gamma_table1_i/ram_i/rst_early_master_reg
RAMB36_X1Y6 RAMB36E1 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_gamma_i/gamma_table1_i/ram_i/RAMB36E1_i/CLKARDCLK
clock pessimism -0.263 31.606
RAMB36_X1Y6 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[6])
0.183 31.789 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_gamma_i/gamma_table1_i/ram_i/RAMB36E1_i
-------------------------------------------------------------------
required time -31.789
arrival time 31.844
-------------------------------------------------------------------
slack 0.055
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: iclk0
Waveform(ns): { -7.253 11.265 }
Period(ns): 37.037
Sources: { sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a DSP48E1/CLK n/a 3.124 37.037 33.913 DSP48_X2Y12 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_gamma_i/table_mult/CLK
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 37.037 176.323 MMCME2_ADV_X0Y0 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
Low Pulse Width Slow RAMD32/CLK n/a 0.910 18.518 17.608 SLICE_X30Y46 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK
High Pulse Width Fast RAMD32/CLK n/a 0.910 18.518 17.608 SLICE_X30Y46 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: iclk1x0
To Clock: iclk1x0
Setup : 0 Failing Endpoints, Worst Slack 12.312ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.140ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 7.007ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 12.312ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
(rising edge-triggered cell FDRE clocked by iclk1x0 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[1]/D
(rising edge-triggered cell FDRE clocked by iclk1x0 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 14.815ns (iclk1x0 rise@22.377ns - iclk1x0 rise@7.562ns)
Data Path Delay: 2.116ns (logic 0.333ns (15.736%) route 1.783ns (84.264%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: -0.106ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.803ns = ( 26.180 - 22.377 )
Source Clock Delay (SCD): 4.288ns = ( 11.850 - 7.562 )
Clock Pessimism Removal (CPR): 0.379ns
Clock Uncertainty: 0.135ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.261ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x0 rise edge) 7.562 7.562 r
AA10 0.000 7.562 r sns1_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.910 8.472 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.085 9.557 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.088 9.645 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.106 10.751 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y0 BUFR (Prop_bufr_I_O) 0.377 11.128 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.722 11.850 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X13Y43 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X13Y43 FDRE (Prop_fdre_C_Q) 0.269 12.119 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/Q
net (fo=30, routed) 1.509 13.629 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/p_0_in
SLICE_X3Y37 LUT2 (Prop_lut2_I0_O) 0.064 13.693 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[1]_i_1/O
net (fo=1, routed) 0.274 13.966 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[1]_i_1_n_0
SLICE_X5Y36 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[1]/D
------------------------------------------------------------------- -------------------
(clock iclk1x0 rise edge) 22.377 22.377 r
AA10 0.000 22.377 r sns1_clkp (IN)
net (fo=0) 0.000 22.377 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.831 23.208 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.887 24.095 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.083 24.178 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.016 25.194 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y0 BUFR (Prop_bufr_I_O) 0.370 25.564 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.616 26.180 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X5Y36 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[1]/C
clock pessimism 0.379 26.559
clock uncertainty -0.135 26.424
SLICE_X5Y36 FDRE (Setup_fdre_C_D) -0.145 26.279 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[1]
-------------------------------------------------------------------
required time 26.279
arrival time -13.966
-------------------------------------------------------------------
slack 12.312
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.140ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/deser_r_reg[2]/C
(rising edge-triggered cell FDRE clocked by iclk1x0 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/deser_r_reg[6]/D
(rising edge-triggered cell FDRE clocked by iclk1x0 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (iclk1x0 rise@7.562ns - iclk1x0 rise@7.562ns)
Data Path Delay: 0.185ns (logic 0.118ns (63.889%) route 0.067ns (36.111%))
Logic Levels: 0
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.021ns = ( 9.583 - 7.562 )
Source Clock Delay (SCD): 1.746ns = ( 9.308 - 7.562 )
Clock Pessimism Removal (CPR): 0.275ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x0 rise edge) 7.562 7.562 r
AA10 0.000 7.562 r sns1_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.412 7.974 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.487 8.461 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.050 8.511 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.433 8.944 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y0 BUFR (Prop_bufr_I_O) 0.090 9.034 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.274 9.308 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/CLK
SLICE_X4Y39 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/deser_r_reg[2]/C
------------------------------------------------------------------- -------------------
SLICE_X4Y39 FDRE (Prop_fdre_C_Q) 0.118 9.426 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/deser_r_reg[2]/Q
net (fo=3, routed) 0.067 9.492 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/D[6]
SLICE_X4Y39 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/deser_r_reg[6]/D
------------------------------------------------------------------- -------------------
(clock iclk1x0 rise edge) 7.562 7.562 r
AA10 0.000 7.562 r sns1_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.481 8.043 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.593 8.636 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.053 8.689 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.490 9.179 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y0 BUFR (Prop_bufr_I_O) 0.093 9.272 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.311 9.583 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/CLK
SLICE_X4Y39 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/deser_r_reg[6]/C
clock pessimism -0.275 9.308
SLICE_X4Y39 FDRE (Hold_fdre_C_D) 0.045 9.353 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/deser_r_reg[6]
-------------------------------------------------------------------
required time -9.353
arrival time 9.492
-------------------------------------------------------------------
slack 0.140
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: iclk1x0
Waveform(ns): { -7.253 0.154 }
Period(ns): 14.815
Sources: { sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFR/I n/a 2.221 14.815 12.594 BUFR_X0Y0 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/I
Max Period n/a MMCME2_ADV/CLKOUT2 n/a 213.360 14.815 198.545 MMCME2_ADV_X0Y0 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
Low Pulse Width Slow FDRE/C n/a 0.400 7.407 7.007 SLICE_X5Y36 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/deser_r_reg[0]/C
High Pulse Width Fast FDRE/C n/a 0.350 7.407 7.057 SLICE_X13Y43 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
---------------------------------------------------------------------------------------------------
From Clock: iclk2x0
To Clock: iclk2x0
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 6.000ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: iclk2x0
Waveform(ns): { -7.253 -3.549 }
Period(ns): 7.407
Sources: { sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFIO/I n/a 1.408 7.407 6.000 BUFIO_X0Y1 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i/I
Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 7.407 205.953 MMCME2_ADV_X0Y0 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT1
---------------------------------------------------------------------------------------------------
From Clock: clk_boson1
To Clock: clk_boson1
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 13.518ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_boson1
Waveform(ns): { 0.000 18.518 }
Period(ns): 37.037
Sources: { sns2_clkp }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 37.037 35.788 PLLE2_ADV_X0Y1 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKIN1
Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 37.037 15.596 PLLE2_ADV_X0Y1 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 5.000 18.518 13.518 PLLE2_ADV_X0Y1 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKIN1
High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 5.000 18.518 13.518 PLLE2_ADV_X0Y1 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKIN1
---------------------------------------------------------------------------------------------------
From Clock: clk_fb_pre_1
To Clock: clk_fb_pre_1
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 15.596ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_fb_pre_1
Waveform(ns): { 0.000 18.518 }
Period(ns): 37.037
Sources: { sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 37.037 35.788 PLLE2_ADV_X0Y1 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKFBOUT
Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 37.037 15.596 PLLE2_ADV_X0Y1 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: iclk1
To Clock: iclk1
Setup : 0 Failing Endpoints, Worst Slack 29.797ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.042ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 17.608ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 29.797ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/sub_frame_reg[0]/C
(rising edge-triggered cell FDRE clocked by iclk1 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/mul2_p_reg/B[1]
(rising edge-triggered cell DSP48E1 clocked by iclk1 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 37.037ns (iclk1 rise@66.821ns - iclk1 rise@29.784ns)
Data Path Delay: 6.742ns (logic 0.691ns (10.250%) route 6.051ns (89.750%))
Logic Levels: 4 (LUT4=1 LUT5=1 LUT6=1 RAMD32=1)
Clock Path Skew: 0.038ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.932ns = ( 72.752 - 66.821 )
Source Clock Delay (SCD): 6.523ns = ( 36.307 - 29.784 )
Clock Pessimism Removal (CPR): 0.630ns
Clock Uncertainty: 0.156ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1 rise edge) 29.784 29.784 r
Y16 0.000 29.784 r sns2_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.857 30.641 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 2.173 32.814 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.088 32.902 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.633 34.535 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.120 34.655 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 1.652 36.307 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/den_r_reg
SLICE_X24Y2 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/sub_frame_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X24Y2 FDRE (Prop_fdre_C_Q) 0.246 36.553 r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/sub_frame_reg[0]/Q
net (fo=47, routed) 1.471 38.023 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/post_scale_ram_reg_0_3_0_2/ADDRA0
SLICE_X22Y8 RAMD32 (Prop_ramd32_RADR0_O)
0.171 38.194 r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/post_scale_ram_reg_0_3_0_2/RAMA/O
net (fo=64, routed) 2.230 40.425 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/p_8_in[0]
SLICE_X30Y13 LUT6 (Prop_lut6_I4_O) 0.168 40.593 r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_92__0/O
net (fo=1, routed) 0.331 40.924 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_92__0_n_0
SLICE_X30Y13 LUT5 (Prop_lut5_I4_O) 0.053 40.977 r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_43__0/O
net (fo=13, routed) 1.348 42.324 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_43__0_n_0
SLICE_X17Y11 LUT4 (Prop_lut4_I1_O) 0.053 42.377 r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_17__0/O
net (fo=1, routed) 0.671 43.048 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/mult_first_scaled[1]
DSP48_X1Y3 DSP48E1 r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/mul2_p_reg/B[1]
------------------------------------------------------------------- -------------------
(clock iclk1 rise edge) 66.821 66.821 r
Y16 0.000 66.821 r sns2_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.779 67.600 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.801 69.400 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.083 69.483 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.550 71.033 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.113 71.146 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 1.606 72.752 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/den_r_reg
DSP48_X1Y3 DSP48E1 r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/mul2_p_reg/CLK
clock pessimism 0.630 73.382
clock uncertainty -0.156 73.226
DSP48_X1Y3 DSP48E1 (Setup_dsp48e1_CLK_B[1])
-0.381 72.845 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/mul2_p_reg
-------------------------------------------------------------------
required time 72.845
arrival time -43.048
-------------------------------------------------------------------
slack 29.797
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.042ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_sof_eof_i/bit_block[1].dly01_16_i/sr_reg[0]/C
(rising edge-triggered cell FDRE clocked by iclk1 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_sof_eof_i/bit_block[1].dly01_16_i/sr_reg[12]_srl12/D
(rising edge-triggered cell SRL16E clocked by iclk1 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (iclk1 rise@29.784ns - iclk1 rise@29.784ns)
Data Path Delay: 0.155ns (logic 0.100ns (64.433%) route 0.055ns (35.568%))
Logic Levels: 0
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 3.178ns = ( 32.962 - 29.784 )
Source Clock Delay (SCD): 2.619ns = ( 32.403 - 29.784 )
Clock Pessimism Removal (CPR): 0.548ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1 rise edge) 29.784 29.784 r
Y16 0.000 29.784 r sns2_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.360 30.144 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.000 31.143 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.050 31.193 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.584 31.777 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.026 31.803 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.600 32.403 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_sof_eof_i/bit_block[1].dly01_16_i/den_r_reg
SLICE_X39Y4 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_sof_eof_i/bit_block[1].dly01_16_i/sr_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X39Y4 FDRE (Prop_fdre_C_Q) 0.100 32.503 r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_sof_eof_i/bit_block[1].dly01_16_i/sr_reg[0]/Q
net (fo=1, routed) 0.055 32.558 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_sof_eof_i/bit_block[1].dly01_16_i/sr_reg_n_0_[0]
SLICE_X38Y4 SRL16E r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_sof_eof_i/bit_block[1].dly01_16_i/sr_reg[12]_srl12/D
------------------------------------------------------------------- -------------------
(clock iclk1 rise edge) 29.784 29.784 r
Y16 0.000 29.784 r sns2_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.428 30.212 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.196 31.408 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.053 31.461 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.651 32.112 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.030 32.142 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.820 32.962 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_sof_eof_i/bit_block[1].dly01_16_i/den_r_reg
SLICE_X38Y4 SRL16E r sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_sof_eof_i/bit_block[1].dly01_16_i/sr_reg[12]_srl12/CLK
clock pessimism -0.548 32.414
SLICE_X38Y4 SRL16E (Hold_srl16e_CLK_D)
0.102 32.516 sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/dly_16_sof_eof_i/bit_block[1].dly01_16_i/sr_reg[12]_srl12
-------------------------------------------------------------------
required time -32.516
arrival time 32.558
-------------------------------------------------------------------
slack 0.042
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: iclk1
Waveform(ns): { -7.253 11.265 }
Period(ns): 37.037
Sources: { sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a DSP48E1/CLK n/a 3.124 37.037 33.913 DSP48_X1Y0 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_gamma_i/table_mult/CLK
Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 37.037 122.963 PLLE2_ADV_X0Y1 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
Low Pulse Width Fast RAMD32/CLK n/a 0.910 18.518 17.608 SLICE_X30Y17 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK
High Pulse Width Slow RAMD32/CLK n/a 0.910 18.518 17.608 SLICE_X30Y17 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: iclk1x1
To Clock: iclk1x1
Setup : 0 Failing Endpoints, Worst Slack 12.646ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.138ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 7.007ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 12.646ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/iserdes_pxd_i/iserdes_i/CLKDIV
(rising edge-triggered cell ISERDESE2 clocked by iclk1x1 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r_reg[1]/D
(rising edge-triggered cell FDRE clocked by iclk1x1 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 14.815ns (iclk1x1 rise@22.377ns - iclk1x1 rise@7.562ns)
Data Path Delay: 2.013ns (logic 0.626ns (31.094%) route 1.387ns (68.906%))
Logic Levels: 1 (LUT4=1)
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.867ns = ( 28.244 - 22.377 )
Source Clock Delay (SCD): 6.588ns = ( 14.150 - 7.562 )
Clock Pessimism Removal (CPR): 0.630ns
Clock Uncertainty: 0.135ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.261ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x1 rise edge) 7.562 7.562 r
Y16 0.000 7.562 r sns2_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.857 8.419 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 2.173 10.592 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.088 10.680 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 1.633 12.313 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y3 BUFG (Prop_bufg_I_O) 0.120 12.433 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 1.717 14.150 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/iserdes_pxd_i/CLK
ILOGIC_X0Y4 ISERDESE2 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/iserdes_pxd_i/iserdes_i/CLKDIV
------------------------------------------------------------------- -------------------
ILOGIC_X0Y4 ISERDESE2 (Prop_iserdese2_CLKDIV_Q4)
0.573 14.723 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/iserdes_pxd_i/iserdes_i/Q4
net (fo=3, routed) 1.387 16.110 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/D[2]
SLICE_X8Y10 LUT4 (Prop_lut4_I2_O) 0.053 16.163 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pre_dout_r[1]_i_1__2/O
net (fo=1, routed) 0.000 16.163 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/iclk_r_reg[2][0]
SLICE_X8Y10 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r_reg[1]/D
------------------------------------------------------------------- -------------------
(clock iclk1x1 rise edge) 22.377 22.377 r
Y16 0.000 22.377 r sns2_clkp (IN)
net (fo=0) 0.000 22.377 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.779 23.155 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.801 24.956 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.083 25.039 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 1.550 26.589 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y3 BUFG (Prop_bufg_I_O) 0.113 26.702 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 1.542 28.244 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/CLK
SLICE_X8Y10 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r_reg[1]/C
clock pessimism 0.630 28.874
clock uncertainty -0.135 28.738
SLICE_X8Y10 FDRE (Setup_fdre_C_D) 0.071 28.809 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r_reg[1]
-------------------------------------------------------------------
required time 28.809
arrival time -16.163
-------------------------------------------------------------------
slack 12.646
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.138ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/deser_r_reg[3]/C
(rising edge-triggered cell FDRE clocked by iclk1x1 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/deser_r_reg[7]/D
(rising edge-triggered cell FDRE clocked by iclk1x1 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (iclk1x1 rise@7.562ns - iclk1x1 rise@7.562ns)
Data Path Delay: 0.183ns (logic 0.118ns (64.311%) route 0.065ns (35.689%))
Logic Levels: 0
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 3.212ns = ( 10.774 - 7.562 )
Source Clock Delay (SCD): 2.652ns = ( 10.214 - 7.562 )
Clock Pessimism Removal (CPR): 0.560ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x1 rise edge) 7.562 7.562 r
Y16 0.000 7.562 r sns2_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.360 7.921 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.000 8.921 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.050 8.971 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 0.584 9.555 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y3 BUFG (Prop_bufg_I_O) 0.026 9.581 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.633 10.214 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/CLK
SLICE_X10Y12 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/deser_r_reg[3]/C
------------------------------------------------------------------- -------------------
SLICE_X10Y12 FDRE (Prop_fdre_C_Q) 0.118 10.332 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/deser_r_reg[3]/Q
net (fo=3, routed) 0.065 10.397 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/D[6]
SLICE_X10Y12 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/deser_r_reg[7]/D
------------------------------------------------------------------- -------------------
(clock iclk1x1 rise edge) 7.562 7.562 r
Y16 0.000 7.562 r sns2_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.428 7.990 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.196 9.186 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.053 9.239 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 0.651 9.890 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y3 BUFG (Prop_bufg_I_O) 0.030 9.920 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.854 10.774 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/CLK
SLICE_X10Y12 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/deser_r_reg[7]/C
clock pessimism -0.560 10.214
SLICE_X10Y12 FDRE (Hold_fdre_C_D) 0.045 10.259 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/deser_r_reg[7]
-------------------------------------------------------------------
required time -10.259
arrival time 10.397
-------------------------------------------------------------------
slack 0.138
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: iclk1x1
Waveform(ns): { -7.253 0.154 }
Period(ns): 14.815
Sources: { sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 1.600 14.815 13.215 BUFGCTRL_X0Y3 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/I
Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 14.815 145.185 PLLE2_ADV_X0Y1 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
Low Pulse Width Slow FDRE/C n/a 0.400 7.407 7.007 SLICE_X9Y9 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[2]/C
High Pulse Width Fast FDRE/C n/a 0.350 7.407 7.057 SLICE_X10Y12 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/deser_r_reg[0]/C
---------------------------------------------------------------------------------------------------
From Clock: iclk2x1
To Clock: iclk2x1
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 5.807ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: iclk2x1
Waveform(ns): { -7.253 -3.549 }
Period(ns): 7.407
Sources: { sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 1.600 7.407 5.807 BUFGCTRL_X0Y6 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i/I
Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 7.407 152.593 PLLE2_ADV_X0Y1 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT1
---------------------------------------------------------------------------------------------------
From Clock: clk_boson2
To Clock: clk_boson2
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 13.518ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_boson2
Waveform(ns): { 0.000 18.518 }
Period(ns): 37.037
Sources: { sns3_clkp }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 37.037 35.788 MMCME2_ADV_X0Y1 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKIN1
Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 37.037 62.963 MMCME2_ADV_X0Y1 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKIN1
Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 5.000 18.518 13.518 MMCME2_ADV_X0Y1 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKIN1
High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 5.000 18.518 13.518 MMCME2_ADV_X0Y1 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKIN1
---------------------------------------------------------------------------------------------------
From Clock: clk_fb_pre_2
To Clock: clk_fb_pre_2
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 35.788ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_fb_pre_2
Waveform(ns): { 0.000 18.518 }
Period(ns): 37.037
Sources: { sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 37.037 35.788 MMCME2_ADV_X0Y1 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKFBOUT
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 37.037 62.963 MMCME2_ADV_X0Y1 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: iclk1x2
To Clock: iclk1x2
Setup : 0 Failing Endpoints, Worst Slack 12.219ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.120ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 7.007ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 12.219ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/iserdes_pxd_i/iserdes_i/CLKDIV
(rising edge-triggered cell ISERDESE2 clocked by iclk1x2 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[0]/D
(rising edge-triggered cell FDRE clocked by iclk1x2 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x2
Path Type: Setup (Max at Slow Process Corner)
Requirement: 14.815ns (iclk1x2 rise@22.377ns - iclk1x2 rise@7.562ns)
Data Path Delay: 2.508ns (logic 0.626ns (24.958%) route 1.882ns (75.042%))
Logic Levels: 1 (LUT4=1)
Clock Path Skew: 0.013ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.825ns = ( 26.201 - 22.377 )
Source Clock Delay (SCD): 4.191ns = ( 11.753 - 7.562 )
Clock Pessimism Removal (CPR): 0.379ns
Clock Uncertainty: 0.135ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.261ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x2 rise edge) 7.562 7.562 r
T21 0.000 7.562 r sns3_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.880 8.441 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.085 9.527 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.088 9.615 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.106 10.721 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y4 BUFR (Prop_bufr_I_O) 0.377 11.098 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.655 11.753 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/iserdes_pxd_i/CLK
ILOGIC_X0Y90 ISERDESE2 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/iserdes_pxd_i/iserdes_i/CLKDIV
------------------------------------------------------------------- -------------------
ILOGIC_X0Y90 ISERDESE2 (Prop_iserdese2_CLKDIV_Q1)
0.573 12.326 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/iserdes_pxd_i/iserdes_i/Q1
net (fo=2, routed) 1.882 14.208 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/deser_r_reg[3]_0[0]
SLICE_X9Y66 LUT4 (Prop_lut4_I3_O) 0.053 14.261 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pre_dout_r[0]_i_1__1/O
net (fo=1, routed) 0.000 14.261 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/iclk_r_reg[2][0]
SLICE_X9Y66 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[0]/D
------------------------------------------------------------------- -------------------
(clock iclk1x2 rise edge) 22.377 22.377 r
T21 0.000 22.377 r sns3_clkp (IN)
net (fo=0) 0.000 22.377 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.801 23.177 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.887 24.064 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.083 24.147 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.016 25.163 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y4 BUFR (Prop_bufr_I_O) 0.370 25.533 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.668 26.201 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/CLK
SLICE_X9Y66 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[0]/C
clock pessimism 0.379 26.580
clock uncertainty -0.135 26.445
SLICE_X9Y66 FDRE (Setup_fdre_C_D) 0.035 26.480 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[0]
-------------------------------------------------------------------
required time 26.480
arrival time -14.261
-------------------------------------------------------------------
slack 12.219
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.120ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/deser_r_reg[2]/C
(rising edge-triggered cell FDRE clocked by iclk1x2 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/deser_r_reg[6]/D
(rising edge-triggered cell FDRE clocked by iclk1x2 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x2
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (iclk1x2 rise@7.562ns - iclk1x2 rise@7.562ns)
Data Path Delay: 0.167ns (logic 0.100ns (59.989%) route 0.067ns (40.011%))
Logic Levels: 0
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.988ns = ( 9.550 - 7.562 )
Source Clock Delay (SCD): 1.714ns = ( 9.275 - 7.562 )
Clock Pessimism Removal (CPR): 0.274ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x2 rise edge) 7.562 7.562 r
T21 0.000 7.562 r sns3_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.382 7.943 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.487 8.430 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.050 8.480 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.433 8.913 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y4 BUFR (Prop_bufr_I_O) 0.090 9.003 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.272 9.275 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/CLK
SLICE_X7Y63 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/deser_r_reg[2]/C
------------------------------------------------------------------- -------------------
SLICE_X7Y63 FDRE (Prop_fdre_C_Q) 0.100 9.375 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/deser_r_reg[2]/Q
net (fo=3, routed) 0.067 9.442 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/D[6]
SLICE_X7Y63 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/deser_r_reg[6]/D
------------------------------------------------------------------- -------------------
(clock iclk1x2 rise edge) 7.562 7.562 r
T21 0.000 7.562 r sns3_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.451 8.012 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.593 8.606 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.053 8.659 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.490 9.149 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y4 BUFR (Prop_bufr_I_O) 0.093 9.242 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.308 9.550 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/CLK
SLICE_X7Y63 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/deser_r_reg[6]/C
clock pessimism -0.274 9.275
SLICE_X7Y63 FDRE (Hold_fdre_C_D) 0.047 9.322 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/deser_r_reg[6]
-------------------------------------------------------------------
required time -9.322
arrival time 9.442
-------------------------------------------------------------------
slack 0.120
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: iclk1x2
Waveform(ns): { -7.253 0.154 }
Period(ns): 14.815
Sources: { sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFR/I n/a 2.221 14.815 12.594 BUFR_X0Y4 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/I
Max Period n/a MMCME2_ADV/CLKOUT2 n/a 213.360 14.815 198.545 MMCME2_ADV_X0Y1 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
Low Pulse Width Slow FDRE/C n/a 0.400 7.407 7.007 SLICE_X5Y67 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/pre_dout_r_reg[3]/C
High Pulse Width Fast FDRE/C n/a 0.350 7.407 7.057 SLICE_X9Y66 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[0]/C
---------------------------------------------------------------------------------------------------
From Clock: iclk2
To Clock: iclk2
Setup : 0 Failing Endpoints, Worst Slack 29.813ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.061ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 17.608ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 29.813ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/sub_frame_reg[0]/C
(rising edge-triggered cell FDRE clocked by iclk2 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul2_p_reg/B[12]
(rising edge-triggered cell DSP48E1 clocked by iclk2 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk2
Path Type: Setup (Max at Slow Process Corner)
Requirement: 37.037ns (iclk2 rise@66.821ns - iclk2 rise@29.784ns)
Data Path Delay: 6.708ns (logic 0.563ns (8.393%) route 6.145ns (91.607%))
Logic Levels: 4 (LUT4=1 LUT5=1 LUT6=1 RAMD32=1)
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.901ns = ( 70.722 - 66.821 )
Source Clock Delay (SCD): 4.259ns = ( 34.043 - 29.784 )
Clock Pessimism Removal (CPR): 0.379ns
Clock Uncertainty: 0.156ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk2 rise edge) 29.784 29.784 r
T21 0.000 29.784 r sns3_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.880 30.664 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.085 31.749 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.088 31.837 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 1.106 32.943 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y5 BUFR (Prop_bufr_I_O) 0.377 33.320 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.723 34.043 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/rst_early_master_reg
SLICE_X31Y64 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/sub_frame_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X31Y64 FDRE (Prop_fdre_C_Q) 0.246 34.289 r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/sub_frame_reg[0]/Q
net (fo=47, routed) 1.380 35.668 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/post_scale_ram_reg_0_3_0_2/ADDRA0
SLICE_X20Y61 RAMD32 (Prop_ramd32_RADR0_O)
0.158 35.826 r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/post_scale_ram_reg_0_3_0_2/RAMA_D1/O
net (fo=65, routed) 2.005 37.832 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/p_8_in[1]
SLICE_X26Y69 LUT6 (Prop_lut6_I3_O) 0.053 37.885 r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_92__1/O
net (fo=1, routed) 0.577 38.462 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_92__1_n_0
SLICE_X26Y69 LUT5 (Prop_lut5_I4_O) 0.053 38.515 r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_43__1/O
net (fo=13, routed) 1.423 39.938 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_43__1_n_0
SLICE_X24Y66 LUT4 (Prop_lut4_I1_O) 0.053 39.991 r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_6__1/O
net (fo=1, routed) 0.760 40.750 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mult_first_scaled[12]
DSP48_X1Y22 DSP48E1 r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul2_p_reg/B[12]
------------------------------------------------------------------- -------------------
(clock iclk2 rise edge) 66.821 66.821 r
T21 0.000 66.821 r sns3_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.801 67.622 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.887 68.509 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.083 68.592 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 1.016 69.608 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y5 BUFR (Prop_bufr_I_O) 0.370 69.978 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.744 70.722 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/rst_early_master_reg
DSP48_X1Y22 DSP48E1 r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul2_p_reg/CLK
clock pessimism 0.379 71.101
clock uncertainty -0.156 70.945
DSP48_X1Y22 DSP48E1 (Setup_dsp48e1_CLK_B[12])
-0.381 70.564 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/mul2_p_reg
-------------------------------------------------------------------
required time 70.564
arrival time -40.750
-------------------------------------------------------------------
slack 29.813
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.061ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[7].dly01_16_i/sr_reg[0]/C
(rising edge-triggered cell FDRE clocked by iclk2 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[7].dly01_16_i/sr_reg[9]_srl9/D
(rising edge-triggered cell SRL16E clocked by iclk2 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk2
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (iclk2 rise@29.784ns - iclk2 rise@29.784ns)
Data Path Delay: 0.190ns (logic 0.091ns (47.978%) route 0.099ns (52.022%))
Logic Levels: 0
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.025ns = ( 31.809 - 29.784 )
Source Clock Delay (SCD): 1.748ns = ( 31.532 - 29.784 )
Clock Pessimism Removal (CPR): 0.266ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk2 rise edge) 29.784 29.784 r
T21 0.000 29.784 r sns3_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.382 30.166 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.487 30.653 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.050 30.703 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 0.433 31.136 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y5 BUFR (Prop_bufr_I_O) 0.090 31.226 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.306 31.532 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[7].dly01_16_i/rst_early_master_reg
SLICE_X19Y59 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[7].dly01_16_i/sr_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X19Y59 FDRE (Prop_fdre_C_Q) 0.091 31.623 r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[7].dly01_16_i/sr_reg[0]/Q
net (fo=1, routed) 0.099 31.721 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[7].dly01_16_i/sr_reg_n_0_[0]
SLICE_X18Y59 SRL16E r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[7].dly01_16_i/sr_reg[9]_srl9/D
------------------------------------------------------------------- -------------------
(clock iclk2 rise edge) 29.784 29.784 r
T21 0.000 29.784 r sns3_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.451 30.235 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.593 30.828 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.053 30.881 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 0.490 31.371 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y5 BUFR (Prop_bufr_I_O) 0.093 31.464 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.345 31.809 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[7].dly01_16_i/rst_early_master_reg
SLICE_X18Y59 SRL16E r sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[7].dly01_16_i/sr_reg[9]_srl9/CLK
clock pessimism -0.266 31.543
SLICE_X18Y59 SRL16E (Hold_srl16e_CLK_D)
0.118 31.661 sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/dly_16_pxd_i/bit_block[7].dly01_16_i/sr_reg[9]_srl9
-------------------------------------------------------------------
required time -31.661
arrival time 31.721
-------------------------------------------------------------------
slack 0.061
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: iclk2
Waveform(ns): { -7.253 11.265 }
Period(ns): 37.037
Sources: { sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a DSP48E1/CLK n/a 3.124 37.037 33.913 DSP48_X2Y22 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_gamma_i/table_mult/CLK
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 37.037 176.323 MMCME2_ADV_X0Y1 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
Low Pulse Width Slow RAMD32/CLK n/a 0.910 18.518 17.608 SLICE_X30Y50 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK
High Pulse Width Slow RAMD32/CLK n/a 0.910 18.519 17.609 SLICE_X30Y50 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: iclk2x2
To Clock: iclk2x2
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 6.000ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: iclk2x2
Waveform(ns): { -7.253 -3.549 }
Period(ns): 7.407
Sources: { sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFIO/I n/a 1.408 7.407 6.000 BUFIO_X0Y5 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i/I
Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 7.407 205.953 MMCME2_ADV_X0Y1 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT1
---------------------------------------------------------------------------------------------------
From Clock: clk_boson3
To Clock: clk_boson3
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 13.518ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_boson3
Waveform(ns): { 0.000 18.518 }
Period(ns): 37.037
Sources: { sns4_clkp }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 37.037 35.788 PLLE2_ADV_X0Y0 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKIN1
Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 37.037 15.596 PLLE2_ADV_X0Y0 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 5.000 18.518 13.518 PLLE2_ADV_X0Y0 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKIN1
High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 5.000 18.518 13.518 PLLE2_ADV_X0Y0 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKIN1
---------------------------------------------------------------------------------------------------
From Clock: clk_fb_pre_3
To Clock: clk_fb_pre_3
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 15.596ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_fb_pre_3
Waveform(ns): { 0.000 18.518 }
Period(ns): 37.037
Sources: { sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 37.037 35.788 PLLE2_ADV_X0Y0 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKFBOUT
Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 37.037 15.596 PLLE2_ADV_X0Y0 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: iclk1x3
To Clock: iclk1x3
Setup : 0 Failing Endpoints, Worst Slack 12.029ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.150ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 7.007ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 12.029ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/iserdes_pxd_i/iserdes_i/CLKDIV
(rising edge-triggered cell ISERDESE2 clocked by iclk1x3 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/pre_dout_r_reg[1]/D
(rising edge-triggered cell FDRE clocked by iclk1x3 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x3
Path Type: Setup (Max at Slow Process Corner)
Requirement: 14.815ns (iclk1x3 rise@22.377ns - iclk1x3 rise@7.562ns)
Data Path Delay: 2.583ns (logic 0.626ns (24.235%) route 1.957ns (75.765%))
Logic Levels: 1 (LUT4=1)
Clock Path Skew: -0.102ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.463ns = ( 27.840 - 22.377 )
Source Clock Delay (SCD): 6.096ns = ( 13.658 - 7.562 )
Clock Pessimism Removal (CPR): 0.531ns
Clock Uncertainty: 0.135ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.261ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x3 rise edge) 7.562 7.562 r
R16 0.000 7.562 r sns4_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.856 8.417 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.502 9.919 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.088 10.007 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 2.009 12.016 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.120 12.136 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 1.522 13.658 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/iserdes_pxd_i/CLK
ILOGIC_X0Y52 ISERDESE2 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/iserdes_pxd_i/iserdes_i/CLKDIV
------------------------------------------------------------------- -------------------
ILOGIC_X0Y52 ISERDESE2 (Prop_iserdese2_CLKDIV_Q4)
0.573 14.231 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/iserdes_pxd_i/iserdes_i/Q4
net (fo=3, routed) 1.957 16.188 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/deser_r_reg[3][2]
SLICE_X27Y65 LUT4 (Prop_lut4_I2_O) 0.053 16.241 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pre_dout_r[1]_i_1__9/O
net (fo=1, routed) 0.000 16.241 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/iclk_r_reg[2][0]
SLICE_X27Y65 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/pre_dout_r_reg[1]/D
------------------------------------------------------------------- -------------------
(clock iclk1x3 rise edge) 22.377 22.377 r
R16 0.000 22.377 r sns4_clkp (IN)
net (fo=0) 0.000 22.377 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.777 23.153 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.242 24.395 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.083 24.478 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 1.911 26.389 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.113 26.502 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 1.338 27.840 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/CLK
SLICE_X27Y65 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/pre_dout_r_reg[1]/C
clock pessimism 0.531 28.371
clock uncertainty -0.135 28.235
SLICE_X27Y65 FDRE (Setup_fdre_C_D) 0.034 28.269 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/pre_dout_r_reg[1]
-------------------------------------------------------------------
required time 28.269
arrival time -16.241
-------------------------------------------------------------------
slack 12.029
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.150ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/deser_r_reg[5]/C
(rising edge-triggered cell FDRE clocked by iclk1x3 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/pre_dout_r_reg[7]/D
(rising edge-triggered cell FDRE clocked by iclk1x3 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x3
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (iclk1x3 rise@7.562ns - iclk1x3 rise@7.562ns)
Data Path Delay: 0.236ns (logic 0.148ns (62.828%) route 0.088ns (37.172%))
Logic Levels: 1 (LUT4=1)
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.963ns = ( 10.525 - 7.562 )
Source Clock Delay (SCD): 2.480ns = ( 10.042 - 7.562 )
Clock Pessimism Removal (CPR): 0.472ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x3 rise edge) 7.562 7.562 r
R16 0.000 7.562 r sns4_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.358 7.920 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.701 8.620 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.050 8.670 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 0.771 9.441 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.026 9.467 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.575 10.042 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/CLK
SLICE_X26Y65 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/deser_r_reg[5]/C
------------------------------------------------------------------- -------------------
SLICE_X26Y65 FDRE (Prop_fdre_C_Q) 0.118 10.160 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/deser_r_reg[5]/Q
net (fo=2, routed) 0.088 10.248 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/deser_r_reg[7]_0[1]
SLICE_X27Y65 LUT4 (Prop_lut4_I2_O) 0.030 10.278 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pre_dout_r[7]_i_1__9/O
net (fo=1, routed) 0.000 10.278 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/iclk_r_reg[2][6]
SLICE_X27Y65 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/pre_dout_r_reg[7]/D
------------------------------------------------------------------- -------------------
(clock iclk1x3 rise edge) 7.562 7.562 r
R16 0.000 7.562 r sns4_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.427 7.988 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.840 8.828 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.053 8.881 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 0.840 9.721 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.030 9.751 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.774 10.525 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/CLK
SLICE_X27Y65 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/pre_dout_r_reg[7]/C
clock pessimism -0.472 10.053
SLICE_X27Y65 FDRE (Hold_fdre_C_D) 0.075 10.128 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/pre_dout_r_reg[7]
-------------------------------------------------------------------
required time -10.128
arrival time 10.278
-------------------------------------------------------------------
slack 0.150
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: iclk1x3
Waveform(ns): { -7.253 0.154 }
Period(ns): 14.815
Sources: { sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 1.600 14.815 13.215 BUFGCTRL_X0Y4 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/I
Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 14.815 145.185 PLLE2_ADV_X0Y0 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
Low Pulse Width Slow FDRE/C n/a 0.400 7.407 7.007 SLICE_X31Y66 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[2]/C
High Pulse Width Slow FDRE/C n/a 0.350 7.407 7.057 SLICE_X28Y67 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r_reg[5]/C
---------------------------------------------------------------------------------------------------
From Clock: iclk2x3
To Clock: iclk2x3
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 5.807ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: iclk2x3
Waveform(ns): { -7.253 -3.549 }
Period(ns): 7.407
Sources: { sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 1.600 7.407 5.807 BUFGCTRL_X0Y7 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i/I
Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 7.407 152.593 PLLE2_ADV_X0Y0 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT1
---------------------------------------------------------------------------------------------------
From Clock: iclk3
To Clock: iclk3
Setup : 0 Failing Endpoints, Worst Slack 29.987ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.085ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 17.608ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 29.987ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/mul1_p_reg/CLK
(rising edge-triggered cell DSP48E1 clocked by iclk3 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/mul2_p_reg/B[6]
(rising edge-triggered cell DSP48E1 clocked by iclk3 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk3
Path Type: Setup (Max at Slow Process Corner)
Requirement: 37.037ns (iclk3 rise@66.821ns - iclk3 rise@29.784ns)
Data Path Delay: 6.487ns (logic 2.036ns (31.387%) route 4.451ns (68.613%))
Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1)
Clock Path Skew: -0.026ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.668ns = ( 72.489 - 66.821 )
Source Clock Delay (SCD): 6.226ns = ( 36.010 - 29.784 )
Clock Pessimism Removal (CPR): 0.533ns
Clock Uncertainty: 0.156ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk3 rise edge) 29.784 29.784 r
R16 0.000 29.784 r sns4_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.856 30.639 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.502 32.141 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.088 32.229 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 2.009 34.238 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y12 BUFG (Prop_bufg_I_O) 0.120 34.358 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 1.652 36.010 sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/den_r_reg
DSP48_X3Y16 DSP48E1 r sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/mul1_p_reg/CLK
------------------------------------------------------------------- -------------------
DSP48_X3Y16 DSP48E1 (Prop_dsp48e1_CLK_P[28])
1.877 37.887 r sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/mul1_p_reg/P[28]
net (fo=12, routed) 1.494 39.382 sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/mul1_p_reg_n_77
SLICE_X45Y44 LUT6 (Prop_lut6_I5_O) 0.053 39.435 r sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_92__2/O
net (fo=1, routed) 0.689 40.124 sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_92__2_n_0
SLICE_X48Y45 LUT5 (Prop_lut5_I4_O) 0.053 40.177 r sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_43__2/O
net (fo=13, routed) 1.376 41.552 sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_43__2_n_0
SLICE_X56Y40 LUT4 (Prop_lut4_I1_O) 0.053 41.605 r sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/mul2_p_reg_i_12__2/O
net (fo=1, routed) 0.892 42.497 sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/mult_first_scaled[6]
DSP48_X2Y16 DSP48E1 r sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/mul2_p_reg/B[6]
------------------------------------------------------------------- -------------------
(clock iclk3 rise edge) 66.821 66.821 r
R16 0.000 66.821 r sns4_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.777 67.598 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.242 68.839 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.083 68.922 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.911 70.833 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y12 BUFG (Prop_bufg_I_O) 0.113 70.946 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 1.542 72.489 sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/den_r_reg
DSP48_X2Y16 DSP48E1 r sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/mul2_p_reg/CLK
clock pessimism 0.533 73.021
clock uncertainty -0.156 72.865
DSP48_X2Y16 DSP48E1 (Setup_dsp48e1_CLK_B[6])
-0.381 72.484 sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/mul2_p_reg
-------------------------------------------------------------------
required time 72.484
arrival time -42.497
-------------------------------------------------------------------
slack 29.987
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.085ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/rwen_even_reg/C
(rising edge-triggered cell FDRE clocked by iclk3 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/sens_hist_ram_snglclk_32_i/ramt_var_w_var_r_even_i/RAMB36E1_i/ENARDEN
(rising edge-triggered cell RAMB36E1 clocked by iclk3 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk3
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (iclk3 rise@29.784ns - iclk3 rise@29.784ns)
Data Path Delay: 0.228ns (logic 0.100ns (43.856%) route 0.128ns (56.144%))
Logic Levels: 0
Clock Path Skew: 0.047ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 3.032ns = ( 32.816 - 29.784 )
Source Clock Delay (SCD): 2.494ns = ( 32.278 - 29.784 )
Clock Pessimism Removal (CPR): 0.491ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk3 rise edge) 29.784 29.784 r
R16 0.000 29.784 r sns4_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.358 30.142 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.701 30.842 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.050 30.892 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.771 31.663 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y12 BUFG (Prop_bufg_I_O) 0.026 31.689 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.589 32.278 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/den_r_reg
SLICE_X33Y27 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/rwen_even_reg/C
------------------------------------------------------------------- -------------------
SLICE_X33Y27 FDRE (Prop_fdre_C_Q) 0.100 32.378 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/rwen_even_reg/Q
net (fo=1, routed) 0.128 32.506 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/sens_hist_ram_snglclk_32_i/ramt_var_w_var_r_even_i/rwen_even
RAMB36_X2Y5 RAMB36E1 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/sens_hist_ram_snglclk_32_i/ramt_var_w_var_r_even_i/RAMB36E1_i/ENARDEN
------------------------------------------------------------------- -------------------
(clock iclk3 rise edge) 29.784 29.784 r
R16 0.000 29.784 r sns4_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.427 30.210 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.840 31.050 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.053 31.103 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.840 31.943 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y12 BUFG (Prop_bufg_I_O) 0.030 31.973 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.843 32.816 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/sens_hist_ram_snglclk_32_i/ramt_var_w_var_r_even_i/den_r_reg
RAMB36_X2Y5 RAMB36E1 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/sens_hist_ram_snglclk_32_i/ramt_var_w_var_r_even_i/RAMB36E1_i/CLKARDCLK
clock pessimism -0.491 32.325
RAMB36_X2Y5 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ENARDEN)
0.096 32.421 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/sens_hist_ram_snglclk_32_i/ramt_var_w_var_r_even_i/RAMB36E1_i
-------------------------------------------------------------------
required time -32.421
arrival time 32.506
-------------------------------------------------------------------
slack 0.085
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: iclk3
Waveform(ns): { -7.253 11.265 }
Period(ns): 37.037
Sources: { sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a DSP48E1/CLK n/a 3.124 37.037 33.913 DSP48_X2Y13 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_gamma_i/table_mult/CLK
Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 37.037 122.963 PLLE2_ADV_X0Y0 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
Low Pulse Width Fast RAMD32/CLK n/a 0.910 18.518 17.608 SLICE_X34Y30 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK
High Pulse Width Slow RAMD32/CLK n/a 0.910 18.519 17.609 SLICE_X34Y30 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: ffclk0
To Clock: ffclk0
Setup : 0 Failing Endpoints, Worst Slack 39.562ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.843ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 20.483ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 39.562ns (required time - arrival time)
Source: clocks393_i/test_clk_reg[1]/C
(rising edge-triggered cell FDCE clocked by ffclk0 {rise@0.000ns fall@20.833ns period=41.667ns})
Destination: clocks393_i/test_clk_reg[1]/D
(rising edge-triggered cell FDCE clocked by ffclk0 {rise@0.000ns fall@20.833ns period=41.667ns})
Path Group: ffclk0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 41.667ns (ffclk0 rise@41.667ns - ffclk0 rise@0.000ns)
Data Path Delay: 2.141ns (logic 0.361ns (16.865%) route 1.780ns (83.135%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.756ns = ( 45.423 - 41.667 )
Source Clock Delay (SCD): 4.440ns
Clock Pessimism Removal (CPR): 0.683ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ffclk0 rise edge) 0.000 0.000 r
Y12 0.000 0.000 r ffclk0p (IN)
net (fo=0) 0.000 0.000 clocks393_i/ibufds_ibufgds0_i/ffclk0p
Y12 IBUFDS (Prop_ibufds_I_O) 0.906 0.906 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 3.534 4.440 clocks393_i/ffclk0
SLICE_X48Y135 FDCE r clocks393_i/test_clk_reg[1]/C
------------------------------------------------------------------- -------------------
SLICE_X48Y135 FDCE (Prop_fdce_C_Q) 0.308 4.748 f clocks393_i/test_clk_reg[1]/Q
net (fo=4, routed) 1.780 6.527 clocks393_i/test_clk_reg
SLICE_X48Y135 LUT1 (Prop_lut1_I0_O) 0.053 6.580 r clocks393_i/test_clk[1]_i_1/O
net (fo=1, routed) 0.000 6.580 clocks393_i/test_clk[1]_i_1_n_0
SLICE_X48Y135 FDCE r clocks393_i/test_clk_reg[1]/D
------------------------------------------------------------------- -------------------
(clock ffclk0 rise edge) 41.667 41.667 r
Y12 0.000 41.667 r ffclk0p (IN)
net (fo=0) 0.000 41.667 clocks393_i/ibufds_ibufgds0_i/ffclk0p
Y12 IBUFDS (Prop_ibufds_I_O) 0.827 42.494 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 2.930 45.423 clocks393_i/ffclk0
SLICE_X48Y135 FDCE r clocks393_i/test_clk_reg[1]/C
clock pessimism 0.683 46.107
clock uncertainty -0.035 46.071
SLICE_X48Y135 FDCE (Setup_fdce_C_D) 0.071 46.142 clocks393_i/test_clk_reg[1]
-------------------------------------------------------------------
required time 46.142
arrival time -6.580
-------------------------------------------------------------------
slack 39.562
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.843ns (arrival time - required time)
Source: clocks393_i/test_clk_reg[1]/C
(rising edge-triggered cell FDCE clocked by ffclk0 {rise@0.000ns fall@20.833ns period=41.667ns})
Destination: clocks393_i/test_clk_reg[1]/D
(rising edge-triggered cell FDCE clocked by ffclk0 {rise@0.000ns fall@20.833ns period=41.667ns})
Path Group: ffclk0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (ffclk0 rise@0.000ns - ffclk0 rise@0.000ns)
Data Path Delay: 0.930ns (logic 0.146ns (15.707%) route 0.784ns (84.293%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.424ns
Source Clock Delay (SCD): 2.028ns
Clock Pessimism Removal (CPR): 0.395ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ffclk0 rise edge) 0.000 0.000 r
Y12 0.000 0.000 r ffclk0p (IN)
net (fo=0) 0.000 0.000 clocks393_i/ibufds_ibufgds0_i/ffclk0p
Y12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.583 2.028 clocks393_i/ffclk0
SLICE_X48Y135 FDCE r clocks393_i/test_clk_reg[1]/C
------------------------------------------------------------------- -------------------
SLICE_X48Y135 FDCE (Prop_fdce_C_Q) 0.118 2.146 f clocks393_i/test_clk_reg[1]/Q
net (fo=4, routed) 0.784 2.930 clocks393_i/test_clk_reg
SLICE_X48Y135 LUT1 (Prop_lut1_I0_O) 0.028 2.958 r clocks393_i/test_clk[1]_i_1/O
net (fo=1, routed) 0.000 2.958 clocks393_i/test_clk[1]_i_1_n_0
SLICE_X48Y135 FDCE r clocks393_i/test_clk_reg[1]/D
------------------------------------------------------------------- -------------------
(clock ffclk0 rise edge) 0.000 0.000 r
Y12 0.000 0.000 r ffclk0p (IN)
net (fo=0) 0.000 0.000 clocks393_i/ibufds_ibufgds0_i/ffclk0p
Y12 IBUFDS (Prop_ibufds_I_O) 0.521 0.521 r clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.903 2.424 clocks393_i/ffclk0
SLICE_X48Y135 FDCE r clocks393_i/test_clk_reg[1]/C
clock pessimism -0.395 2.028
SLICE_X48Y135 FDCE (Hold_fdce_C_D) 0.087 2.115 clocks393_i/test_clk_reg[1]
-------------------------------------------------------------------
required time -2.115
arrival time 2.958
-------------------------------------------------------------------
slack 0.843
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ffclk0
Waveform(ns): { 0.000 20.833 }
Period(ns): 41.667
Sources: { ffclk0p }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a FDCE/C n/a 0.700 41.667 40.967 SLICE_X48Y135 clocks393_i/test_clk_reg[1]/C
Low Pulse Width Slow FDCE/C n/a 0.350 20.833 20.484 SLICE_X48Y135 clocks393_i/test_clk_reg[1]/C
High Pulse Width Slow FDCE/C n/a 0.350 20.833 20.483 SLICE_X48Y135 clocks393_i/test_clk_reg[1]/C
---------------------------------------------------------------------------------------------------
From Clock: gtrefclk
To Clock: gtrefclk
Setup : 0 Failing Endpoints, Worst Slack 4.424ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.233ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 2.553ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 4.424ns (required time - arrival time)
Source: sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/C
(rising edge-triggered cell FDRE clocked by gtrefclk {rise@0.000ns fall@3.333ns period=6.666ns})
Destination: sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/CE
(rising edge-triggered cell FDRE clocked by gtrefclk {rise@0.000ns fall@3.333ns period=6.666ns})
Path Group: gtrefclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 6.666ns (gtrefclk rise@6.666ns - gtrefclk rise@0.000ns)
Data Path Delay: 1.963ns (logic 0.375ns (19.108%) route 1.588ns (80.892%))
Logic Levels: 2 (LUT3=1 LUT6=1)
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.445ns = ( 8.111 - 6.666 )
Source Clock Delay (SCD): 1.569ns
Clock Pessimism Removal (CPR): 0.124ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock gtrefclk rise edge)
0.000 0.000 r
IBUFDS_GTE2_X0Y0 IBUFDS_GTE2 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
net (fo=25, routed) 1.569 1.569 sata_top/ahci_sata_layers_i/phy/gtrefclk
SLICE_X67Y49 FDRE r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/C
------------------------------------------------------------------- -------------------
SLICE_X67Y49 FDRE (Prop_fdre_C_Q) 0.269 1.838 r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/Q
net (fo=5, routed) 0.942 2.781 sata_top/ahci_sata_layers_i/phy/rst_timer_reg__0[2]
SLICE_X67Y49 LUT6 (Prop_lut6_I1_O) 0.053 2.834 f sata_top/ahci_sata_layers_i/phy/sata_areset_i_2/O
net (fo=4, routed) 0.359 3.192 sata_top/ahci_sata_layers_i/phy/sata_areset_i_2_n_0
SLICE_X66Y49 LUT3 (Prop_lut3_I2_O) 0.053 3.245 r sata_top/ahci_sata_layers_i/phy/rst_timer[7]_i_2/O
net (fo=8, routed) 0.287 3.532 sata_top/ahci_sata_layers_i/phy/rst_timer[7]_i_2_n_0
SLICE_X67Y49 FDRE r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/CE
------------------------------------------------------------------- -------------------
(clock gtrefclk rise edge)
6.666 6.666 r
IBUFDS_GTE2_X0Y0 IBUFDS_GTE2 0.000 6.666 r sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
net (fo=25, routed) 1.445 8.111 sata_top/ahci_sata_layers_i/phy/gtrefclk
SLICE_X67Y49 FDRE r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/C
clock pessimism 0.124 8.235
clock uncertainty -0.035 8.200
SLICE_X67Y49 FDRE (Setup_fdre_C_CE) -0.244 7.956 sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]
-------------------------------------------------------------------
required time 7.956
arrival time -3.532
-------------------------------------------------------------------
slack 4.424
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.233ns (arrival time - required time)
Source: sata_top/ahci_sata_layers_i/phy/rst_timer_reg[4]/C
(rising edge-triggered cell FDRE clocked by gtrefclk {rise@0.000ns fall@3.333ns period=6.666ns})
Destination: sata_top/ahci_sata_layers_i/phy/rst_timer_reg[5]/D
(rising edge-triggered cell FDRE clocked by gtrefclk {rise@0.000ns fall@3.333ns period=6.666ns})
Path Group: gtrefclk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (gtrefclk rise@0.000ns - gtrefclk rise@0.000ns)
Data Path Delay: 0.294ns (logic 0.157ns (53.385%) route 0.137ns (46.615%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 0.659ns
Source Clock Delay (SCD): 0.456ns
Clock Pessimism Removal (CPR): 0.203ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock gtrefclk rise edge)
0.000 0.000 r
IBUFDS_GTE2_X0Y0 IBUFDS_GTE2 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
net (fo=25, routed) 0.456 0.456 sata_top/ahci_sata_layers_i/phy/gtrefclk
SLICE_X67Y49 FDRE r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[4]/C
------------------------------------------------------------------- -------------------
SLICE_X67Y49 FDRE (Prop_fdre_C_Q) 0.091 0.547 r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[4]/Q
net (fo=3, routed) 0.137 0.685 sata_top/ahci_sata_layers_i/phy/rst_timer_reg__0[4]
SLICE_X67Y49 LUT6 (Prop_lut6_I5_O) 0.066 0.751 r sata_top/ahci_sata_layers_i/phy/rst_timer[5]_i_1/O
net (fo=1, routed) 0.000 0.751 sata_top/ahci_sata_layers_i/phy/rst_timer0[5]
SLICE_X67Y49 FDRE r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[5]/D
------------------------------------------------------------------- -------------------
(clock gtrefclk rise edge)
0.000 0.000 r
IBUFDS_GTE2_X0Y0 IBUFDS_GTE2 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
net (fo=25, routed) 0.659 0.659 sata_top/ahci_sata_layers_i/phy/gtrefclk
SLICE_X67Y49 FDRE r sata_top/ahci_sata_layers_i/phy/rst_timer_reg[5]/C
clock pessimism -0.203 0.456
SLICE_X67Y49 FDRE (Hold_fdre_C_D) 0.061 0.517 sata_top/ahci_sata_layers_i/phy/rst_timer_reg[5]
-------------------------------------------------------------------
required time -0.517
arrival time 0.751
-------------------------------------------------------------------
slack 0.233
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: gtrefclk
Waveform(ns): { 0.000 3.333 }
Period(ns): 6.666
Sources: { sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a GTXE2_CHANNEL/GTREFCLK0 n/a 1.538 6.666 5.128 GTXE2_CHANNEL_X0Y0 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/GTREFCLK0
Low Pulse Width Slow SRL16E/CLK n/a 0.780 3.333 2.553 SLICE_X84Y48 sata_top/ahci_sata_layers_i/phy/rxreset_f_r_reg_srl2/CLK
High Pulse Width Slow SRL16E/CLK n/a 0.780 3.333 2.553 SLICE_X84Y48 sata_top/ahci_sata_layers_i/phy/rxreset_f_r_reg_srl2/CLK
---------------------------------------------------------------------------------------------------
From Clock: rx_clk
To Clock: rx_clk
Setup : 0 Failing Endpoints, Worst Slack 0.839ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.058ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 2.423ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.839ns (required time - arrival time)
Source: sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/indata_r_reg[19]/C
(rising edge-triggered cell FDRE clocked by rx_clk {rise@0.000ns fall@3.333ns period=6.666ns})
Destination: sata_top/ahci_sata_layers_i/phy/gtx_wrap/state_aligned_reg/D
(rising edge-triggered cell FDRE clocked by rx_clk {rise@0.000ns fall@3.333ns period=6.666ns})
Path Group: rx_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 6.666ns (rx_clk rise@6.666ns - rx_clk rise@0.000ns)
Data Path Delay: 5.793ns (logic 0.820ns (14.154%) route 4.973ns (85.846%))
Logic Levels: 8 (LUT4=1 LUT5=4 LUT6=3)
Clock Path Skew: -0.033ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.890ns = ( 9.556 - 6.666 )
Source Clock Delay (SCD): 3.063ns
Clock Pessimism Removal (CPR): 0.140ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock rx_clk rise edge) 0.000 0.000 r
GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
net (fo=1, routed) 1.349 1.349 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.120 1.469 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
net (fo=327, routed) 1.594 3.063 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/CLK
SLICE_X71Y8 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/indata_r_reg[19]/C
------------------------------------------------------------------- -------------------
SLICE_X71Y8 FDRE (Prop_fdre_C_Q) 0.269 3.332 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/indata_r_reg[19]/Q
net (fo=55, routed) 1.296 4.628 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/subwindow[1]_0[18]
SLICE_X49Y4 LUT5 (Prop_lut5_I3_O) 0.063 4.691 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/comma_match_prev[2]_i_8/O
net (fo=1, routed) 0.307 4.998 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/comma_match_prev[2]_i_8_n_0
SLICE_X49Y4 LUT6 (Prop_lut6_I5_O) 0.170 5.168 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/xlnx_opt_LUT_comma_match_prev[2]_i_2_1/O
net (fo=1, routed) 0.341 5.509 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/xlnx_opt_comma_match_p_2__15
SLICE_X47Y3 LUT6 (Prop_lut6_I5_O) 0.053 5.562 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/xlnx_opt_LUT_comma_match_prev[2]_i_2_2/O
net (fo=4, routed) 0.340 5.901 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/comma_match_p_2__15
SLICE_X50Y3 LUT6 (Prop_lut6_I0_O) 0.053 5.954 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/comma_match_prev[2]_i_1/O
net (fo=5, routed) 0.809 6.763 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/comma_match[2]
SLICE_X55Y2 LUT5 (Prop_lut5_I0_O) 0.053 6.816 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/xlnx_opt_LUT_comma_match_prev[19]_i_2/O
net (fo=1, routed) 0.546 7.362 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/xlnx_opt_comma_3
SLICE_X57Y2 LUT4 (Prop_lut4_I0_O) 0.053 7.415 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/xlnx_opt_LUT_comma_match_prev[19]_i_2_4/O
net (fo=43, routed) 0.881 8.296 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/comma
SLICE_X60Y2 LUT5 (Prop_lut5_I0_O) 0.053 8.349 f sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/state_aligned_i_2/O
net (fo=2, routed) 0.455 8.803 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/realign
SLICE_X63Y8 LUT5 (Prop_lut5_I1_O) 0.053 8.856 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_comma_align/state_aligned_i_1/O
net (fo=1, routed) 0.000 8.856 sata_top/ahci_sata_layers_i/phy/gtx_wrap/state_aligned0
SLICE_X63Y8 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/state_aligned_reg/D
------------------------------------------------------------------- -------------------
(clock rx_clk rise edge) 6.666 6.666 r
GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 6.666 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
net (fo=1, routed) 1.300 7.966 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.113 8.079 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
net (fo=327, routed) 1.477 9.556 sata_top/ahci_sata_layers_i/phy/gtx_wrap/busy_r_reg
SLICE_X63Y8 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/state_aligned_reg/C
clock pessimism 0.140 9.696
clock uncertainty -0.035 9.661
SLICE_X63Y8 FDRE (Setup_fdre_C_D) 0.035 9.696 sata_top/ahci_sata_layers_i/phy/gtx_wrap/state_aligned_reg
-------------------------------------------------------------------
required time 9.696
arrival time -8.856
-------------------------------------------------------------------
slack 0.839
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.058ns (arrival time - required time)
Source: sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/disperror_in_r_reg[0]/C
(rising edge-triggered cell FDRE clocked by rx_clk {rise@0.000ns fall@3.333ns period=6.666ns})
Destination: sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_36_41/RAMC/I
(rising edge-triggered cell RAMD32 clocked by rx_clk {rise@0.000ns fall@3.333ns period=6.666ns})
Path Group: rx_clk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (rx_clk rise@0.000ns - rx_clk rise@0.000ns)
Data Path Delay: 0.201ns (logic 0.100ns (49.804%) route 0.101ns (50.196%))
Logic Levels: 0
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.340ns
Source Clock Delay (SCD): 1.093ns
Clock Pessimism Removal (CPR): 0.233ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock rx_clk rise edge) 0.000 0.000 r
GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
net (fo=1, routed) 0.526 0.526 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.552 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
net (fo=327, routed) 0.541 1.093 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/CLK
SLICE_X89Y148 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/disperror_in_r_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X89Y148 FDRE (Prop_fdre_C_Q) 0.100 1.193 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/disperror_in_r_reg[0]/Q
net (fo=4, routed) 0.101 1.294 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_36_41/DIC0
SLICE_X88Y147 RAMD32 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_36_41/RAMC/I
------------------------------------------------------------------- -------------------
(clock rx_clk rise edge) 0.000 0.000 r
GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
net (fo=1, routed) 0.563 0.563 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.030 0.593 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
net (fo=327, routed) 0.747 1.340 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_36_41/WCLK
SLICE_X88Y147 RAMD32 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_36_41/RAMC/CLK
clock pessimism -0.233 1.107
SLICE_X88Y147 RAMD32 (Hold_ramd32_CLK_I)
0.129 1.236 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_36_41/RAMC
-------------------------------------------------------------------
required time -1.236
arrival time 1.294
-------------------------------------------------------------------
slack 0.058
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: rx_clk
Waveform(ns): { 0.000 3.333 }
Period(ns): 6.666
Sources: { sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 4.000 6.666 2.666 GTXE2_CHANNEL_X0Y0 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXUSRCLK
Low Pulse Width Fast RAMD32/CLK n/a 0.910 3.333 2.423 SLICE_X88Y145 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA/CLK
High Pulse Width Slow RAMD32/CLK n/a 0.910 3.333 2.423 SLICE_X88Y145 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: txoutclk
To Clock: txoutclk
Setup : 0 Failing Endpoints, Worst Slack 0.968ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.100ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 2.666ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.968ns (required time - arrival time)
Source: sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[14]/C
(rising edge-triggered cell FDRE clocked by txoutclk {rise@0.000ns fall@3.333ns period=6.666ns})
Destination: sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/ADDRBWRADDR[11]
(rising edge-triggered cell RAMB36E1 clocked by txoutclk {rise@0.000ns fall@3.333ns period=6.666ns})
Path Group: txoutclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 6.666ns (txoutclk rise@6.666ns - txoutclk rise@0.000ns)
Data Path Delay: 5.349ns (logic 0.269ns (5.029%) route 5.080ns (94.971%))
Logic Levels: 0
Clock Path Skew: 0.166ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.974ns = ( 9.640 - 6.666 )
Source Clock Delay (SCD): 2.864ns
Clock Pessimism Removal (CPR): 0.056ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock txoutclk rise edge)
0.000 0.000 r
GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
net (fo=1, routed) 1.349 1.349 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.120 1.469 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
net (fo=136, routed) 1.395 2.864 sata_top/ahci_sata_layers_i/phy/gtx_wrap/CLK
SLICE_X71Y144 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[14]/C
------------------------------------------------------------------- -------------------
SLICE_X71Y144 FDRE (Prop_fdre_C_Q) 0.269 3.133 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[14]/Q
net (fo=1, routed) 5.080 8.213 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/ADDRBWRADDR[6]
RAMB36_X5Y3 RAMB36E1 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/ADDRBWRADDR[11]
------------------------------------------------------------------- -------------------
(clock txoutclk rise edge)
6.666 6.666 r
GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 6.666 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
net (fo=1, routed) 1.300 7.966 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.113 8.079 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
net (fo=136, routed) 1.561 9.640 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/CLK
RAMB36_X5Y3 RAMB36E1 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/CLKBWRCLK
clock pessimism 0.056 9.696
clock uncertainty -0.035 9.660
RAMB36_X5Y3 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[11])
-0.479 9.181 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i
-------------------------------------------------------------------
required time 9.181
arrival time -8.213
-------------------------------------------------------------------
slack 0.968
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.100ns (arrival time - required time)
Source: sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[7]/C
(rising edge-triggered cell FDRE clocked by txoutclk {rise@0.000ns fall@3.333ns period=6.666ns})
Destination: sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXDATA[7]
(rising edge-triggered cell GTXE2_CHANNEL clocked by txoutclk {rise@0.000ns fall@3.333ns period=6.666ns})
Path Group: txoutclk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (txoutclk rise@0.000ns - txoutclk rise@0.000ns)
Data Path Delay: 0.407ns (logic 0.100ns (24.591%) route 0.307ns (75.409%))
Logic Levels: 0
Clock Path Skew: 0.229ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.645ns
Source Clock Delay (SCD): 1.187ns
Clock Pessimism Removal (CPR): 0.229ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock txoutclk rise edge)
0.000 0.000 r
GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
net (fo=1, routed) 0.526 0.526 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 0.552 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
net (fo=136, routed) 0.635 1.187 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/CLK
SLICE_X107Y6 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[7]/C
------------------------------------------------------------------- -------------------
SLICE_X107Y6 FDRE (Prop_fdre_C_Q) 0.100 1.287 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[7]/Q
net (fo=1, routed) 0.307 1.594 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/outdata_l_reg[19][7]
GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXDATA[7]
------------------------------------------------------------------- -------------------
(clock txoutclk rise edge)
0.000 0.000 r
GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
net (fo=1, routed) 0.563 0.563 sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 0.593 r sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
net (fo=136, routed) 1.052 1.645 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/rxreset_f_rr_reg__0
GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL r sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXUSRCLK2
clock pessimism -0.229 1.416
GTXE2_CHANNEL_X0Y0 GTXE2_CHANNEL (Hold_gtxe2_channel_TXUSRCLK2_TXDATA[7])
0.078 1.494 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims
-------------------------------------------------------------------
required time -1.494
arrival time 1.594
-------------------------------------------------------------------
slack 0.100
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: txoutclk
Waveform(ns): { 0.000 3.333 }
Period(ns): 6.666
Sources: { sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 4.000 6.666 2.666 GTXE2_CHANNEL_X0Y0 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXUSRCLK
Low Pulse Width Fast FDRE/C n/a 0.400 3.333 2.933 SLICE_X69Y141 sata_top/ahci_sata_layers_i/phy/gtx_wrap/txcharisk_enc_in_r_reg[1]/C
High Pulse Width Slow FDRE/C n/a 0.350 3.333 2.983 SLICE_X65Y49 sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/C
---------------------------------------------------------------------------------------------------
From Clock: usrclk2
To Clock: usrclk2
Setup : 0 Failing Endpoints, Worst Slack 3.391ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.029ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 5.756ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 3.391ns (required time - arrival time)
Source: sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/C
(rising edge-triggered cell FDCE clocked by usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns})
Destination: sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_dav2_reg/D
(rising edge-triggered cell FDRE clocked by usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns})
Path Group: usrclk2
Path Type: Setup (Max at Slow Process Corner)
Requirement: 13.333ns (usrclk2 rise@13.333ns - usrclk2 rise@0.000ns)
Data Path Delay: 9.805ns (logic 0.609ns (6.211%) route 9.196ns (93.789%))
Logic Levels: 4 (LUT2=1 LUT3=1 LUT5=1 LUT6=1)
Clock Path Skew: -0.137ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.034ns = ( 16.367 - 13.333 )
Source Clock Delay (SCD): 3.465ns
Clock Pessimism Removal (CPR): 0.294ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock usrclk2 rise edge) 0.000 0.000 r
SLICE_X65Y49 FDRE 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
net (fo=2, routed) 1.941 1.941 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.120 2.061 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
net (fo=2023, routed) 1.404 3.465 sata_top/ahci_sata_layers_i/phy/rxdata_reg[0]__0
SLICE_X77Y50 FDCE r sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/C
------------------------------------------------------------------- -------------------
SLICE_X77Y50 FDCE (Prop_fdce_C_Q) 0.269 3.734 f sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/Q
net (fo=8, routed) 0.467 4.201 sata_top/ahci_sata_layers_i/phy/sata_reset_done
SLICE_X77Y50 LUT3 (Prop_lut3_I2_O) 0.053 4.254 r sata_top/ahci_sata_layers_i/phy/was_rst_i_1/O
net (fo=278, routed) 7.131 11.385 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/sata_reset_done_r_reg[0]
SLICE_X45Y133 LUT5 (Prop_lut5_I4_O) 0.064 11.449 r sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/slow_down_i_6/O
net (fo=3, routed) 0.777 12.226 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/slow_down_i_6_n_0
SLICE_X47Y132 LUT6 (Prop_lut6_I4_O) 0.170 12.396 r sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/slow_down_i_2/O
net (fo=2, routed) 0.821 13.217 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/slow_down_i_2_n_0
SLICE_X45Y136 LUT2 (Prop_lut2_I1_O) 0.053 13.270 r sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/fifo_dav2_i_1__0/O
net (fo=1, routed) 0.000 13.270 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i_n_2
SLICE_X45Y136 FDRE r sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_dav2_reg/D
------------------------------------------------------------------- -------------------
(clock usrclk2 rise edge) 13.333 13.333 r
SLICE_X65Y49 FDRE 0.000 13.333 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
net (fo=2, routed) 1.654 14.987 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.113 15.100 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
net (fo=2023, routed) 1.267 16.367 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/usrclk2_r_reg
SLICE_X45Y136 FDRE r sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_dav2_reg/C
clock pessimism 0.294 16.661
clock uncertainty -0.035 16.626
SLICE_X45Y136 FDRE (Setup_fdre_C_D) 0.035 16.661 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_dav2_reg
-------------------------------------------------------------------
required time 16.661
arrival time -13.270
-------------------------------------------------------------------
slack 3.391
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.029ns (arrival time - required time)
Source: sata_top/ahci_sata_layers_i/link/phy_data_in_r0_reg[6]/C
(rising edge-triggered cell FDRE clocked by usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns})
Destination: sata_top/ahci_sata_layers_i/link/last_not_cont_di_reg[6]/D
(rising edge-triggered cell FDRE clocked by usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns})
Path Group: usrclk2
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (usrclk2 rise@0.000ns - usrclk2 rise@0.000ns)
Data Path Delay: 0.365ns (logic 0.100ns (27.363%) route 0.265ns (72.637%))
Logic Levels: 0
Clock Path Skew: 0.291ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.919ns
Source Clock Delay (SCD): 1.463ns
Clock Pessimism Removal (CPR): 0.165ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock usrclk2 rise edge) 0.000 0.000 r
SLICE_X65Y49 FDRE 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
net (fo=2, routed) 0.897 0.897 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 0.923 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
net (fo=2023, routed) 0.540 1.463 sata_top/ahci_sata_layers_i/link/usrclk2_r_reg
SLICE_X87Y148 FDRE r sata_top/ahci_sata_layers_i/link/phy_data_in_r0_reg[6]/C
------------------------------------------------------------------- -------------------
SLICE_X87Y148 FDRE (Prop_fdre_C_Q) 0.100 1.563 r sata_top/ahci_sata_layers_i/link/phy_data_in_r0_reg[6]/Q
net (fo=5, routed) 0.265 1.828 sata_top/ahci_sata_layers_i/link/phy_data_in_r0[6]
SLICE_X70Y150 FDRE r sata_top/ahci_sata_layers_i/link/last_not_cont_di_reg[6]/D
------------------------------------------------------------------- -------------------
(clock usrclk2 rise edge) 0.000 0.000 r
SLICE_X65Y49 FDRE 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
net (fo=2, routed) 1.050 1.050 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.080 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
net (fo=2023, routed) 0.839 1.919 sata_top/ahci_sata_layers_i/link/usrclk2_r_reg
SLICE_X70Y150 FDRE r sata_top/ahci_sata_layers_i/link/last_not_cont_di_reg[6]/C
clock pessimism -0.165 1.754
SLICE_X70Y150 FDRE (Hold_fdre_C_D) 0.045 1.799 sata_top/ahci_sata_layers_i/link/last_not_cont_di_reg[6]
-------------------------------------------------------------------
required time -1.799
arrival time 1.828
-------------------------------------------------------------------
slack 0.029
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: usrclk2
Waveform(ns): { 0.000 6.666 }
Period(ns): 13.333
Sources: { sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.183 13.333 11.150 RAMB36_X2Y26 sata_top/ahci_top_i/ahci_dma_i/ct_data_ram_reg_bram_0/CLKARDCLK
Low Pulse Width Slow RAMD32/CLK n/a 0.910 6.667 5.757 SLICE_X32Y134 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/fifo0_ram_reg_0_7_30_31/RAMA/CLK
High Pulse Width Fast RAMD32/CLK n/a 0.910 6.666 5.756 SLICE_X30Y136 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/fifo0_ram_reg_0_7_24_29/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: ddr3_clk_div
To Clock: ddr3_clk
Setup : 0 Failing Endpoints, Worst Slack 0.100ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.172ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.100ns (required time - arrival time)
Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
(rising edge-triggered cell FDSE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/oserdes_i/T1
(rising edge-triggered cell OSERDESE2 clocked by ddr3_clk {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: ddr3_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.500ns (ddr3_clk rise@2.500ns - ddr3_clk_div rise@0.000ns)
Data Path Delay: 1.502ns (logic 0.269ns (17.905%) route 1.233ns (82.095%))
Logic Levels: 0
Clock Path Skew: -0.013ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.645ns = ( 6.145 - 2.500 )
Source Clock Delay (SCD): 3.801ns
Clock Pessimism Removal (CPR): 0.143ns
Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.156ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.575 1.575 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.088 1.663 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.106 2.769 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.377 3.146 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.655 3.801 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
SLICE_X115Y132 FDSE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
------------------------------------------------------------------- -------------------
SLICE_X115Y132 FDSE (Prop_fdse_C_Q) 0.269 4.070 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/Q
net (fo=23, routed) 1.233 5.303 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/in_tri_r_reg
OLOGIC_X1Y101 OSERDESE2 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/oserdes_i/T1
------------------------------------------------------------------- -------------------
(clock ddr3_clk rise edge)
2.500 2.500 r
BUFGCTRL_X0Y17 BUFG 0.000 2.500 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.437 3.937 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
0.083 4.020 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1
net (fo=1, routed) 1.016 5.036 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_pre
BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.370 5.406 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/O
net (fo=75, routed) 0.739 6.145 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/clk
OLOGIC_X1Y101 OSERDESE2 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/oserdes_i/CLK
clock pessimism 0.143 6.288
clock uncertainty -0.205 6.083
OLOGIC_X1Y101 OSERDESE2 (Setup_oserdese2_CLK_T1)
-0.679 5.404 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/oserdes_i
-------------------------------------------------------------------
required time 5.404
arrival time -5.303
-------------------------------------------------------------------
slack 0.100
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.172ns (arrival time - required time)
Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
(rising edge-triggered cell FDSE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/oserdes_i/T1
(rising edge-triggered cell OSERDESE2 clocked by ddr3_clk {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: ddr3_clk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (ddr3_clk rise@0.000ns - ddr3_clk_div rise@0.000ns)
Data Path Delay: 0.427ns (logic 0.100ns (23.409%) route 0.327ns (76.591%))
Logic Levels: 0
Clock Path Skew: 0.154ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.796ns
Source Clock Delay (SCD): 1.423ns
Clock Pessimism Removal (CPR): 0.219ns
Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.156ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.580 0.580 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.050 0.630 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.433 1.063 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.090 1.153 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.270 1.423 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
SLICE_X115Y132 FDSE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
------------------------------------------------------------------- -------------------
SLICE_X115Y132 FDSE (Prop_fdse_C_Q) 0.100 1.523 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/Q
net (fo=23, routed) 0.327 1.850 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/in_tri_r_reg
OLOGIC_X1Y138 OSERDESE2 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/oserdes_i/T1
------------------------------------------------------------------- -------------------
(clock ddr3_clk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.796 0.796 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
0.053 0.849 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1
net (fo=1, routed) 0.490 1.339 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_pre
BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.093 1.432 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/O
net (fo=75, routed) 0.364 1.796 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/clk
OLOGIC_X1Y138 OSERDESE2 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/oserdes_i/CLK
clock pessimism -0.219 1.577
clock uncertainty 0.205 1.782
OLOGIC_X1Y138 OSERDESE2 (Hold_oserdese2_CLK_T1)
-0.104 1.678 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/oserdes_i
-------------------------------------------------------------------
required time -1.678
arrival time 1.850
-------------------------------------------------------------------
slack 0.172
---------------------------------------------------------------------------------------------------
From Clock: ddr3_mclk
To Clock: ddr3_clk_div
Setup : 0 Failing Endpoints, Worst Slack 0.188ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 1.426ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.188ns (required time - arrival time)
Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK
(rising edge-triggered cell RAMB36E1 clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/tin_dqs_r_reg[2]/D
(rising edge-triggered cell FDSE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: ddr3_clk_div
Path Type: Setup (Max at Slow Process Corner)
Requirement: 3.750ns (ddr3_clk_div rise@5.000ns - ddr3_mclk rise@1.250ns)
Data Path Delay: 2.156ns (logic 0.854ns (39.611%) route 1.302ns (60.389%))
Logic Levels: 2 (LUT4=1 LUT6=1)
Clock Path Skew: -1.184ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.565ns = ( 8.565 - 5.000 )
Source Clock Delay (SCD): 4.892ns = ( 6.142 - 1.250 )
Clock Pessimism Removal (CPR): 0.143ns
Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.156ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y17 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.575 2.825 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.088 2.913 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 1.628 4.541 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.120 4.661 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=34863, routed) 1.481 6.142 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/CLK
RAMB36_X7Y26 RAMB36E1 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK
------------------------------------------------------------------- -------------------
RAMB36_X7Y26 RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[6])
0.748 6.890 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/DOADO[6]
net (fo=1, routed) 0.698 7.588 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_0[5]
SLICE_X110Y126 LUT4 (Prop_lut4_I3_O) 0.053 7.641 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/extra_prev[5]_i_1/O
net (fo=6, routed) 0.164 7.804 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/RAMB36E1_i[0]
SLICE_X110Y126 LUT6 (Prop_lut6_I1_O) 0.053 7.857 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/tin_dqs_r[2]_i_1/O
net (fo=2, routed) 0.440 8.298 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/tin_dqs_r_reg[3]_0[2]
SLICE_X110Y126 FDSE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/tin_dqs_r_reg[2]/D
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
5.000 5.000 r
BUFGCTRL_X0Y17 BUFG 0.000 5.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.437 6.437 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.083 6.520 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.016 7.536 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.370 7.906 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.659 8.565 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/psincdec_reg_0
SLICE_X110Y126 FDSE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/tin_dqs_r_reg[2]/C
clock pessimism 0.143 8.708
clock uncertainty -0.205 8.503
SLICE_X110Y126 FDSE (Setup_fdse_C_D) -0.017 8.486 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/tin_dqs_r_reg[2]
-------------------------------------------------------------------
required time 8.486
arrival time -8.298
-------------------------------------------------------------------
slack 0.188
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 1.426ns (arrival time - required time)
Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/deser_r_reg[4]/C
(rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[4]/D
(rising edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: ddr3_clk_div
Path Type: Hold (Min at Fast Process Corner)
Requirement: -1.250ns (ddr3_clk_div rise@0.000ns - ddr3_mclk rise@1.250ns)
Data Path Delay: 0.201ns (logic 0.100ns (49.804%) route 0.101ns (50.196%))
Logic Levels: 0
Clock Path Skew: -0.222ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.772ns
Source Clock Delay (SCD): 1.775ns = ( 3.025 - 1.250 )
Clock Pessimism Removal (CPR): 0.219ns
Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.156ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y17 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.580 1.830 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.050 1.880 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 0.559 2.439 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 2.465 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=34863, routed) 0.560 3.025 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/CLK
SLICE_X95Y115 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/deser_r_reg[4]/C
------------------------------------------------------------------- -------------------
SLICE_X95Y115 FDRE (Prop_fdre_C_Q) 0.100 3.125 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/deser_r_reg[4]/Q
net (fo=1, routed) 0.101 3.226 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/deser_r_reg[6][4]
SLICE_X95Y116 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[4]/D
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.796 0.796 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.053 0.849 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.490 1.339 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.093 1.432 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.340 1.772 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div
SLICE_X95Y116 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[4]/C
clock pessimism -0.219 1.553
clock uncertainty 0.205 1.758
SLICE_X95Y116 FDRE (Hold_fdre_C_D) 0.041 1.799 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[4]
-------------------------------------------------------------------
required time -1.799
arrival time 3.226
-------------------------------------------------------------------
slack 1.426
---------------------------------------------------------------------------------------------------
From Clock: ddr3_clk_div
To Clock: ddr3_mclk
Setup : 0 Failing Endpoints, Worst Slack 2.610ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.544ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.610ns (required time - arrival time)
Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[1]/C
(falling edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]/D
(rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Path Group: ddr3_mclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 3.750ns (ddr3_mclk rise@6.250ns - ddr3_clk_div fall@2.500ns)
Data Path Delay: 1.571ns (logic 0.272ns (17.318%) route 1.299ns (82.682%))
Logic Levels: 0
Clock Path Skew: 0.657ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.445ns = ( 10.695 - 6.250 )
Source Clock Delay (SCD): 3.931ns = ( 6.431 - 2.500 )
Clock Pessimism Removal (CPR): 0.143ns
Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.156ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div fall edge)
2.500 2.500 f
BUFGCTRL_X0Y17 BUFG 0.000 2.500 f clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.575 4.075 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.088 4.163 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.106 5.269 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.377 5.646 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.785 6.431 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div
SLICE_X85Y102 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[1]/C (IS_INVERTED)
------------------------------------------------------------------- -------------------
SLICE_X85Y102 FDRE (Prop_fdre_C_Q) 0.272 6.703 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[1]/Q
net (fo=1, routed) 1.299 8.002 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1[1]
SLICE_X53Y100 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]/D
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
6.250 6.250 r
BUFGCTRL_X0Y17 BUFG 0.000 6.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.437 7.687 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.083 7.770 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 1.544 9.314 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.113 9.427 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=34863, routed) 1.268 10.695 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/CLK
SLICE_X53Y100 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]/C
clock pessimism 0.143 10.838
clock uncertainty -0.205 10.633
SLICE_X53Y100 FDRE (Setup_fdre_C_D) -0.021 10.612 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]
-------------------------------------------------------------------
required time 10.612
arrival time -8.002
-------------------------------------------------------------------
slack 2.610
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.544ns (arrival time - required time)
Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r1_reg/C
(falling edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r2_reg/D
(rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Path Group: ddr3_mclk
Path Type: Hold (Min at Slow Process Corner)
Requirement: -1.250ns (ddr3_mclk rise@1.250ns - ddr3_clk_div fall@2.500ns)
Data Path Delay: 0.662ns (logic 0.218ns (32.948%) route 0.444ns (67.052%))
Logic Levels: 0
Clock Path Skew: 1.004ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 4.798ns = ( 6.048 - 1.250 )
Source Clock Delay (SCD): 3.651ns = ( 6.151 - 2.500 )
Clock Pessimism Removal (CPR): 0.143ns
Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.156ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div fall edge)
2.500 2.500 f
BUFGCTRL_X0Y17 BUFG 0.000 2.500 f clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.437 3.937 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.083 4.020 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.016 5.036 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.370 5.406 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.745 6.151 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div
SLICE_X61Y104 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r1_reg/C (IS_INVERTED)
------------------------------------------------------------------- -------------------
SLICE_X61Y104 FDRE (Prop_fdre_C_Q) 0.218 6.369 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r1_reg/Q
net (fo=1, routed) 0.444 6.813 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r1
SLICE_X53Y104 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r2_reg/D
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y17 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.575 2.825 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.088 2.913 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 1.628 4.541 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.120 4.661 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=34863, routed) 1.387 6.048 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/CLK
SLICE_X53Y104 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r2_reg/C
clock pessimism -0.143 5.905
clock uncertainty 0.205 6.110
SLICE_X53Y104 FDRE (Hold_fdre_C_D) 0.158 6.268 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r2_reg
-------------------------------------------------------------------
required time -6.268
arrival time 6.813
-------------------------------------------------------------------
slack 0.544
---------------------------------------------------------------------------------------------------
From Clock: iclk1x0
To Clock: iclk0
Setup : 0 Failing Endpoints, Worst Slack 5.510ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.147ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 5.510ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[4]/C
(rising edge-triggered cell FDRE clocked by iclk1x0 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[4]/D
(rising edge-triggered cell FDRE clocked by iclk0 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 7.407ns (iclk0 rise@29.784ns - iclk1x0 rise@22.377ns)
Data Path Delay: 1.456ns (logic 0.308ns (21.151%) route 1.148ns (78.849%))
Logic Levels: 0
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.806ns = ( 33.590 - 29.784 )
Source Clock Delay (SCD): 4.228ns = ( 26.605 - 22.377 )
Clock Pessimism Removal (CPR): 0.277ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x0 rise edge) 22.377 22.377 r
AA10 0.000 22.377 r sns1_clkp (IN)
net (fo=0) 0.000 22.377 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.910 23.287 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.085 24.372 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.088 24.460 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.106 25.566 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y0 BUFR (Prop_bufr_I_O) 0.377 25.943 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.662 26.605 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/CLK
SLICE_X6Y39 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[4]/C
------------------------------------------------------------------- -------------------
SLICE_X6Y39 FDRE (Prop_fdre_C_Q) 0.308 26.913 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[4]/Q
net (fo=1, routed) 1.148 28.061 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r[4]
SLICE_X5Y39 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[4]/D
------------------------------------------------------------------- -------------------
(clock iclk0 rise edge) 29.784 29.784 r
AA10 0.000 29.784 r sns1_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.831 30.615 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.887 31.502 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.083 31.585 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 1.016 32.601 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y1 BUFR (Prop_bufr_I_O) 0.370 32.971 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.619 33.590 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/rst_early_master_reg
SLICE_X5Y39 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[4]/C
clock pessimism 0.277 33.867
clock uncertainty -0.276 33.591
SLICE_X5Y39 FDRE (Setup_fdre_C_D) -0.020 33.571 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[4]
-------------------------------------------------------------------
required time 33.571
arrival time -28.061
-------------------------------------------------------------------
slack 5.510
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.147ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r_reg[6]/C
(rising edge-triggered cell FDRE clocked by iclk1x0 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/dout_r_reg[6]/D
(rising edge-triggered cell FDRE clocked by iclk0 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (iclk0 rise@66.821ns - iclk1x0 rise@66.821ns)
Data Path Delay: 0.562ns (logic 0.100ns (17.793%) route 0.462ns (82.207%))
Logic Levels: 0
Clock Path Skew: 0.099ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.018ns = ( 68.839 - 66.821 )
Source Clock Delay (SCD): 1.744ns = ( 68.565 - 66.821 )
Clock Pessimism Removal (CPR): 0.175ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x0 rise edge) 66.821 66.821 r
AA10 0.000 66.821 r sns1_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.412 67.233 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.487 67.720 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.050 67.770 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.433 68.203 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y0 BUFR (Prop_bufr_I_O) 0.090 68.293 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.272 68.565 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/CLK
SLICE_X3Y37 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r_reg[6]/C
------------------------------------------------------------------- -------------------
SLICE_X3Y37 FDRE (Prop_fdre_C_Q) 0.100 68.665 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r_reg[6]/Q
net (fo=1, routed) 0.462 69.127 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r[6]
SLICE_X2Y36 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/dout_r_reg[6]/D
------------------------------------------------------------------- -------------------
(clock iclk0 rise edge) 66.821 66.821 r
AA10 0.000 66.821 r sns1_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.481 67.302 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.593 67.895 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.053 67.948 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 0.490 68.438 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y1 BUFR (Prop_bufr_I_O) 0.093 68.531 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.308 68.839 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/rst_early_master_reg
SLICE_X2Y36 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/dout_r_reg[6]/C
clock pessimism -0.175 68.664
clock uncertainty 0.276 68.940
SLICE_X2Y36 FDRE (Hold_fdre_C_D) 0.040 68.980 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/dout_r_reg[6]
-------------------------------------------------------------------
required time -68.980
arrival time 69.127
-------------------------------------------------------------------
slack 0.147
---------------------------------------------------------------------------------------------------
From Clock: iclk0
To Clock: iclk1x0
Setup : 0 Failing Endpoints, Worst Slack 2.547ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 3.577ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.547ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C
(falling edge-triggered cell FDCE clocked by iclk0 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
(rising edge-triggered cell FDRE clocked by iclk1x0 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 3.704ns (iclk1x0 rise@52.006ns - iclk0 fall@48.302ns)
Data Path Delay: 0.775ns (logic 0.368ns (47.494%) route 0.407ns (52.506%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.865ns = ( 55.871 - 52.006 )
Source Clock Delay (SCD): 4.288ns = ( 52.591 - 48.302 )
Clock Pessimism Removal (CPR): 0.282ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk0 fall edge) 48.302 48.302 f
AA10 0.000 48.302 f sns1_clkp (IN)
net (fo=0) 0.000 48.302 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.910 49.213 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.085 50.298 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.088 50.386 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 1.106 51.492 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y1 BUFR (Prop_bufr_I_O) 0.377 51.869 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.722 52.591 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X14Y43 FDCE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
------------------------------------------------------------------- -------------------
SLICE_X14Y43 FDCE (Prop_fdce_C_Q) 0.315 52.906 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/Q
net (fo=1, routed) 0.407 53.313 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r
SLICE_X13Y43 LUT2 (Prop_lut2_I0_O) 0.053 53.366 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1/O
net (fo=1, routed) 0.000 53.366 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1_n_0
SLICE_X13Y43 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
------------------------------------------------------------------- -------------------
(clock iclk1x0 rise edge) 52.006 52.006 r
AA10 0.000 52.006 r sns1_clkp (IN)
net (fo=0) 0.000 52.006 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.831 52.837 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.887 53.724 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.083 53.807 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.016 54.823 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y0 BUFR (Prop_bufr_I_O) 0.370 55.193 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.678 55.871 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X13Y43 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
clock pessimism 0.282 56.153
clock uncertainty -0.276 55.877
SLICE_X13Y43 FDRE (Setup_fdre_C_D) 0.035 55.912 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]
-------------------------------------------------------------------
required time 55.912
arrival time -53.366
-------------------------------------------------------------------
slack 2.547
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 3.577ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C
(falling edge-triggered cell FDCE clocked by iclk0 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
(rising edge-triggered cell FDRE clocked by iclk1x0 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x0
Path Type: Hold (Min at Fast Process Corner)
Requirement: -3.704ns (iclk1x0 rise@7.562ns - iclk0 fall@11.265ns)
Data Path Delay: 0.310ns (logic 0.151ns (48.735%) route 0.159ns (51.265%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: 0.100ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.055ns = ( 9.617 - 7.562 )
Source Clock Delay (SCD): 1.777ns = ( 13.042 - 11.265 )
Clock Pessimism Removal (CPR): 0.178ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk0 fall edge) 11.265 11.265 f
AA10 0.000 11.265 f sns1_clkp (IN)
net (fo=0) 0.000 11.265 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.412 11.677 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.487 12.164 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.050 12.214 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 0.433 12.647 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y1 BUFR (Prop_bufr_I_O) 0.090 12.737 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.305 13.042 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X14Y43 FDCE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
------------------------------------------------------------------- -------------------
SLICE_X14Y43 FDCE (Prop_fdce_C_Q) 0.123 13.165 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/Q
net (fo=1, routed) 0.159 13.324 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r
SLICE_X13Y43 LUT2 (Prop_lut2_I0_O) 0.028 13.352 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1/O
net (fo=1, routed) 0.000 13.352 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1_n_0
SLICE_X13Y43 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
------------------------------------------------------------------- -------------------
(clock iclk1x0 rise edge) 7.562 7.562 r
AA10 0.000 7.562 r sns1_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.481 8.043 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.593 8.636 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.053 8.689 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.490 9.179 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y0 BUFR (Prop_bufr_I_O) 0.093 9.272 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.345 9.617 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X13Y43 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
clock pessimism -0.178 9.439
clock uncertainty 0.276 9.715
SLICE_X13Y43 FDRE (Hold_fdre_C_D) 0.060 9.775 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]
-------------------------------------------------------------------
required time -9.775
arrival time 13.352
-------------------------------------------------------------------
slack 3.577
---------------------------------------------------------------------------------------------------
From Clock: iclk1x1
To Clock: iclk1
Setup : 0 Failing Endpoints, Worst Slack 5.033ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.147ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 5.033ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r_reg[6]/C
(rising edge-triggered cell FDRE clocked by iclk1x1 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/dout_r_reg[6]/D
(rising edge-triggered cell FDRE clocked by iclk1 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 7.407ns (iclk1 rise@29.784ns - iclk1x1 rise@22.377ns)
Data Path Delay: 1.874ns (logic 0.308ns (16.435%) route 1.566ns (83.565%))
Logic Levels: 0
Clock Path Skew: -0.207ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.867ns = ( 35.651 - 29.784 )
Source Clock Delay (SCD): 6.525ns = ( 28.902 - 22.377 )
Clock Pessimism Removal (CPR): 0.451ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x1 rise edge) 22.377 22.377 r
Y16 0.000 22.377 r sns2_clkp (IN)
net (fo=0) 0.000 22.377 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.857 23.234 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 2.173 25.407 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.088 25.495 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 1.633 27.128 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y3 BUFG (Prop_bufg_I_O) 0.120 27.248 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 1.654 28.902 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/CLK
SLICE_X8Y10 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r_reg[6]/C
------------------------------------------------------------------- -------------------
SLICE_X8Y10 FDRE (Prop_fdre_C_Q) 0.308 29.210 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r_reg[6]/Q
net (fo=1, routed) 1.566 30.776 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r[6]
SLICE_X9Y10 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/dout_r_reg[6]/D
------------------------------------------------------------------- -------------------
(clock iclk1 rise edge) 29.784 29.784 r
Y16 0.000 29.784 r sns2_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.779 30.563 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.801 32.363 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.083 32.446 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.550 33.996 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.113 34.109 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 1.542 35.651 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/den_r_reg_0
SLICE_X9Y10 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/dout_r_reg[6]/C
clock pessimism 0.451 36.102
clock uncertainty -0.276 35.826
SLICE_X9Y10 FDRE (Setup_fdre_C_D) -0.017 35.809 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/dout_r_reg[6]
-------------------------------------------------------------------
required time 35.809
arrival time -30.776
-------------------------------------------------------------------
slack 5.033
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.147ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[5]/C
(rising edge-triggered cell FDRE clocked by iclk1x1 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[5]/D
(rising edge-triggered cell FDRE clocked by iclk1 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (iclk1 rise@66.821ns - iclk1x1 rise@66.821ns)
Data Path Delay: 0.752ns (logic 0.118ns (15.702%) route 0.634ns (84.298%))
Logic Levels: 0
Clock Path Skew: 0.296ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 3.214ns = ( 70.035 - 66.821 )
Source Clock Delay (SCD): 2.653ns = ( 69.474 - 66.821 )
Clock Pessimism Removal (CPR): 0.265ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x1 rise edge) 66.821 66.821 r
Y16 0.000 66.821 r sns2_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.360 67.181 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.000 68.180 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.050 68.230 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 0.584 68.814 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y3 BUFG (Prop_bufg_I_O) 0.026 68.840 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.634 69.474 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/CLK
SLICE_X10Y10 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[5]/C
------------------------------------------------------------------- -------------------
SLICE_X10Y10 FDRE (Prop_fdre_C_Q) 0.118 69.592 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[5]/Q
net (fo=1, routed) 0.634 70.226 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r[5]
SLICE_X9Y10 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[5]/D
------------------------------------------------------------------- -------------------
(clock iclk1 rise edge) 66.821 66.821 r
Y16 0.000 66.821 r sns2_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.428 67.249 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.196 68.445 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.053 68.498 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.651 69.149 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.030 69.179 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.856 70.035 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/den_r_reg_0
SLICE_X9Y10 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[5]/C
clock pessimism -0.265 69.770
clock uncertainty 0.276 70.046
SLICE_X9Y10 FDRE (Hold_fdre_C_D) 0.032 70.078 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[5]
-------------------------------------------------------------------
required time -70.078
arrival time 70.226
-------------------------------------------------------------------
slack 0.147
---------------------------------------------------------------------------------------------------
From Clock: iclk1
To Clock: iclk1x1
Setup : 0 Failing Endpoints, Worst Slack 2.549ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 3.350ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.549ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C
(falling edge-triggered cell FDCE clocked by iclk1 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
(rising edge-triggered cell FDRE clocked by iclk1x1 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 3.704ns (iclk1x1 rise@52.006ns - iclk1 fall@48.302ns)
Data Path Delay: 0.748ns (logic 0.325ns (43.459%) route 0.423ns (56.541%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: -0.202ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.864ns = ( 57.870 - 52.006 )
Source Clock Delay (SCD): 6.522ns = ( 54.824 - 48.302 )
Clock Pessimism Removal (CPR): 0.456ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1 fall edge) 48.302 48.302 f
Y16 0.000 48.302 f sns2_clkp (IN)
net (fo=0) 0.000 48.302 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.857 49.160 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 2.173 51.332 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.088 51.420 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.633 53.053 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.120 53.173 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 1.651 54.824 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X13Y14 FDCE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
------------------------------------------------------------------- -------------------
SLICE_X13Y14 FDCE (Prop_fdce_C_Q) 0.272 55.096 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/Q
net (fo=1, routed) 0.423 55.519 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r
SLICE_X14Y14 LUT2 (Prop_lut2_I0_O) 0.053 55.572 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1__0/O
net (fo=1, routed) 0.000 55.572 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1__0_n_0
SLICE_X14Y14 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
------------------------------------------------------------------- -------------------
(clock iclk1x1 rise edge) 52.006 52.006 r
Y16 0.000 52.006 r sns2_clkp (IN)
net (fo=0) 0.000 52.006 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.779 52.785 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.801 54.585 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.083 54.668 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 1.550 56.218 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y3 BUFG (Prop_bufg_I_O) 0.113 56.331 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 1.539 57.870 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X14Y14 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
clock pessimism 0.456 58.326
clock uncertainty -0.276 58.050
SLICE_X14Y14 FDRE (Setup_fdre_C_D) 0.071 58.121 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]
-------------------------------------------------------------------
required time 58.121
arrival time -55.572
-------------------------------------------------------------------
slack 2.549
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 3.350ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C
(falling edge-triggered cell FDCE clocked by iclk1 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
(rising edge-triggered cell FDRE clocked by iclk1x1 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x1
Path Type: Hold (Min at Fast Process Corner)
Requirement: -3.704ns (iclk1x1 rise@7.562ns - iclk1 fall@11.265ns)
Data Path Delay: 0.301ns (logic 0.135ns (44.875%) route 0.166ns (55.125%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: 0.291ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 3.210ns = ( 10.772 - 7.562 )
Source Clock Delay (SCD): 2.651ns = ( 13.917 - 11.265 )
Clock Pessimism Removal (CPR): 0.268ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1 fall edge) 11.265 11.265 f
Y16 0.000 11.265 f sns2_clkp (IN)
net (fo=0) 0.000 11.265 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.360 11.625 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.000 12.625 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.050 12.675 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.584 13.259 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.026 13.285 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.632 13.917 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X13Y14 FDCE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
------------------------------------------------------------------- -------------------
SLICE_X13Y14 FDCE (Prop_fdce_C_Q) 0.107 14.024 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/Q
net (fo=1, routed) 0.166 14.189 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r
SLICE_X14Y14 LUT2 (Prop_lut2_I0_O) 0.028 14.217 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1__0/O
net (fo=1, routed) 0.000 14.217 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1__0_n_0
SLICE_X14Y14 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
------------------------------------------------------------------- -------------------
(clock iclk1x1 rise edge) 7.562 7.562 r
Y16 0.000 7.562 r sns2_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.428 7.990 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.196 9.186 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.053 9.239 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 0.651 9.890 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y3 BUFG (Prop_bufg_I_O) 0.030 9.920 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.852 10.772 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X14Y14 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
clock pessimism -0.268 10.504
clock uncertainty 0.276 10.780
SLICE_X14Y14 FDRE (Hold_fdre_C_D) 0.087 10.867 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]
-------------------------------------------------------------------
required time -10.867
arrival time 14.217
-------------------------------------------------------------------
slack 3.350
---------------------------------------------------------------------------------------------------
From Clock: iclk2
To Clock: iclk1x2
Setup : 0 Failing Endpoints, Worst Slack 2.827ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 3.461ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.827ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C
(falling edge-triggered cell FDCE clocked by iclk2 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
(rising edge-triggered cell FDRE clocked by iclk1x2 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x2
Path Type: Setup (Max at Slow Process Corner)
Requirement: 3.704ns (iclk1x2 rise@52.006ns - iclk2 fall@48.302ns)
Data Path Delay: 0.531ns (logic 0.325ns (61.173%) route 0.206ns (38.827%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.773ns = ( 55.779 - 52.006 )
Source Clock Delay (SCD): 4.195ns = ( 52.497 - 48.302 )
Clock Pessimism Removal (CPR): 0.282ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk2 fall edge) 48.302 48.302 f
T21 0.000 48.302 f sns3_clkp (IN)
net (fo=0) 0.000 48.302 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.880 49.182 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.085 50.267 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.088 50.355 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 1.106 51.461 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y5 BUFR (Prop_bufr_I_O) 0.377 51.838 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.659 52.497 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X7Y64 FDCE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
------------------------------------------------------------------- -------------------
SLICE_X7Y64 FDCE (Prop_fdce_C_Q) 0.272 52.769 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/Q
net (fo=1, routed) 0.206 52.975 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r
SLICE_X6Y64 LUT2 (Prop_lut2_I0_O) 0.053 53.028 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1__1/O
net (fo=1, routed) 0.000 53.028 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1__1_n_0
SLICE_X6Y64 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
------------------------------------------------------------------- -------------------
(clock iclk1x2 rise edge) 52.006 52.006 r
T21 0.000 52.006 r sns3_clkp (IN)
net (fo=0) 0.000 52.006 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.801 52.807 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.887 53.694 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.083 53.777 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.016 54.793 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y4 BUFR (Prop_bufr_I_O) 0.370 55.163 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.616 55.779 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X6Y64 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
clock pessimism 0.282 56.061
clock uncertainty -0.276 55.785
SLICE_X6Y64 FDRE (Setup_fdre_C_D) 0.071 55.856 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]
-------------------------------------------------------------------
required time 55.856
arrival time -53.028
-------------------------------------------------------------------
slack 2.827
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 3.461ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C
(falling edge-triggered cell FDCE clocked by iclk2 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
(rising edge-triggered cell FDRE clocked by iclk1x2 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x2
Path Type: Hold (Min at Fast Process Corner)
Requirement: -3.704ns (iclk1x2 rise@7.562ns - iclk2 fall@11.265ns)
Data Path Delay: 0.216ns (logic 0.135ns (62.418%) route 0.081ns (37.582%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: 0.096ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.988ns = ( 9.550 - 7.562 )
Source Clock Delay (SCD): 1.714ns = ( 12.979 - 11.265 )
Clock Pessimism Removal (CPR): 0.178ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk2 fall edge) 11.265 11.265 f
T21 0.000 11.265 f sns3_clkp (IN)
net (fo=0) 0.000 11.265 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.382 11.647 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.487 12.134 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.050 12.184 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 0.433 12.617 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y5 BUFR (Prop_bufr_I_O) 0.090 12.707 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.272 12.979 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X7Y64 FDCE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
------------------------------------------------------------------- -------------------
SLICE_X7Y64 FDCE (Prop_fdce_C_Q) 0.107 13.086 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/Q
net (fo=1, routed) 0.081 13.167 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r
SLICE_X6Y64 LUT2 (Prop_lut2_I0_O) 0.028 13.195 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1__1/O
net (fo=1, routed) 0.000 13.195 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1__1_n_0
SLICE_X6Y64 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
------------------------------------------------------------------- -------------------
(clock iclk1x2 rise edge) 7.562 7.562 r
T21 0.000 7.562 r sns3_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.451 8.012 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.593 8.606 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.053 8.659 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.490 9.149 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y4 BUFR (Prop_bufr_I_O) 0.093 9.242 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.308 9.550 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X6Y64 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
clock pessimism -0.178 9.371
clock uncertainty 0.276 9.648
SLICE_X6Y64 FDRE (Hold_fdre_C_D) 0.087 9.735 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]
-------------------------------------------------------------------
required time -9.735
arrival time 13.195
-------------------------------------------------------------------
slack 3.461
---------------------------------------------------------------------------------------------------
From Clock: iclk1x2
To Clock: iclk2
Setup : 0 Failing Endpoints, Worst Slack 5.486ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.102ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 5.486ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r_reg[8]/C
(rising edge-triggered cell FDRE clocked by iclk1x2 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/dout_r_reg[8]/D
(rising edge-triggered cell FDRE clocked by iclk2 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk2
Path Type: Setup (Max at Slow Process Corner)
Requirement: 7.407ns (iclk2 rise@29.784ns - iclk1x2 rise@22.377ns)
Data Path Delay: 1.424ns (logic 0.246ns (17.273%) route 1.178ns (82.727%))
Logic Levels: 0
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.825ns = ( 33.609 - 29.784 )
Source Clock Delay (SCD): 4.191ns = ( 26.567 - 22.377 )
Clock Pessimism Removal (CPR): 0.277ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x2 rise edge) 22.377 22.377 r
T21 0.000 22.377 r sns3_clkp (IN)
net (fo=0) 0.000 22.377 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.880 23.256 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.085 24.341 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.088 24.429 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.106 25.535 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y4 BUFR (Prop_bufr_I_O) 0.377 25.912 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.655 26.567 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/CLK
SLICE_X5Y67 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r_reg[8]/C
------------------------------------------------------------------- -------------------
SLICE_X5Y67 FDRE (Prop_fdre_C_Q) 0.246 26.813 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r_reg[8]/Q
net (fo=1, routed) 1.178 27.992 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/pre_dout_r[8]
SLICE_X9Y67 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/dout_r_reg[8]/D
------------------------------------------------------------------- -------------------
(clock iclk2 rise edge) 29.784 29.784 r
T21 0.000 29.784 r sns3_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.801 30.585 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.887 31.472 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.083 31.555 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 1.016 32.571 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y5 BUFR (Prop_bufr_I_O) 0.370 32.941 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.668 33.609 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/rst_early_master_reg
SLICE_X9Y67 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/dout_r_reg[8]/C
clock pessimism 0.277 33.886
clock uncertainty -0.276 33.609
SLICE_X9Y67 FDRE (Setup_fdre_C_D) -0.132 33.477 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[2].sens_103993_lane_i/dout_r_reg[8]
-------------------------------------------------------------------
required time 33.477
arrival time -27.992
-------------------------------------------------------------------
slack 5.486
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.102ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[2]/C
(rising edge-triggered cell FDRE clocked by iclk1x2 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[2]/D
(rising edge-triggered cell FDRE clocked by iclk2 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk2
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (iclk2 rise@66.821ns - iclk1x2 rise@66.821ns)
Data Path Delay: 0.480ns (logic 0.091ns (18.945%) route 0.389ns (81.055%))
Logic Levels: 0
Clock Path Skew: 0.101ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.015ns = ( 68.836 - 66.821 )
Source Clock Delay (SCD): 1.739ns = ( 68.560 - 66.821 )
Clock Pessimism Removal (CPR): 0.175ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x2 rise edge) 66.821 66.821 r
T21 0.000 66.821 r sns3_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.382 67.203 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.487 67.690 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.050 67.740 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.433 68.173 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y4 BUFR (Prop_bufr_I_O) 0.090 68.263 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.297 68.560 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/CLK
SLICE_X9Y66 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[2]/C
------------------------------------------------------------------- -------------------
SLICE_X9Y66 FDRE (Prop_fdre_C_Q) 0.091 68.651 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[2]/Q
net (fo=1, routed) 0.389 69.040 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r[2]
SLICE_X11Y67 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[2]/D
------------------------------------------------------------------- -------------------
(clock iclk2 rise edge) 66.821 66.821 r
T21 0.000 66.821 r sns3_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.451 67.272 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.593 67.865 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.053 67.918 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 0.490 68.408 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y5 BUFR (Prop_bufr_I_O) 0.093 68.501 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.335 68.836 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/rst_early_master_reg
SLICE_X11Y67 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[2]/C
clock pessimism -0.175 68.661
clock uncertainty 0.276 68.937
SLICE_X11Y67 FDRE (Hold_fdre_C_D) 0.001 68.938 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[2]
-------------------------------------------------------------------
required time -68.938
arrival time 69.040
-------------------------------------------------------------------
slack 0.102
---------------------------------------------------------------------------------------------------
From Clock: iclk3
To Clock: iclk1x3
Setup : 0 Failing Endpoints, Worst Slack 2.725ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 3.318ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.725ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C
(falling edge-triggered cell FDCE clocked by iclk3 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
(rising edge-triggered cell FDRE clocked by iclk1x3 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x3
Path Type: Setup (Max at Slow Process Corner)
Requirement: 3.704ns (iclk1x3 rise@52.006ns - iclk3 fall@48.302ns)
Data Path Delay: 0.525ns (logic 0.325ns (61.848%) route 0.200ns (38.153%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: -0.212ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.452ns = ( 57.458 - 52.006 )
Source Clock Delay (SCD): 6.008ns = ( 54.311 - 48.302 )
Clock Pessimism Removal (CPR): 0.344ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk3 fall edge) 48.302 48.302 f
R16 0.000 48.302 f sns4_clkp (IN)
net (fo=0) 0.000 48.302 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.856 49.158 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.502 50.660 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.088 50.748 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 2.009 52.757 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y12 BUFG (Prop_bufg_I_O) 0.120 52.877 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 1.434 54.311 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X29Y75 FDCE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
------------------------------------------------------------------- -------------------
SLICE_X29Y75 FDCE (Prop_fdce_C_Q) 0.272 54.583 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/Q
net (fo=1, routed) 0.200 54.783 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r
SLICE_X28Y75 LUT2 (Prop_lut2_I0_O) 0.053 54.836 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1__2/O
net (fo=1, routed) 0.000 54.836 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1__2_n_0
SLICE_X28Y75 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
------------------------------------------------------------------- -------------------
(clock iclk1x3 rise edge) 52.006 52.006 r
R16 0.000 52.006 r sns4_clkp (IN)
net (fo=0) 0.000 52.006 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.777 52.783 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.242 54.024 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.083 54.107 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 1.911 56.018 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.113 56.131 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 1.327 57.458 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X28Y75 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
clock pessimism 0.344 57.802
clock uncertainty -0.276 57.526
SLICE_X28Y75 FDRE (Setup_fdre_C_D) 0.035 57.561 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]
-------------------------------------------------------------------
required time 57.561
arrival time -54.836
-------------------------------------------------------------------
slack 2.725
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 3.318ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C
(falling edge-triggered cell FDCE clocked by iclk3 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
(rising edge-triggered cell FDRE clocked by iclk1x3 {rise@-7.253ns fall@0.154ns period=14.815ns})
Path Group: iclk1x3
Path Type: Hold (Min at Fast Process Corner)
Requirement: -3.704ns (iclk1x3 rise@7.562ns - iclk3 fall@11.265ns)
Data Path Delay: 0.220ns (logic 0.135ns (61.229%) route 0.085ns (38.771%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: 0.270ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.951ns = ( 10.513 - 7.562 )
Source Clock Delay (SCD): 2.470ns = ( 13.736 - 11.265 )
Clock Pessimism Removal (CPR): 0.211ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk3 fall edge) 11.265 11.265 f
R16 0.000 11.265 f sns4_clkp (IN)
net (fo=0) 0.000 11.265 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.358 11.623 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.701 12.324 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.050 12.374 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.771 13.145 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y12 BUFG (Prop_bufg_I_O) 0.026 13.171 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.565 13.736 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X29Y75 FDCE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
------------------------------------------------------------------- -------------------
SLICE_X29Y75 FDCE (Prop_fdce_C_Q) 0.107 13.843 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/Q
net (fo=1, routed) 0.085 13.928 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r
SLICE_X28Y75 LUT2 (Prop_lut2_I0_O) 0.028 13.956 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1__2/O
net (fo=1, routed) 0.000 13.956 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r[0]_i_1__2_n_0
SLICE_X28Y75 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/D
------------------------------------------------------------------- -------------------
(clock iclk1x3 rise edge) 7.562 7.562 r
R16 0.000 7.562 r sns4_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.427 7.988 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.840 8.828 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.053 8.881 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 0.840 9.721 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.030 9.751 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.762 10.513 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X28Y75 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
clock pessimism -0.211 10.302
clock uncertainty 0.276 10.578
SLICE_X28Y75 FDRE (Hold_fdre_C_D) 0.060 10.638 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]
-------------------------------------------------------------------
required time -10.638
arrival time 13.956
-------------------------------------------------------------------
slack 3.318
---------------------------------------------------------------------------------------------------
From Clock: iclk1x3
To Clock: iclk3
Setup : 0 Failing Endpoints, Worst Slack 5.084ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.146ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 5.084ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[9]/C
(rising edge-triggered cell FDRE clocked by iclk1x3 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[9]/D
(rising edge-triggered cell FDRE clocked by iclk3 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk3
Path Type: Setup (Max at Slow Process Corner)
Requirement: 7.407ns (iclk3 rise@29.784ns - iclk1x3 rise@22.377ns)
Data Path Delay: 1.648ns (logic 0.282ns (17.113%) route 1.366ns (82.887%))
Logic Levels: 0
Clock Path Skew: -0.277ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.405ns = ( 35.189 - 29.784 )
Source Clock Delay (SCD): 6.021ns = ( 28.398 - 22.377 )
Clock Pessimism Removal (CPR): 0.339ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x3 rise edge) 22.377 22.377 r
R16 0.000 22.377 r sns4_clkp (IN)
net (fo=0) 0.000 22.377 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.856 23.232 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.502 24.734 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.088 24.822 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 2.009 26.831 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.120 26.951 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 1.447 28.398 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/CLK
SLICE_X30Y65 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[9]/C
------------------------------------------------------------------- -------------------
SLICE_X30Y65 FDRE (Prop_fdre_C_Q) 0.282 28.680 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r_reg[9]/Q
net (fo=1, routed) 1.366 30.046 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/pre_dout_r[9]
SLICE_X35Y64 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[9]/D
------------------------------------------------------------------- -------------------
(clock iclk3 rise edge) 29.784 29.784 r
R16 0.000 29.784 r sns4_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.777 30.561 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.242 31.802 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.083 31.885 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.911 33.796 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y12 BUFG (Prop_bufg_I_O) 0.113 33.909 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 1.280 35.189 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/den_r_reg_0
SLICE_X35Y64 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[9]/C
clock pessimism 0.339 35.528
clock uncertainty -0.276 35.252
SLICE_X35Y64 FDRE (Setup_fdre_C_D) -0.122 35.130 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[0].sens_103993_lane_i/dout_r_reg[9]
-------------------------------------------------------------------
required time 35.130
arrival time -30.046
-------------------------------------------------------------------
slack 5.084
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.146ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/pre_dout_r_reg[4]/C
(rising edge-triggered cell FDRE clocked by iclk1x3 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/dout_r_reg[4]/D
(rising edge-triggered cell FDRE clocked by iclk3 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: iclk3
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (iclk3 rise@66.821ns - iclk1x3 rise@66.821ns)
Data Path Delay: 0.667ns (logic 0.107ns (16.051%) route 0.560ns (83.949%))
Logic Levels: 0
Clock Path Skew: 0.244ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.931ns = ( 69.752 - 66.821 )
Source Clock Delay (SCD): 2.479ns = ( 69.300 - 66.821 )
Clock Pessimism Removal (CPR): 0.208ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x3 rise edge) 66.821 66.821 r
R16 0.000 66.821 r sns4_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.358 67.179 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.701 67.879 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.050 67.929 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 0.771 68.700 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.026 68.726 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.574 69.300 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/CLK
SLICE_X30Y65 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/pre_dout_r_reg[4]/C
------------------------------------------------------------------- -------------------
SLICE_X30Y65 FDRE (Prop_fdre_C_Q) 0.107 69.407 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/pre_dout_r_reg[4]/Q
net (fo=1, routed) 0.560 69.967 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/pre_dout_r[4]
SLICE_X35Y66 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/dout_r_reg[4]/D
------------------------------------------------------------------- -------------------
(clock iclk3 rise edge) 66.821 66.821 r
R16 0.000 66.821 r sns4_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.427 67.247 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.840 68.087 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.053 68.140 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.840 68.980 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y12 BUFG (Prop_bufg_I_O) 0.030 69.010 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.742 69.752 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/den_r_reg_0
SLICE_X35Y66 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/dout_r_reg[4]/C
clock pessimism -0.208 69.544
clock uncertainty 0.276 69.820
SLICE_X35Y66 FDRE (Hold_fdre_C_D) 0.000 69.820 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/lane_block[1].sens_103993_lane_i/dout_r_reg[4]
-------------------------------------------------------------------
required time -69.820
arrival time 69.967
-------------------------------------------------------------------
slack 0.146
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: axihp_clk
To Clock: axihp_clk
Setup : 0 Failing Endpoints, Worst Slack 2.567ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.489ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.567ns (required time - arrival time)
Source: sync_resets_i/rst_block[9].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/C
(rising edge-triggered cell FDRE clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns})
Destination: compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_out_fifo_i/eof_written_wclk_i/in_reg_reg/CLR
(recovery check against rising-edge clock axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 6.667ns (axihp_clk rise@6.667ns - axihp_clk rise@0.000ns)
Data Path Delay: 3.436ns (logic 0.269ns (7.829%) route 3.167ns (92.171%))
Logic Levels: 0
Clock Path Skew: -0.337ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.482ns = ( 11.149 - 6.667 )
Source Clock Delay (SCD): 5.048ns
Clock Pessimism Removal (CPR): 0.229ns
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.124ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.610 1.610 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.088 1.698 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.621 3.319 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.120 3.439 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3871, routed) 1.609 5.048 sync_resets_i/rst_block[9].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk
SLICE_X29Y154 FDRE r sync_resets_i/rst_block[9].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/C
------------------------------------------------------------------- -------------------
SLICE_X29Y154 FDRE (Prop_fdre_C_Q) 0.269 5.317 f sync_resets_i/rst_block[9].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/Q
net (fo=335, routed) 3.167 8.484 compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_out_fifo_i/eof_written_wclk_i/rst[0]
SLICE_X37Y72 FDCE f compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_out_fifo_i/eof_written_wclk_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
6.667 6.667 r
BUFGCTRL_X0Y17 BUFG 0.000 6.667 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.476 8.143 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.083 8.226 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.538 9.764 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.113 9.877 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3871, routed) 1.272 11.149 compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_out_fifo_i/eof_written_wclk_i/hclk
SLICE_X37Y72 FDCE r compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_out_fifo_i/eof_written_wclk_i/in_reg_reg/C
clock pessimism 0.229 11.378
clock uncertainty -0.071 11.306
SLICE_X37Y72 FDCE (Recov_fdce_C_CLR) -0.255 11.051 compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_out_fifo_i/eof_written_wclk_i/in_reg_reg
-------------------------------------------------------------------
required time 11.051
arrival time -8.484
-------------------------------------------------------------------
slack 2.567
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.489ns (arrival time - required time)
Source: sync_resets_i/rst_block[9].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/C
(rising edge-triggered cell FDRE clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns})
Destination: sata_top/nhrst_r_reg[0]/CLR
(removal check against rising-edge clock axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (axihp_clk rise@0.000ns - axihp_clk rise@0.000ns)
Data Path Delay: 0.517ns (logic 0.100ns (19.328%) route 0.417ns (80.672%))
Logic Levels: 0
Clock Path Skew: 0.097ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.281ns
Source Clock Delay (SCD): 1.891ns
Clock Pessimism Removal (CPR): 0.293ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.604 0.604 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.050 0.654 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.577 1.231 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.257 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3871, routed) 0.634 1.891 sync_resets_i/rst_block[9].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk
SLICE_X29Y154 FDRE r sync_resets_i/rst_block[9].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/C
------------------------------------------------------------------- -------------------
SLICE_X29Y154 FDRE (Prop_fdre_C_Q) 0.100 1.991 f sync_resets_i/rst_block[9].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/Q
net (fo=335, routed) 0.417 2.408 sata_top/Q[0]
SLICE_X33Y141 FDCE f sata_top/nhrst_r_reg[0]/CLR
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.816 0.816 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.053 0.869 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.643 1.512 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 1.542 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3871, routed) 0.739 2.281 sata_top/hclk
SLICE_X33Y141 FDCE r sata_top/nhrst_r_reg[0]/C
clock pessimism -0.293 1.988
SLICE_X33Y141 FDCE (Remov_fdce_C_CLR) -0.069 1.919 sata_top/nhrst_r_reg[0]
-------------------------------------------------------------------
required time -1.919
arrival time 2.408
-------------------------------------------------------------------
slack 0.489
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: ddr3_mclk
To Clock: ddr3_mclk
Setup : 0 Failing Endpoints, Worst Slack 0.577ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.303ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.577ns (required time - arrival time)
Source: sync_resets_i/rst_early_master_reg_replica_15/C
(rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Destination: compressor393_i/cmprs_afi0_mux_i/en_rst_i/in_reg_reg/CLR
(recovery check against rising-edge clock ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 5.000ns (ddr3_mclk rise@6.250ns - ddr3_mclk rise@1.250ns)
Data Path Delay: 4.021ns (logic 0.246ns (6.118%) route 3.775ns (93.882%))
Logic Levels: 0
Clock Path Skew: -0.023ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.518ns = ( 10.768 - 6.250 )
Source Clock Delay (SCD): 4.857ns = ( 6.107 - 1.250 )
Clock Pessimism Removal (CPR): 0.316ns
Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.156ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y17 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.575 2.825 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.088 2.913 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 1.628 4.541 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.120 4.661 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=34863, routed) 1.446 6.107 sync_resets_i/mclk
SLICE_X9Y72 FDRE r sync_resets_i/rst_early_master_reg_replica_15/C
------------------------------------------------------------------- -------------------
SLICE_X9Y72 FDRE (Prop_fdre_C_Q) 0.246 6.353 f sync_resets_i/rst_early_master_reg_replica_15/Q
net (fo=394, routed) 3.775 10.128 compressor393_i/cmprs_afi0_mux_i/en_rst_i/rst[0]_repN_15_alias
SLICE_X22Y81 FDCE f compressor393_i/cmprs_afi0_mux_i/en_rst_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
6.250 6.250 r
BUFGCTRL_X0Y17 BUFG 0.000 6.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.437 7.687 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.083 7.770 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 1.544 9.314 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.113 9.427 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=34863, routed) 1.341 10.768 compressor393_i/cmprs_afi0_mux_i/en_rst_i/mclk
SLICE_X22Y81 FDCE r compressor393_i/cmprs_afi0_mux_i/en_rst_i/in_reg_reg/C
clock pessimism 0.316 11.084
clock uncertainty -0.085 10.999
SLICE_X22Y81 FDCE (Recov_fdce_C_CLR) -0.294 10.705 compressor393_i/cmprs_afi0_mux_i/en_rst_i/in_reg_reg
-------------------------------------------------------------------
required time 10.705
arrival time -10.128
-------------------------------------------------------------------
slack 0.577
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.303ns (arrival time - required time)
Source: sync_resets_i/rst_early_master_reg_replica_11/C
(rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Destination: compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/frame_start_xclk_i/in_reg_reg/CLR
(removal check against rising-edge clock ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (ddr3_mclk rise@1.250ns - ddr3_mclk rise@1.250ns)
Data Path Delay: 0.254ns (logic 0.091ns (35.850%) route 0.163ns (64.150%))
Logic Levels: 0
Clock Path Skew: 0.058ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.275ns = ( 3.525 - 1.250 )
Source Clock Delay (SCD): 1.762ns = ( 3.012 - 1.250 )
Clock Pessimism Removal (CPR): 0.455ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y17 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.580 1.830 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.050 1.880 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 0.559 2.439 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 2.465 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=34863, routed) 0.547 3.012 sync_resets_i/mclk
SLICE_X89Y79 FDRE r sync_resets_i/rst_early_master_reg_replica_11/C
------------------------------------------------------------------- -------------------
SLICE_X89Y79 FDRE (Prop_fdre_C_Q) 0.091 3.103 f sync_resets_i/rst_early_master_reg_replica_11/Q
net (fo=478, routed) 0.163 3.266 compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/frame_start_xclk_i/rst[0]_repN_11_alias
SLICE_X95Y79 FDCE f compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/frame_start_xclk_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y17 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.796 2.046 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.053 2.099 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 0.623 2.722 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.030 2.752 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=34863, routed) 0.773 3.525 compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/frame_start_xclk_i/mclk
SLICE_X95Y79 FDCE r compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/frame_start_xclk_i/in_reg_reg/C
clock pessimism -0.455 3.070
SLICE_X95Y79 FDCE (Remov_fdce_C_CLR) -0.107 2.963 compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/frame_start_xclk_i/in_reg_reg
-------------------------------------------------------------------
required time -2.963
arrival time 3.266
-------------------------------------------------------------------
slack 0.303
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: iclk0
To Clock: iclk0
Setup : 0 Failing Endpoints, Worst Slack 34.838ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.578ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 34.838ns (required time - arrival time)
Source: sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/C
(rising edge-triggered cell FDRE clocked by iclk0 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[0].sensor_membuf_i/page_written_i/in_reg_reg/CLR
(recovery check against rising-edge clock iclk0 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 37.037ns (iclk0 rise@66.821ns - iclk0 rise@29.784ns)
Data Path Delay: 1.805ns (logic 0.269ns (14.901%) route 1.536ns (85.099%))
Logic Levels: 0
Clock Path Skew: 0.017ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.927ns = ( 70.748 - 66.821 )
Source Clock Delay (SCD): 4.289ns = ( 34.073 - 29.784 )
Clock Pessimism Removal (CPR): 0.379ns
Clock Uncertainty: 0.156ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk0 rise edge) 29.784 29.784 r
AA10 0.000 29.784 r sns1_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.910 30.694 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.085 31.779 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.088 31.867 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 1.106 32.973 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y1 BUFR (Prop_bufr_I_O) 0.377 33.350 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.723 34.073 sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/pclk[0]
SLICE_X15Y49 FDRE r sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/C
------------------------------------------------------------------- -------------------
SLICE_X15Y49 FDRE (Prop_fdre_C_Q) 0.269 34.342 f sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/Q
net (fo=22, routed) 1.536 35.879 sensors393_i/sensor_channel_block[0].sensor_membuf_i/page_written_i/rst[0]
SLICE_X45Y47 FDCE f sensors393_i/sensor_channel_block[0].sensor_membuf_i/page_written_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk0 rise edge) 66.821 66.821 r
AA10 0.000 66.821 r sns1_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.831 67.652 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.887 68.539 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.083 68.622 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 1.016 69.638 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y1 BUFR (Prop_bufr_I_O) 0.370 70.008 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.740 70.748 sensors393_i/sensor_channel_block[0].sensor_membuf_i/page_written_i/CLK
SLICE_X45Y47 FDCE r sensors393_i/sensor_channel_block[0].sensor_membuf_i/page_written_i/in_reg_reg/C
clock pessimism 0.379 71.127
clock uncertainty -0.156 70.971
SLICE_X45Y47 FDCE (Recov_fdce_C_CLR) -0.255 70.716 sensors393_i/sensor_channel_block[0].sensor_membuf_i/page_written_i/in_reg_reg
-------------------------------------------------------------------
required time 70.716
arrival time -35.879
-------------------------------------------------------------------
slack 34.838
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.578ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/en_pclk_reg/C
(rising edge-triggered cell FDRE clocked by iclk0 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/CLR
(removal check against rising-edge clock iclk0 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (iclk0 rise@29.784ns - iclk0 rise@29.784ns)
Data Path Delay: 0.552ns (logic 0.171ns (30.957%) route 0.381ns (69.044%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.043ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.092ns = ( 31.876 - 29.784 )
Source Clock Delay (SCD): 1.811ns = ( 31.595 - 29.784 )
Clock Pessimism Removal (CPR): 0.238ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk0 rise edge) 29.784 29.784 r
AA10 0.000 29.784 r sns1_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.412 30.196 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.487 30.683 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.050 30.733 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 0.433 31.166 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y1 BUFR (Prop_bufr_I_O) 0.090 31.256 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.339 31.595 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/rst_early_master_reg
SLICE_X34Y47 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/en_pclk_reg/C
------------------------------------------------------------------- -------------------
SLICE_X34Y47 FDRE (Prop_fdre_C_Q) 0.107 31.702 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/en_pclk_reg/Q
net (fo=1, routed) 0.239 31.941 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/en_pclk
SLICE_X37Y47 LUT1 (Prop_lut1_I0_O) 0.064 32.005 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_i_2__0/O
net (fo=2, routed) 0.142 32.147 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/rst0
SLICE_X39Y49 FDCE f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk0 rise edge) 29.784 29.784 r
AA10 0.000 29.784 r sns1_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.481 30.265 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.593 30.858 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.053 30.911 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 0.490 31.401 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y1 BUFR (Prop_bufr_I_O) 0.093 31.494 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.382 31.876 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/rst_early_master_reg
SLICE_X39Y49 FDCE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/C
clock pessimism -0.238 31.638
SLICE_X39Y49 FDCE (Remov_fdce_C_CLR) -0.069 31.569 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg
-------------------------------------------------------------------
required time -31.569
arrival time 32.147
-------------------------------------------------------------------
slack 0.578
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: iclk1x0
To Clock: iclk0
Setup : 0 Failing Endpoints, Worst Slack 2.308ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 3.676ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.308ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
(rising edge-triggered cell FDRE clocked by iclk1x0 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
(recovery check against rising-edge clock iclk0 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 3.704ns (iclk0 fall@11.265ns - iclk1x0 rise@7.562ns)
Data Path Delay: 0.791ns (logic 0.269ns (34.000%) route 0.522ns (66.000%))
Logic Levels: 0
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.865ns = ( 15.130 - 11.265 )
Source Clock Delay (SCD): 4.288ns = ( 11.850 - 7.562 )
Clock Pessimism Removal (CPR): 0.282ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x0 rise edge) 7.562 7.562 r
AA10 0.000 7.562 r sns1_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.910 8.472 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.085 9.557 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.088 9.645 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.106 10.751 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y0 BUFR (Prop_bufr_I_O) 0.377 11.128 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.722 11.850 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X13Y43 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X13Y43 FDRE (Prop_fdre_C_Q) 0.269 12.119 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/Q
net (fo=30, routed) 0.522 12.641 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/p_0_in
SLICE_X14Y43 FDCE f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk0 fall edge) 11.265 11.265 f
AA10 0.000 11.265 f sns1_clkp (IN)
net (fo=0) 0.000 11.265 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.831 12.096 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.887 12.983 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.083 13.066 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 1.016 14.082 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y1 BUFR (Prop_bufr_I_O) 0.370 14.452 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.678 15.130 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X14Y43 FDCE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
clock pessimism 0.282 15.413
clock uncertainty -0.276 15.137
SLICE_X14Y43 FDCE (Recov_fdce_C_CLR) -0.187 14.950 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg
-------------------------------------------------------------------
required time 14.950
arrival time -12.641
-------------------------------------------------------------------
slack 2.308
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 3.676ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
(rising edge-triggered cell FDRE clocked by iclk1x0 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
(removal check against rising-edge clock iclk0 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: -3.704ns (iclk0 fall@48.302ns - iclk1x0 rise@52.006ns)
Data Path Delay: 0.304ns (logic 0.100ns (32.875%) route 0.204ns (67.126%))
Logic Levels: 0
Clock Path Skew: 0.100ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.055ns = ( 50.358 - 48.302 )
Source Clock Delay (SCD): 1.777ns = ( 53.783 - 52.006 )
Clock Pessimism Removal (CPR): 0.178ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x0 rise edge) 52.006 52.006 r
AA10 0.000 52.006 r sns1_clkp (IN)
net (fo=0) 0.000 52.006 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.412 52.418 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.487 52.905 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.050 52.955 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.433 53.388 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y0 BUFR (Prop_bufr_I_O) 0.090 53.478 r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.305 53.783 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X13Y43 FDRE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X13Y43 FDRE (Prop_fdre_C_Q) 0.100 53.883 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/Q
net (fo=30, routed) 0.204 54.087 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/p_0_in
SLICE_X14Y43 FDCE f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk0 fall edge) 48.302 48.302 f
AA10 0.000 48.302 f sns1_clkp (IN)
net (fo=0) 0.000 48.302 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns1_clkp
AA10 IBUFDS (Prop_ibufds_I_O) 0.481 48.784 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.593 49.377 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.053 49.430 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 0.490 49.920 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y1 BUFR (Prop_bufr_I_O) 0.093 50.013 f sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.345 50.358 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X14Y43 FDCE r sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
clock pessimism -0.178 50.179
clock uncertainty 0.276 50.456
SLICE_X14Y43 FDCE (Remov_fdce_C_CLR) -0.044 50.412 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg
-------------------------------------------------------------------
required time -50.412
arrival time 54.087
-------------------------------------------------------------------
slack 3.676
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: iclk1
To Clock: iclk1
Setup : 0 Failing Endpoints, Worst Slack 35.328ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.486ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 35.328ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/C
(rising edge-triggered cell FDPE clocked by iclk1 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/CLR
(recovery check against rising-edge clock iclk1 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 37.037ns (iclk1 rise@66.821ns - iclk1 rise@29.784ns)
Data Path Delay: 1.277ns (logic 0.269ns (21.063%) route 1.008ns (78.937%))
Logic Levels: 0
Clock Path Skew: -0.084ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.797ns = ( 72.618 - 66.821 )
Source Clock Delay (SCD): 6.511ns = ( 36.295 - 29.784 )
Clock Pessimism Removal (CPR): 0.630ns
Clock Uncertainty: 0.156ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1 rise edge) 29.784 29.784 r
Y16 0.000 29.784 r sns2_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.857 30.641 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 2.173 32.814 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.088 32.902 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.633 34.535 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.120 34.655 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 1.640 36.295 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/pclk_r_reg
SLICE_X28Y17 FDPE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X28Y17 FDPE (Prop_fdpe_C_Q) 0.269 36.564 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/Q
net (fo=111, routed) 1.008 37.572 sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/Q[0]
SLICE_X38Y16 FDCE f sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk1 rise edge) 66.821 66.821 r
Y16 0.000 66.821 r sns2_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.779 67.600 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.801 69.400 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.083 69.483 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.550 71.033 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.113 71.146 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 1.472 72.618 sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/den_r_reg
SLICE_X38Y16 FDCE r sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/C
clock pessimism 0.630 73.248
clock uncertainty -0.156 73.092
SLICE_X38Y16 FDCE (Recov_fdce_C_CLR) -0.192 72.900 sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg
-------------------------------------------------------------------
required time 72.900
arrival time -37.572
-------------------------------------------------------------------
slack 35.328
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.486ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/C
(rising edge-triggered cell FDPE clocked by iclk1 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg/CLR
(removal check against rising-edge clock iclk1 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (iclk1 rise@29.784ns - iclk1 rise@29.784ns)
Data Path Delay: 0.441ns (logic 0.100ns (22.677%) route 0.341ns (77.324%))
Logic Levels: 0
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 3.175ns = ( 32.959 - 29.784 )
Source Clock Delay (SCD): 2.643ns = ( 32.427 - 29.784 )
Clock Pessimism Removal (CPR): 0.527ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1 rise edge) 29.784 29.784 r
Y16 0.000 29.784 r sns2_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.360 30.144 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.000 31.143 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.050 31.193 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.584 31.777 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.026 31.803 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.624 32.427 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/pclk_r_reg
SLICE_X28Y17 FDPE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X28Y17 FDPE (Prop_fdpe_C_Q) 0.100 32.527 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/Q
net (fo=111, routed) 0.341 32.868 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/Q[0]
SLICE_X32Y12 FDCE f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk1 rise edge) 29.784 29.784 r
Y16 0.000 29.784 r sns2_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.428 30.212 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.196 31.408 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.053 31.461 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.651 32.112 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.030 32.142 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.817 32.959 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/den_r_reg
SLICE_X32Y12 FDCE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg/C
clock pessimism -0.527 32.432
SLICE_X32Y12 FDCE (Remov_fdce_C_CLR) -0.050 32.382 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg
-------------------------------------------------------------------
required time -32.382
arrival time 32.868
-------------------------------------------------------------------
slack 0.486
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: iclk1x1
To Clock: iclk1
Setup : 0 Failing Endpoints, Worst Slack 2.093ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 3.530ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.093ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
(rising edge-triggered cell FDRE clocked by iclk1x1 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
(recovery check against rising-edge clock iclk1 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 3.704ns (iclk1 fall@11.265ns - iclk1x1 rise@7.562ns)
Data Path Delay: 0.879ns (logic 0.308ns (35.026%) route 0.571ns (64.974%))
Logic Levels: 0
Clock Path Skew: -0.202ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.864ns = ( 17.130 - 11.265 )
Source Clock Delay (SCD): 6.522ns = ( 14.084 - 7.562 )
Clock Pessimism Removal (CPR): 0.456ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x1 rise edge) 7.562 7.562 r
Y16 0.000 7.562 r sns2_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.857 8.419 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 2.173 10.592 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.088 10.680 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 1.633 12.313 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y3 BUFG (Prop_bufg_I_O) 0.120 12.433 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 1.651 14.084 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X14Y14 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X14Y14 FDRE (Prop_fdre_C_Q) 0.308 14.392 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/Q
net (fo=30, routed) 0.571 14.963 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/p_0_in
SLICE_X13Y14 FDCE f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk1 fall edge) 11.265 11.265 f
Y16 0.000 11.265 f sns2_clkp (IN)
net (fo=0) 0.000 11.265 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.779 12.044 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.801 13.845 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.083 13.928 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.550 15.478 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.113 15.591 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 1.539 17.130 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X13Y14 FDCE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
clock pessimism 0.456 17.585
clock uncertainty -0.276 17.309
SLICE_X13Y14 FDCE (Recov_fdce_C_CLR) -0.253 17.056 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg
-------------------------------------------------------------------
required time 17.056
arrival time -14.963
-------------------------------------------------------------------
slack 2.093
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 3.530ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
(rising edge-triggered cell FDRE clocked by iclk1x1 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
(removal check against rising-edge clock iclk1 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: -3.704ns (iclk1 fall@48.302ns - iclk1x1 rise@52.006ns)
Data Path Delay: 0.332ns (logic 0.118ns (35.505%) route 0.214ns (64.495%))
Logic Levels: 0
Clock Path Skew: 0.291ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 3.210ns = ( 51.512 - 48.302 )
Source Clock Delay (SCD): 2.651ns = ( 54.657 - 52.006 )
Clock Pessimism Removal (CPR): 0.268ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x1 rise edge) 52.006 52.006 r
Y16 0.000 52.006 r sns2_clkp (IN)
net (fo=0) 0.000 52.006 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.360 52.366 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.000 53.365 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.050 53.415 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 0.584 53.999 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y3 BUFG (Prop_bufg_I_O) 0.026 54.025 r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.632 54.657 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X14Y14 FDRE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X14Y14 FDRE (Prop_fdre_C_Q) 0.118 54.775 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/Q
net (fo=30, routed) 0.214 54.990 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/p_0_in
SLICE_X13Y14 FDCE f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk1 fall edge) 48.302 48.302 f
Y16 0.000 48.302 f sns2_clkp (IN)
net (fo=0) 0.000 48.302 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns2_clkp
Y16 IBUFDS (Prop_ibufds_I_O) 0.428 48.731 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.196 49.926 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.053 49.979 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.651 50.630 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.030 50.660 f sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.852 51.512 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X13Y14 FDCE r sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
clock pessimism -0.268 51.245
clock uncertainty 0.276 51.521
SLICE_X13Y14 FDCE (Remov_fdce_C_CLR) -0.061 51.460 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg
-------------------------------------------------------------------
required time -51.460
arrival time 54.990
-------------------------------------------------------------------
slack 3.530
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: iclk1x2
To Clock: iclk2
Setup : 0 Failing Endpoints, Worst Slack 2.279ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 3.700ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.279ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
(rising edge-triggered cell FDRE clocked by iclk1x2 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
(recovery check against rising-edge clock iclk2 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 3.704ns (iclk2 fall@11.265ns - iclk1x2 rise@7.562ns)
Data Path Delay: 0.755ns (logic 0.308ns (40.786%) route 0.447ns (59.214%))
Logic Levels: 0
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.773ns = ( 15.038 - 11.265 )
Source Clock Delay (SCD): 4.195ns = ( 11.757 - 7.562 )
Clock Pessimism Removal (CPR): 0.282ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x2 rise edge) 7.562 7.562 r
T21 0.000 7.562 r sns3_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.880 8.441 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.085 9.527 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.088 9.615 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.106 10.721 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y4 BUFR (Prop_bufr_I_O) 0.377 11.098 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.659 11.757 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X6Y64 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X6Y64 FDRE (Prop_fdre_C_Q) 0.308 12.065 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/Q
net (fo=30, routed) 0.447 12.512 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/p_0_in
SLICE_X7Y64 FDCE f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk2 fall edge) 11.265 11.265 f
T21 0.000 11.265 f sns3_clkp (IN)
net (fo=0) 0.000 11.265 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.801 12.066 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.887 12.953 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.083 13.036 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 1.016 14.052 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y5 BUFR (Prop_bufr_I_O) 0.370 14.422 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.616 15.038 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X7Y64 FDCE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
clock pessimism 0.282 15.320
clock uncertainty -0.276 15.044
SLICE_X7Y64 FDCE (Recov_fdce_C_CLR) -0.253 14.791 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg
-------------------------------------------------------------------
required time 14.791
arrival time -12.512
-------------------------------------------------------------------
slack 2.279
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 3.700ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
(rising edge-triggered cell FDRE clocked by iclk1x2 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
(removal check against rising-edge clock iclk2 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: -3.704ns (iclk2 fall@48.302ns - iclk1x2 rise@52.006ns)
Data Path Delay: 0.307ns (logic 0.118ns (38.417%) route 0.189ns (61.583%))
Logic Levels: 0
Clock Path Skew: 0.096ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.988ns = ( 50.290 - 48.302 )
Source Clock Delay (SCD): 1.714ns = ( 53.720 - 52.006 )
Clock Pessimism Removal (CPR): 0.178ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x2 rise edge) 52.006 52.006 r
T21 0.000 52.006 r sns3_clkp (IN)
net (fo=0) 0.000 52.006 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.382 52.388 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.487 52.875 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.050 52.925 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.433 53.358 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFR_X0Y4 BUFR (Prop_bufr_I_O) 0.090 53.448 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.272 53.720 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X6Y64 FDRE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X6Y64 FDRE (Prop_fdre_C_Q) 0.118 53.838 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/Q
net (fo=30, routed) 0.189 54.027 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/p_0_in
SLICE_X7Y64 FDCE f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk2 fall edge) 48.302 48.302 f
T21 0.000 48.302 f sns3_clkp (IN)
net (fo=0) 0.000 48.302 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.451 48.753 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.593 49.346 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.053 49.399 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 0.490 49.889 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y5 BUFR (Prop_bufr_I_O) 0.093 49.982 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.308 50.290 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X7Y64 FDCE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
clock pessimism -0.178 50.112
clock uncertainty 0.276 50.388
SLICE_X7Y64 FDCE (Remov_fdce_C_CLR) -0.061 50.327 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg
-------------------------------------------------------------------
required time -50.327
arrival time 54.027
-------------------------------------------------------------------
slack 3.700
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: iclk2
To Clock: iclk2
Setup : 0 Failing Endpoints, Worst Slack 33.682ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.517ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 33.682ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/C
(rising edge-triggered cell FDPE clocked by iclk2 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg/CLR
(recovery check against rising-edge clock iclk2 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 37.037ns (iclk2 rise@66.821ns - iclk2 rise@29.784ns)
Data Path Delay: 2.971ns (logic 0.269ns (9.055%) route 2.702ns (90.945%))
Logic Levels: 0
Clock Path Skew: 0.027ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.893ns = ( 70.714 - 66.821 )
Source Clock Delay (SCD): 4.245ns = ( 34.029 - 29.784 )
Clock Pessimism Removal (CPR): 0.379ns
Clock Uncertainty: 0.156ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk2 rise edge) 29.784 29.784 r
T21 0.000 29.784 r sns3_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.880 30.664 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.085 31.749 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.088 31.837 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 1.106 32.943 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y5 BUFR (Prop_bufr_I_O) 0.377 33.320 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.709 34.029 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/pclk_r_reg
SLICE_X15Y70 FDPE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X15Y70 FDPE (Prop_fdpe_C_Q) 0.269 34.298 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/Q
net (fo=111, routed) 2.702 36.999 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/Q[0]
SLICE_X33Y50 FDCE f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk2 rise edge) 66.821 66.821 r
T21 0.000 66.821 r sns3_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.801 67.622 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.887 68.509 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.083 68.592 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 1.016 69.608 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y5 BUFR (Prop_bufr_I_O) 0.370 69.978 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.736 70.714 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/rst_early_master_reg
SLICE_X33Y50 FDCE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg/C
clock pessimism 0.379 71.093
clock uncertainty -0.156 70.936
SLICE_X33Y50 FDCE (Recov_fdce_C_CLR) -0.255 70.681 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg
-------------------------------------------------------------------
required time 70.681
arrival time -36.999
-------------------------------------------------------------------
slack 33.682
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.517ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/C
(rising edge-triggered cell FDPE clocked by iclk2 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[2].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/CLR
(removal check against rising-edge clock iclk2 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (iclk2 rise@29.784ns - iclk2 rise@29.784ns)
Data Path Delay: 0.464ns (logic 0.100ns (21.562%) route 0.364ns (78.438%))
Logic Levels: 0
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.018ns = ( 31.802 - 29.784 )
Source Clock Delay (SCD): 1.738ns = ( 31.522 - 29.784 )
Clock Pessimism Removal (CPR): 0.264ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk2 rise edge) 29.784 29.784 r
T21 0.000 29.784 r sns3_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.382 30.166 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.487 30.653 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.050 30.703 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 0.433 31.136 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y5 BUFR (Prop_bufr_I_O) 0.090 31.226 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.296 31.522 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/pclk_r_reg
SLICE_X15Y70 FDPE r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X15Y70 FDPE (Prop_fdpe_C_Q) 0.100 31.622 f sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/Q
net (fo=111, routed) 0.364 31.985 sensors393_i/sensor_channel_block[2].sensor_channel_i/pulse_cross_clock_eof_mclk_i/Q[0]
SLICE_X13Y66 FDCE f sensors393_i/sensor_channel_block[2].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk2 rise edge) 29.784 29.784 r
T21 0.000 29.784 r sns3_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns3_clkp
T21 IBUFDS (Prop_ibufds_I_O) 0.451 30.235 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.593 30.828 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.053 30.881 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/CLKOUT0
net (fo=1, routed) 0.490 31.371 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFR_X0Y5 BUFR (Prop_bufr_I_O) 0.093 31.464 r sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.338 31.802 sensors393_i/sensor_channel_block[2].sensor_channel_i/pulse_cross_clock_eof_mclk_i/rst_early_master_reg
SLICE_X13Y66 FDCE r sensors393_i/sensor_channel_block[2].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/C
clock pessimism -0.264 31.538
SLICE_X13Y66 FDCE (Remov_fdce_C_CLR) -0.069 31.469 sensors393_i/sensor_channel_block[2].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg
-------------------------------------------------------------------
required time -31.469
arrival time 31.985
-------------------------------------------------------------------
slack 0.517
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: iclk1x3
To Clock: iclk3
Setup : 0 Failing Endpoints, Worst Slack 2.272ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 3.482ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.272ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
(rising edge-triggered cell FDRE clocked by iclk1x3 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
(recovery check against rising-edge clock iclk3 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 3.704ns (iclk3 fall@11.265ns - iclk1x3 rise@7.562ns)
Data Path Delay: 0.690ns (logic 0.269ns (38.975%) route 0.421ns (61.025%))
Logic Levels: 0
Clock Path Skew: -0.212ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.452ns = ( 16.718 - 11.265 )
Source Clock Delay (SCD): 6.008ns = ( 13.570 - 7.562 )
Clock Pessimism Removal (CPR): 0.344ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x3 rise edge) 7.562 7.562 r
R16 0.000 7.562 r sns4_clkp (IN)
net (fo=0) 0.000 7.562 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.856 8.417 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.502 9.919 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.088 10.007 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 2.009 12.016 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.120 12.136 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 1.434 13.570 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X28Y75 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X28Y75 FDRE (Prop_fdre_C_Q) 0.269 13.839 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/Q
net (fo=30, routed) 0.421 14.260 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/p_0_in
SLICE_X29Y75 FDCE f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk3 fall edge) 11.265 11.265 f
R16 0.000 11.265 f sns4_clkp (IN)
net (fo=0) 0.000 11.265 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.777 12.042 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.242 13.284 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.083 13.367 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.911 15.278 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y12 BUFG (Prop_bufg_I_O) 0.113 15.391 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 1.327 16.718 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X29Y75 FDCE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
clock pessimism 0.344 17.062
clock uncertainty -0.276 16.785
SLICE_X29Y75 FDCE (Recov_fdce_C_CLR) -0.253 16.532 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg
-------------------------------------------------------------------
required time 16.532
arrival time -14.260
-------------------------------------------------------------------
slack 2.272
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 3.482ns (arrival time - required time)
Source: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
(rising edge-triggered cell FDRE clocked by iclk1x3 {rise@-7.253ns fall@0.154ns period=14.815ns})
Destination: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
(removal check against rising-edge clock iclk3 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: -3.704ns (iclk3 fall@48.302ns - iclk1x3 rise@52.006ns)
Data Path Delay: 0.263ns (logic 0.100ns (37.996%) route 0.163ns (62.004%))
Logic Levels: 0
Clock Path Skew: 0.270ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.951ns = ( 51.254 - 48.302 )
Source Clock Delay (SCD): 2.470ns = ( 54.476 - 52.006 )
Clock Pessimism Removal (CPR): 0.211ns
Clock Uncertainty: 0.276ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.120ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk1x3 rise edge) 52.006 52.006 r
R16 0.000 52.006 r sns4_clkp (IN)
net (fo=0) 0.000 52.006 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.358 52.364 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.701 53.064 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
0.050 53.114 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT2
net (fo=1, routed) 0.771 53.885 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre
BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) 0.026 53.911 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk1x_i/O
net (fo=58, routed) 0.565 54.476 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/CLK
SLICE_X28Y75 FDRE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X28Y75 FDRE (Prop_fdre_C_Q) 0.100 54.576 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/iclk_r_reg[0]/Q
net (fo=30, routed) 0.163 54.740 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/p_0_in
SLICE_X29Y75 FDCE f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk3 fall edge) 48.302 48.302 f
R16 0.000 48.302 f sns4_clkp (IN)
net (fo=0) 0.000 48.302 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.427 48.729 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.840 49.569 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.053 49.622 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.840 50.462 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y12 BUFG (Prop_bufg_I_O) 0.030 50.492 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.762 51.254 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg_0
SLICE_X29Y75 FDCE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg/C (IS_INVERTED)
clock pessimism -0.211 51.043
clock uncertainty 0.276 51.319
SLICE_X29Y75 FDCE (Remov_fdce_C_CLR) -0.061 51.258 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_r_reg
-------------------------------------------------------------------
required time -51.258
arrival time 54.740
-------------------------------------------------------------------
slack 3.482
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: iclk3
To Clock: iclk3
Setup : 0 Failing Endpoints, Worst Slack 34.122ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.445ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 34.122ns (required time - arrival time)
Source: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/C
(rising edge-triggered cell FDPE clocked by iclk3 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg/CLR
(recovery check against rising-edge clock iclk3 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 37.037ns (iclk3 rise@66.821ns - iclk3 rise@29.784ns)
Data Path Delay: 2.593ns (logic 0.308ns (11.880%) route 2.285ns (88.120%))
Logic Levels: 0
Clock Path Skew: 0.089ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.591ns = ( 72.412 - 66.821 )
Source Clock Delay (SCD): 5.961ns = ( 35.745 - 29.784 )
Clock Pessimism Removal (CPR): 0.459ns
Clock Uncertainty: 0.156ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.304ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk3 rise edge) 29.784 29.784 r
R16 0.000 29.784 r sns4_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.856 30.639 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.502 32.141 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.088 32.229 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 2.009 34.238 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y12 BUFG (Prop_bufg_I_O) 0.120 34.358 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 1.387 35.745 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/pclk_r_reg
SLICE_X36Y67 FDPE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X36Y67 FDPE (Prop_fdpe_C_Q) 0.308 36.053 f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/prst_with_sens_mrst_reg[0]/Q
net (fo=111, routed) 2.285 38.338 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/Q[0]
SLICE_X41Y28 FDCE f sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk3 rise edge) 66.821 66.821 r
R16 0.000 66.821 r sns4_clkp (IN)
net (fo=0) 0.000 66.821 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.777 67.598 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 1.242 68.839 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.083 68.922 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.911 70.833 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y12 BUFG (Prop_bufg_I_O) 0.113 70.946 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 1.466 72.412 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/den_r_reg
SLICE_X41Y28 FDCE r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg/C
clock pessimism 0.459 72.871
clock uncertainty -0.156 72.715
SLICE_X41Y28 FDCE (Recov_fdce_C_CLR) -0.255 72.460 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg
-------------------------------------------------------------------
required time 72.460
arrival time -38.338
-------------------------------------------------------------------
slack 34.122
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.445ns (arrival time - required time)
Source: sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/C
(rising edge-triggered cell FDRE clocked by iclk3 {rise@-7.253ns fall@11.265ns period=37.037ns})
Destination: sensors393_i/sensor_channel_block[3].sensor_membuf_i/page_written_i/in_reg_reg/CLR
(removal check against rising-edge clock iclk3 {rise@-7.253ns fall@11.265ns period=37.037ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (iclk3 rise@29.784ns - iclk3 rise@29.784ns)
Data Path Delay: 0.412ns (logic 0.100ns (24.296%) route 0.312ns (75.705%))
Logic Levels: 0
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.934ns = ( 32.718 - 29.784 )
Source Clock Delay (SCD): 2.446ns = ( 32.230 - 29.784 )
Clock Pessimism Removal (CPR): 0.452ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock iclk3 rise edge) 29.784 29.784 r
R16 0.000 29.784 r sns4_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.358 30.142 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.701 30.842 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.050 30.892 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.771 31.663 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y12 BUFG (Prop_bufg_I_O) 0.026 31.689 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.541 32.230 sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/pclk[0]
SLICE_X37Y68 FDRE r sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/C
------------------------------------------------------------------- -------------------
SLICE_X37Y68 FDRE (Prop_fdre_C_Q) 0.100 32.330 f sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/Q
net (fo=22, routed) 0.312 32.642 sensors393_i/sensor_channel_block[3].sensor_membuf_i/page_written_i/rst[0]
SLICE_X47Y60 FDCE f sensors393_i/sensor_channel_block[3].sensor_membuf_i/page_written_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock iclk3 rise edge) 29.784 29.784 r
R16 0.000 29.784 r sns4_clkp (IN)
net (fo=0) 0.000 29.784 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/sns4_clkp
R16 IBUFDS (Prop_ibufds_I_O) 0.427 30.210 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/IBUFDS_i/O
net (fo=1, routed) 0.840 31.050 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/clk_in
PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.053 31.103 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/mmcm_or_pll_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.840 31.943 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre
BUFGCTRL_X0Y12 BUFG (Prop_bufg_I_O) 0.030 31.973 r sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/clk2x_i__0/O
net (fo=1176, routed) 0.745 32.718 sensors393_i/sensor_channel_block[3].sensor_membuf_i/page_written_i/CLK
SLICE_X47Y60 FDCE r sensors393_i/sensor_channel_block[3].sensor_membuf_i/page_written_i/in_reg_reg/C
clock pessimism -0.452 32.266
SLICE_X47Y60 FDCE (Remov_fdce_C_CLR) -0.069 32.197 sensors393_i/sensor_channel_block[3].sensor_membuf_i/page_written_i/in_reg_reg
-------------------------------------------------------------------
required time -32.197
arrival time 32.642
-------------------------------------------------------------------
slack 0.445
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: sclk
To Clock: sclk
Setup : 0 Failing Endpoints, Worst Slack 5.990ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.396ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 5.990ns (required time - arrival time)
Source: timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/sync_zer_reg[1]/C
(rising edge-triggered cell FDRE clocked by sclk {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: timing393_i/camsync393_i/i_ts_snap_mclk0/in_reg_reg/CLR
(recovery check against rising-edge clock sclk {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 10.000ns (sclk rise@10.000ns - sclk rise@0.000ns)
Data Path Delay: 3.381ns (logic 0.439ns (12.985%) route 2.942ns (87.015%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: -0.299ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.540ns = ( 14.540 - 10.000 )
Source Clock Delay (SCD): 5.078ns
Clock Pessimism Removal (CPR): 0.239ns
Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.133ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sclk rise edge) 0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.610 1.610 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
0.088 1.698 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
net (fo=1, routed) 1.621 3.319 clocks393_i/sync_clk_i/sync_clk_pre
BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.120 3.439 r clocks393_i/sync_clk_i/clk1x_i/O
net (fo=1449, routed) 1.639 5.078 timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/camsync_clk
SLICE_X106Y153 FDRE r timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/sync_zer_reg[1]/C
------------------------------------------------------------------- -------------------
SLICE_X106Y153 FDRE (Prop_fdre_C_Q) 0.282 5.360 r timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/sync_zer_reg[1]/Q
net (fo=3, routed) 0.487 5.847 sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/sync_zer_reg[1]_0[0]
SLICE_X106Y152 LUT2 (Prop_lut2_I1_O) 0.157 6.004 f sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/in_reg_i_1__119/O
net (fo=33, routed) 2.455 8.459 timing393_i/camsync393_i/i_ts_snap_mclk0/regs_reg[4]
SLICE_X101Y134 FDCE f timing393_i/camsync393_i/i_ts_snap_mclk0/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock sclk rise edge) 10.000 10.000 r
BUFGCTRL_X0Y17 BUFG 0.000 10.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.476 11.476 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
0.083 11.559 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
net (fo=1, routed) 1.538 13.097 clocks393_i/sync_clk_i/sync_clk_pre
BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.113 13.210 r clocks393_i/sync_clk_i/clk1x_i/O
net (fo=1449, routed) 1.330 14.540 timing393_i/camsync393_i/i_ts_snap_mclk0/camsync_clk
SLICE_X101Y134 FDCE r timing393_i/camsync393_i/i_ts_snap_mclk0/in_reg_reg/C
clock pessimism 0.239 14.779
clock uncertainty -0.075 14.704
SLICE_X101Y134 FDCE (Recov_fdce_C_CLR) -0.255 14.449 timing393_i/camsync393_i/i_ts_snap_mclk0/in_reg_reg
-------------------------------------------------------------------
required time 14.449
arrival time -8.459
-------------------------------------------------------------------
slack 5.990
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.396ns (arrival time - required time)
Source: sync_resets_i/rst_block[7].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/C
(rising edge-triggered cell FDRE clocked by sclk {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/CLR
(removal check against rising-edge clock sclk {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (sclk rise@0.000ns - sclk rise@0.000ns)
Data Path Delay: 0.319ns (logic 0.091ns (28.526%) route 0.228ns (71.474%))
Logic Levels: 0
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.403ns
Source Clock Delay (SCD): 1.894ns
Clock Pessimism Removal (CPR): 0.498ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sclk rise edge) 0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.604 0.604 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
0.050 0.654 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
net (fo=1, routed) 0.577 1.231 clocks393_i/sync_clk_i/sync_clk_pre
BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.026 1.257 r clocks393_i/sync_clk_i/clk1x_i/O
net (fo=1449, routed) 0.637 1.894 sync_resets_i/rst_block[7].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/camsync_clk
SLICE_X105Y175 FDRE r sync_resets_i/rst_block[7].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/C
------------------------------------------------------------------- -------------------
SLICE_X105Y175 FDRE (Prop_fdre_C_Q) 0.091 1.985 f sync_resets_i/rst_block[7].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/Q
net (fo=3, routed) 0.228 2.213 timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/rst[0]
SLICE_X104Y175 FDCE f timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/CLR
------------------------------------------------------------------- -------------------
(clock sclk rise edge) 0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.816 0.816 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
0.053 0.869 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
net (fo=1, routed) 0.643 1.512 clocks393_i/sync_clk_i/sync_clk_pre
BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.030 1.542 r clocks393_i/sync_clk_i/clk1x_i/O
net (fo=1449, routed) 0.861 2.403 timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/camsync_clk
SLICE_X104Y175 FDCE r timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/C
clock pessimism -0.498 1.905
SLICE_X104Y175 FDCE (Remov_fdce_C_CLR) -0.088 1.817 timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg
-------------------------------------------------------------------
required time -1.817
arrival time 2.213
-------------------------------------------------------------------
slack 0.396
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: usrclk2
To Clock: usrclk2
Setup : 0 Failing Endpoints, Worst Slack 4.953ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.715ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 4.953ns (required time - arrival time)
Source: sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/C
(rising edge-triggered cell FDCE clocked by usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns})
Destination: sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/CLR
(recovery check against rising-edge clock usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 13.333ns (usrclk2 rise@13.333ns - usrclk2 rise@0.000ns)
Data Path Delay: 7.957ns (logic 0.375ns (4.713%) route 7.582ns (95.287%))
Logic Levels: 2 (LUT2=1 LUT3=1)
Clock Path Skew: -0.133ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.038ns = ( 16.371 - 13.333 )
Source Clock Delay (SCD): 3.465ns
Clock Pessimism Removal (CPR): 0.294ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock usrclk2 rise edge) 0.000 0.000 r
SLICE_X65Y49 FDRE 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
net (fo=2, routed) 1.941 1.941 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.120 2.061 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
net (fo=2023, routed) 1.404 3.465 sata_top/ahci_sata_layers_i/phy/rxdata_reg[0]__0
SLICE_X77Y50 FDCE r sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/C
------------------------------------------------------------------- -------------------
SLICE_X77Y50 FDCE (Prop_fdce_C_Q) 0.269 3.734 r sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/Q
net (fo=8, routed) 0.467 4.201 sata_top/ahci_sata_layers_i/phy/sata_reset_done
SLICE_X77Y50 LUT3 (Prop_lut3_I2_O) 0.053 4.254 f sata_top/ahci_sata_layers_i/phy/was_rst_i_1/O
net (fo=278, routed) 6.275 10.529 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/sata_reset_done_r_reg[0]
SLICE_X43Y136 LUT2 (Prop_lut2_I1_O) 0.053 10.582 f sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/dout_vld_r[1]_i_1/O
net (fo=15, routed) 0.840 11.422 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/abort_busy_mclk_reg
SLICE_X39Y138 FDCE f sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock usrclk2 rise edge) 13.333 13.333 r
SLICE_X65Y49 FDRE 0.000 13.333 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
net (fo=2, routed) 1.654 14.987 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.113 15.100 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
net (fo=2023, routed) 1.271 16.371 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/usrclk2_r_reg
SLICE_X39Y138 FDCE r sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/C
clock pessimism 0.294 16.665
clock uncertainty -0.035 16.630
SLICE_X39Y138 FDCE (Recov_fdce_C_CLR) -0.255 16.375 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg
-------------------------------------------------------------------
required time 16.375
arrival time -11.422
-------------------------------------------------------------------
slack 4.953
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.715ns (arrival time - required time)
Source: sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/C
(rising edge-triggered cell FDRE clocked by usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns})
Destination: sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/init_confirm_i/in_reg_reg/CLR
(removal check against rising-edge clock usrclk2 {rise@0.000ns fall@6.666ns period=13.333ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (usrclk2 rise@0.000ns - usrclk2 rise@0.000ns)
Data Path Delay: 0.675ns (logic 0.128ns (18.956%) route 0.547ns (81.044%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: 0.029ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.812ns
Source Clock Delay (SCD): 1.453ns
Clock Pessimism Removal (CPR): 0.330ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock usrclk2 rise edge) 0.000 0.000 r
SLICE_X65Y49 FDRE 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
net (fo=2, routed) 0.897 0.897 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 0.923 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
net (fo=2023, routed) 0.530 1.453 sata_top/ahci_top_i/ahci_dma_i/usrclk2_r_reg
SLICE_X45Y138 FDRE r sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/C
------------------------------------------------------------------- -------------------
SLICE_X45Y138 FDRE (Prop_fdre_C_Q) 0.100 1.553 f sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/Q
net (fo=18, routed) 0.227 1.780 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/abort_busy_mclk_reg
SLICE_X43Y136 LUT2 (Prop_lut2_I0_O) 0.028 1.808 f sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/dout_vld_r[1]_i_1/O
net (fo=15, routed) 0.320 2.128 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/init_confirm_i/SR[0]
SLICE_X40Y133 FDCE f sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/init_confirm_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock usrclk2 rise edge) 0.000 0.000 r
SLICE_X65Y49 FDRE 0.000 0.000 r sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
net (fo=2, routed) 1.050 1.050 sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.080 r sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
net (fo=2023, routed) 0.732 1.812 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/init_confirm_i/usrclk2_r_reg
SLICE_X40Y133 FDCE r sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/init_confirm_i/in_reg_reg/C
clock pessimism -0.330 1.482
SLICE_X40Y133 FDCE (Remov_fdce_C_CLR) -0.069 1.413 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/init_confirm_i/in_reg_reg
-------------------------------------------------------------------
required time -1.413
arrival time 2.128
-------------------------------------------------------------------
slack 0.715
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: xclk
To Clock: xclk
Setup : 0 Failing Endpoints, Worst Slack 1.004ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.398ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 1.004ns (required time - arrival time)
Source: compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/cmprs_en_xclk_jp_reg/C
(rising edge-triggered cell FDRE clocked by xclk {rise@0.000ns fall@2.083ns period=4.167ns})
Destination: compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/flush_clk_i/in_reg_reg/CLR
(recovery check against rising-edge clock xclk {rise@0.000ns fall@2.083ns period=4.167ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 4.167ns (xclk rise@4.167ns - xclk rise@0.000ns)
Data Path Delay: 2.598ns (logic 0.322ns (12.395%) route 2.276ns (87.605%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.306ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.547ns = ( 8.714 - 4.167 )
Source Clock Delay (SCD): 5.092ns
Clock Pessimism Removal (CPR): 0.239ns
Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.114ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock xclk rise edge) 0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.610 1.610 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
0.088 1.698 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
net (fo=1, routed) 1.621 3.319 clocks393_i/xclk_i/xclk_pre
BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.120 3.439 r clocks393_i/xclk_i/clk1x_i/O
net (fo=13491, routed) 1.653 5.092 compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/xclk
SLICE_X103Y44 FDRE r compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/cmprs_en_xclk_jp_reg/C
------------------------------------------------------------------- -------------------
SLICE_X103Y44 FDRE (Prop_fdre_C_Q) 0.269 5.361 r compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/cmprs_en_xclk_jp_reg/Q
net (fo=122, routed) 0.575 5.936 compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/frame_en_jp
SLICE_X98Y40 LUT1 (Prop_lut1_I0_O) 0.053 5.989 f compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/mb_first_in_row_i_1__1/O
net (fo=275, routed) 1.701 7.690 compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/flush_clk_i/clear
SLICE_X102Y72 FDCE f compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/flush_clk_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock xclk rise edge) 4.167 4.167 r
BUFGCTRL_X0Y17 BUFG 0.000 4.167 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.476 5.643 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
0.083 5.726 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
net (fo=1, routed) 1.538 7.264 clocks393_i/xclk_i/xclk_pre
BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.113 7.377 r clocks393_i/xclk_i/clk1x_i/O
net (fo=13491, routed) 1.337 8.714 compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/flush_clk_i/xclk
SLICE_X102Y72 FDCE r compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/flush_clk_i/in_reg_reg/C
clock pessimism 0.239 8.953
clock uncertainty -0.067 8.885
SLICE_X102Y72 FDCE (Recov_fdce_C_CLR) -0.192 8.693 compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/flush_clk_i/in_reg_reg
-------------------------------------------------------------------
required time 8.693
arrival time -7.690
-------------------------------------------------------------------
slack 1.004
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.398ns (arrival time - required time)
Source: sync_resets_i/rst_block[5].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/C
(rising edge-triggered cell FDRE clocked by xclk {rise@0.000ns fall@2.083ns period=4.167ns})
Destination: compressor393_i/cmprs_channel_block[0].jp_channel_i/stuffer_done_mclk_i/in_reg_reg/CLR
(removal check against rising-edge clock xclk {rise@0.000ns fall@2.083ns period=4.167ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (xclk rise@0.000ns - xclk rise@0.000ns)
Data Path Delay: 0.362ns (logic 0.100ns (27.659%) route 0.262ns (72.341%))
Logic Levels: 0
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.293ns
Source Clock Delay (SCD): 1.807ns
Clock Pessimism Removal (CPR): 0.453ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock xclk rise edge) 0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.604 0.604 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
0.050 0.654 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
net (fo=1, routed) 0.577 1.231 clocks393_i/xclk_i/xclk_pre
BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.257 r clocks393_i/xclk_i/clk1x_i/O
net (fo=13491, routed) 0.550 1.807 sync_resets_i/rst_block[5].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/CLK
SLICE_X79Y57 FDRE r sync_resets_i/rst_block[5].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/C
------------------------------------------------------------------- -------------------
SLICE_X79Y57 FDRE (Prop_fdre_C_Q) 0.100 1.907 f sync_resets_i/rst_block[5].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[4]/Q
net (fo=116, routed) 0.262 2.169 compressor393_i/cmprs_channel_block[0].jp_channel_i/stuffer_done_mclk_i/Q[0]
SLICE_X75Y53 FDCE f compressor393_i/cmprs_channel_block[0].jp_channel_i/stuffer_done_mclk_i/in_reg_reg/CLR
------------------------------------------------------------------- -------------------
(clock xclk rise edge) 0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.816 0.816 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
0.053 0.869 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
net (fo=1, routed) 0.643 1.512 clocks393_i/xclk_i/xclk_pre
BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.542 r clocks393_i/xclk_i/clk1x_i/O
net (fo=13491, routed) 0.751 2.293 compressor393_i/cmprs_channel_block[0].jp_channel_i/stuffer_done_mclk_i/xclk
SLICE_X75Y53 FDCE r compressor393_i/cmprs_channel_block[0].jp_channel_i/stuffer_done_mclk_i/in_reg_reg/C
clock pessimism -0.453 1.840
SLICE_X75Y53 FDCE (Remov_fdce_C_CLR) -0.069 1.771 compressor393_i/cmprs_channel_block[0].jp_channel_i/stuffer_done_mclk_i/in_reg_reg
-------------------------------------------------------------------
required time -1.771
arrival time 2.169
-------------------------------------------------------------------
slack 0.398