Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for f7c039856cce093f4cb94895355c64434d815788 Apr 26 - Mar 08

  • Total: 121 commits
  • Average per day: 0.4 commits
  • Authors: 1

Commits per day of month

Commits per weekday

Commits per day hour (UTC)