Programming languages used in this repository
-
Verilog
56.25 %
-
Python
29.11 %
-
HCL
7.27 %
-
SystemVerilog
6.82 %
-
Tcl
0.3 %
Commit statistics for f485624d6988670d6328b5b3fdd6390d3695d309 Apr 26 - Jul 03
- Total: 236 commits
- Average per day: 0.5 commits
- Authors: 1
Commits per day of month
Commits per weekday
Commits per day hour (UTC)