Programming languages used in this repository
-
Verilog
56.25 %
-
Python
29.11 %
-
HCL
7.27 %
-
SystemVerilog
6.82 %
-
Tcl
0.3 %
Commit statistics for f3cc7226a21f72470410e05aaf16ea4d8014449f Apr 26 - Sep 10
- Total: 339 commits
- Average per day: 0.7 commits
- Authors: 2
Commits per day of month
Commits per weekday
Commits per day hour (UTC)