Programming languages used in this repository
-
Verilog
56.25 %
-
Python
29.11 %
-
HCL
7.27 %
-
SystemVerilog
6.82 %
-
Tcl
0.3 %
Commit statistics for e9a79158cad5314f7a46059a63809d234c928fa5 Apr 26 - May 08
- Total: 13 commits
- Average per day: 1.0 commits
- Authors: 1
Commits per day of month
Commits per weekday
Commits per day hour (UTC)