Programming languages used in this repository
-
Verilog
56.25 %
-
Python
29.11 %
-
HCL
7.27 %
-
SystemVerilog
6.82 %
-
Tcl
0.3 %
Commit statistics for e79823dbc2043b1422cbdb70bbb3b3e15e120623 Apr 26 - Apr 27
- Total: 174 commits
- Average per day: 0.5 commits
- Authors: 1
Commits per day of month
Commits per weekday
Commits per day hour (UTC)