Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for de64188006061380d06bf6da3ea8d3aa5c0fb50b Apr 26 - Aug 15

  • Total: 300 commits
  • Average per day: 0.6 commits
  • Authors: 2

Commits per day of month

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Commits per day hour (UTC)