Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for cd341af85f78fce5a6677554ca3fe9fb6bcc552e Apr 26 - Aug 18

  • Total: 305 commits
  • Average per day: 0.6 commits
  • Authors: 2

Commits per day of month

Commits per weekday

Commits per day hour (UTC)