Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for cb75953f8ab4fb05bdd779876bd8e5c421af7ce1 Apr 26 - Mar 29

  • Total: 758 commits
  • Average per day: 0.4 commits
  • Authors: 5

Commits per day of month

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